106c3fb27SDimitry Andric//===- AArch64SchedPredNeoverse.td - AArch64 Sched Preds -----*- tablegen -*-===// 206c3fb27SDimitry Andric// 306c3fb27SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 406c3fb27SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 506c3fb27SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 606c3fb27SDimitry Andric// 706c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 806c3fb27SDimitry Andric// 906c3fb27SDimitry Andric// This file defines scheduling predicate definitions that are used by the 1006c3fb27SDimitry Andric// AArch64 Neoverse processors. 1106c3fb27SDimitry Andric// 1206c3fb27SDimitry Andric//===----------------------------------------------------------------------===// 1306c3fb27SDimitry Andric 1406c3fb27SDimitry Andric// Auxiliary predicates. 1506c3fb27SDimitry Andric 1606c3fb27SDimitry Andric// Check for LSL shift == 0 1706c3fb27SDimitry Andricdef NeoverseNoLSL : MCSchedPredicate< 1806c3fb27SDimitry Andric CheckAll<[CheckShiftLSL, 1906c3fb27SDimitry Andric CheckShiftBy0]>>; 2006c3fb27SDimitry Andric 2106c3fb27SDimitry Andric// Identify LDR/STR H/Q-form scaled (and potentially extended) FP instructions 2206c3fb27SDimitry Andricdef NeoverseHQForm : MCSchedPredicate< 2306c3fb27SDimitry Andric CheckAll<[ 2406c3fb27SDimitry Andric CheckAny<[CheckHForm, CheckQForm]>, 2506c3fb27SDimitry Andric CheckImmOperand<4, 1>]>>; 2606c3fb27SDimitry Andric 2706c3fb27SDimitry Andric// Check if <Pd> == <Pg> 2806c3fb27SDimitry Andricdef NeoversePdIsPgFn : TIIPredicate< 2906c3fb27SDimitry Andric "isNeoversePdSameAsPg", 3006c3fb27SDimitry Andric MCOpcodeSwitchStatement< 3106c3fb27SDimitry Andric [MCOpcodeSwitchCase<[BRKA_PPmP, BRKB_PPmP], 3206c3fb27SDimitry Andric MCReturnStatement<CheckSameRegOperand<1, 2>>>], 3306c3fb27SDimitry Andric MCReturnStatement<CheckSameRegOperand<0, 1>>>>; 3406c3fb27SDimitry Andricdef NeoversePdIsPg : MCSchedPredicate<NeoversePdIsPgFn>; 3506c3fb27SDimitry Andric 3606c3fb27SDimitry Andric// Check if SVE INC/DEC (scalar), ALL, {1, 2, 4} 3706c3fb27SDimitry Andricdef NeoverseCheapIncDec : MCSchedPredicate< 3806c3fb27SDimitry Andric CheckAll<[CheckOpcode<[ 3906c3fb27SDimitry Andric INCB_XPiI, INCH_XPiI, 4006c3fb27SDimitry Andric INCW_XPiI, INCD_XPiI, 4106c3fb27SDimitry Andric DECB_XPiI, DECH_XPiI, 4206c3fb27SDimitry Andric DECW_XPiI, DECD_XPiI]>, 4306c3fb27SDimitry Andric CheckImmOperand<2, 31>, 4406c3fb27SDimitry Andric CheckAny<[ 4506c3fb27SDimitry Andric CheckImmOperand<3, 1>, 4606c3fb27SDimitry Andric CheckImmOperand<3, 2>, 4706c3fb27SDimitry Andric CheckImmOperand<3, 4>]>]>>; 4806c3fb27SDimitry Andric 4906c3fb27SDimitry Andric// Identify "[SU]?(MADD|MSUB)L?" as the alias for "[SU]?(MUL|MNEG)L?". 5006c3fb27SDimitry Andricdef NeoverseMULIdiomPred : MCSchedPredicate< // <op> Rd, Rs, Rv, ZR 5106c3fb27SDimitry Andric CheckAll<[CheckOpcode< 5206c3fb27SDimitry Andric [MADDWrrr, MADDXrrr, 5306c3fb27SDimitry Andric MSUBWrrr, MSUBXrrr, 5406c3fb27SDimitry Andric SMADDLrrr, UMADDLrrr, 5506c3fb27SDimitry Andric SMSUBLrrr, UMSUBLrrr]>, 5606c3fb27SDimitry Andric CheckIsReg3Zero]>>; 575f757f3fSDimitry Andric 585f757f3fSDimitry Andricdef NeoverseZeroMove : MCSchedPredicate< 595f757f3fSDimitry Andric CheckAny<[ 605f757f3fSDimitry Andric // MOV Wd, #0 615f757f3fSDimitry Andric // MOV Xd, #0 625f757f3fSDimitry Andric CheckAll<[CheckOpcode<[MOVZWi, MOVZXi]>, 63*0fca6ea1SDimitry Andric CheckIsImmOperand<1>, 64*0fca6ea1SDimitry Andric CheckImmOperand<1, 0>, 65*0fca6ea1SDimitry Andric CheckImmOperand<2, 0>]>, 665f757f3fSDimitry Andric // MOV Wd, WZR 675f757f3fSDimitry Andric // MOV Xd, XZR 685f757f3fSDimitry Andric // MOV Wd, Wn 695f757f3fSDimitry Andric // MOV Xd, Xn 705f757f3fSDimitry Andric CheckAll<[CheckOpcode<[ORRWrs, ORRXrs]>, 715f757f3fSDimitry Andric CheckAll<[CheckIsReg1Zero, 725f757f3fSDimitry Andric CheckImmOperand<3, 0>]>]>, 735f757f3fSDimitry Andric // FMOV Hd, WZR 745f757f3fSDimitry Andric // FMOV Hd, XZR 755f757f3fSDimitry Andric // FMOV Sd, WZR 765f757f3fSDimitry Andric // FMOV Dd, XZR 775f757f3fSDimitry Andric CheckAll<[CheckOpcode<[FMOVWHr, FMOVXHr, 785f757f3fSDimitry Andric FMOVWSr, FMOVXDr]>, 795f757f3fSDimitry Andric CheckIsReg1Zero]>, 805f757f3fSDimitry Andric // MOVI Dd, #0 815f757f3fSDimitry Andric // MOVI Vd.2D, #0 825f757f3fSDimitry Andric CheckAll<[CheckOpcode<[MOVID, MOVIv2d_ns]>, 835f757f3fSDimitry Andric CheckImmOperand<1, 0>]> 845f757f3fSDimitry Andric ]>>; 85