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Searched refs:TII (Results 1 – 25 of 528) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kExpandPseudo.cpp48 const M68kInstrInfo *TII; member in __anon49c204510111::M68kExpandPseudo
84 return TII->ExpandMOVI(MIB, MVT::i8); in INITIALIZE_PASS()
86 return TII->ExpandMOVI(MIB, MVT::i16); in INITIALIZE_PASS()
88 return TII->ExpandMOVI(MIB, MVT::i32); in INITIALIZE_PASS()
91 return TII->ExpandMOVX_RR(MIB, MVT::i16, MVT::i8); in INITIALIZE_PASS()
93 return TII->ExpandMOVX_RR(MIB, MVT::i32, MVT::i8); in INITIALIZE_PASS()
95 return TII->ExpandMOVX_RR(MIB, MVT::i32, MVT::i16); in INITIALIZE_PASS()
98 return TII->ExpandMOVSZX_RR(MIB, true, MVT::i16, MVT::i8); in INITIALIZE_PASS()
100 return TII->ExpandMOVSZX_RR(MIB, true, MVT::i32, MVT::i8); in INITIALIZE_PASS()
102 return TII->ExpandMOVSZX_RR(MIB, true, MVT::i32, MVT::i16); in INITIALIZE_PASS()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyLowerBrUnless.cpp62 const auto &TII = *MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo(); in runOnMachineFunction() local
80 Def->setDesc(TII.get(NE_I32)); in runOnMachineFunction()
84 Def->setDesc(TII.get(EQ_I32)); in runOnMachineFunction()
88 Def->setDesc(TII.get(LE_S_I32)); in runOnMachineFunction()
92 Def->setDesc(TII.get(LT_S_I32)); in runOnMachineFunction()
96 Def->setDesc(TII.get(GE_S_I32)); in runOnMachineFunction()
100 Def->setDesc(TII.get(GT_S_I32)); in runOnMachineFunction()
104 Def->setDesc(TII.get(LE_U_I32)); in runOnMachineFunction()
108 Def->setDesc(TII.get(LT_U_I32)); in runOnMachineFunction()
112 Def->setDesc(TII.get(GE_U_I32)); in runOnMachineFunction()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCInstructionSelector.cpp70 const PPCInstrInfo &TII; member in __anone05d911e0111::PPCInstructionSelector
92 : TM(TM), STI(STI), TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), in PPCInstructionSelector()
130 static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII, in selectCopy() argument
146 LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode()) in selectCopy()
197 BuildMI(MBB, I, DbgLoc, TII.get(PPC::MTVSRD), MoveReg).addReg(SrcReg); in selectIntToFP()
205 BuildMI(MBB, I, DbgLoc, TII.get(ConvOp), DstReg).addReg(MoveReg); in selectIntToFP()
208 return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI); in selectIntToFP()
222 BuildMI(MBB, I, DbgLoc, TII.get(TargetOpcode::COPY), CopyReg).addReg(SrcReg); in selectFPToInt()
232 BuildMI(MBB, I, DbgLoc, TII.get(ConvOp), ConvReg).addReg(CopyReg); in selectFPToInt()
235 BuildMI(MBB, I, DbgLoc, TII.get(PPC::MFVSRD), DstReg).addReg(ConvReg); in selectFPToInt()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUIGroupLP.cpp91 const SIInstrInfo *TII; member in __anon5d856e630111::InstructionRule
104 InstructionRule(const SIInstrInfo *TII, unsigned SGID, in InstructionRule() argument
106 : TII(TII), SGID(SGID) { in InstructionRule()
155 const SIInstrInfo *TII; member in __anon5d856e630111::SchedGroup
231 ScheduleDAGInstrs *DAG, const SIInstrInfo *TII) in SchedGroup() argument
232 : SGMask(SGMask), MaxSize(MaxSize), DAG(DAG), TII(TII) { in SchedGroup()
237 ScheduleDAGInstrs *DAG, const SIInstrInfo *TII) in SchedGroup() argument
238 : SGMask(SGMask), MaxSize(MaxSize), SyncID(SyncID), DAG(DAG), TII(TII) { in SchedGroup()
844 const SIInstrInfo *TII; member in __anon5d856e630111::IGLPStrategy
859 IGLPStrategy(ScheduleDAGInstrs *DAG, const SIInstrInfo *TII) in IGLPStrategy() argument
[all …]
H A DR600ExpandSpecialInstrs.cpp31 const R600InstrInfo *TII = nullptr; member in __anondcd2053f0111::R600ExpandSpecialInstrsPass
65 int OpIdx = TII->getOperandIdx(*OldMI, Op); in SetFlagInNewMI()
68 TII->setImmOperand(*NewMI, Op, Val); in SetFlagInNewMI()
74 TII = ST.getInstrInfo(); in runOnMachineFunction()
76 const R600RegisterInfo &TRI = TII->getRegisterInfo(); in runOnMachineFunction()
85 if (TII->isLDSRetInstr(MI.getOpcode())) { in runOnMachineFunction()
86 int DstIdx = TII->getOperandIdx(MI.getOpcode(), R600::OpName::dst); in runOnMachineFunction()
89 MachineInstr *Mov = TII->buildMovInstr(&MBB, I, in runOnMachineFunction()
92 int LDSPredSelIdx = TII->getOperandIdx(MI.getOpcode(), in runOnMachineFunction()
94 int MovPredSelIdx = TII->getOperandIdx(Mov->getOpcode(), in runOnMachineFunction()
[all …]
H A DSIPeepholeSDWA.cpp41 const SIInstrInfo *TII);
52 const SIInstrInfo *TII; member in __anon5b8513100111::SIPeepholeSDWA
97 virtual MachineInstr *potentialToConvert(const SIInstrInfo *TII,
100 virtual bool convertToSDWA(MachineInstr &MI, const SIInstrInfo *TII) = 0;
132 MachineInstr *potentialToConvert(const SIInstrInfo *TII,
135 bool convertToSDWA(MachineInstr &MI, const SIInstrInfo *TII) override;
142 uint64_t getSrcMods(const SIInstrInfo *TII,
161 MachineInstr *potentialToConvert(const SIInstrInfo *TII,
164 bool convertToSDWA(MachineInstr &MI, const SIInstrInfo *TII) override;
184 bool convertToSDWA(MachineInstr &MI, const SIInstrInfo *TII) override;
[all …]
H A DGCNDPPCombine.cpp56 const SIInstrInfo *TII; member in __anon1318784c0111::GCNDPPCombine
119 if (!TII->isVOP3(Op)) { in isShrinkable()
122 if (!TII->hasVALU32BitEncoding(Op)) { in isShrinkable()
130 if (const auto *SDst = TII->getNamedOperand(MI, AMDGPU::OpName::sdst)) { in isShrinkable()
158 if (DPP32 != -1 && TII->pseudoToMCOpcode(DPP32) != -1) in getDPPOp()
163 if (DPP64 != -1 && TII->pseudoToMCOpcode(DPP64) != -1) in getDPPOp()
223 auto *RowMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::row_mask); in createDPPInst()
225 auto *BankMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::bank_mask); in createDPPInst()
231 !(TII->isVOPC(DPPOp) || (TII->isVOP3(DPPOp) && OrigOpE32 != -1 && in createDPPInst()
232 TII->isVOPC(OrigOpE32)))) && in createDPPInst()
[all …]
H A DR600Packetizer.cpp52 const R600InstrInfo *TII; member in __anon0b5b71cd0111::R600PacketizerList
67 if (!TII->isALUInstr(I->getOpcode()) && !I->isBundle()) in getPreviousVector()
79 if (TII->isPredicated(*BI)) in getPreviousVector()
81 int OperandIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::write); in getPreviousVector()
84 int DstIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::dst); in getPreviousVector()
89 if (isTrans || TII->isTransOnly(*BI)) { in getPreviousVector()
131 int OperandIdx = TII->getOperandIdx(MI.getOpcode(), Op); in substitutePV()
145 TII(ST.getInstrInfo()), in R600PacketizerList()
146 TRI(TII->getRegisterInfo()) { in R600PacketizerList()
164 if (TII->isVector(MI)) in isSoloInstruction()
[all …]
H A DSIModeRegister.cpp138 void processBlockPhase1(MachineBasicBlock &MBB, const SIInstrInfo *TII);
140 void processBlockPhase2(MachineBasicBlock &MBB, const SIInstrInfo *TII);
142 void processBlockPhase3(MachineBasicBlock &MBB, const SIInstrInfo *TII);
144 Status getInstructionMode(MachineInstr &MI, const SIInstrInfo *TII);
147 const SIInstrInfo *TII, Status InstrMode);
165 const SIInstrInfo *TII) { in getInstructionMode() argument
166 if (TII->usesFPDPRounding(MI) || in getInstructionMode()
178 if (TII->getSubtarget().hasTrue16BitInsts()) { in getInstructionMode()
181 MI.setDesc(TII->get(AMDGPU::V_CVT_F16_F32_t16_e64)); in getInstructionMode()
189 MI.setDesc(TII->get(AMDGPU::V_CVT_F16_F32_e32)); in getInstructionMode()
[all …]
H A DR600EmitClauseMarkers.cpp34 const R600InstrInfo *TII = nullptr; member in __anonc14e5a1c0111::R600EmitClauseMarkers
52 if (TII->isLDSRetInstr(MI.getOpcode())) in OccupiedDwords()
55 if (TII->isVector(MI) || TII->isCubeOp(MI.getOpcode()) || in OccupiedDwords()
56 TII->isReductionOp(MI.getOpcode())) in OccupiedDwords()
71 if (TII->isALUInstr(MI.getOpcode())) in isALU()
73 if (TII->isVector(MI) || TII->isCubeOp(MI.getOpcode())) in isALU()
119 if (!TII->isALUInstr(MI.getOpcode()) && MI.getOpcode() != R600::DOT_4) in SubstituteKCacheBank()
123 TII->getSrcs(MI); in SubstituteKCacheBank()
125 (TII->isALUInstr(MI.getOpcode()) || MI.getOpcode() == R600::DOT_4) && in SubstituteKCacheBank()
181 const R600RegisterInfo &TRI = TII->getRegisterInfo(); in canClauseLocalKillFitInClause()
[all …]
H A DR600ClauseMergePass.cpp39 const R600InstrInfo *TII; member in __anoncc0cd03f0111::R600ClauseMergePass
79 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::COUNT)) in getCFAluSize()
86 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::Enabled)) in isCFAluEnabled()
92 int CntIdx = TII->getOperandIdx(R600::CF_ALU, R600::OpName::COUNT); in cleanPotentialDisabledCFAlu()
111 int CntIdx = TII->getOperandIdx(R600::CF_ALU, R600::OpName::COUNT); in mergeIfPossible()
115 if (CumuledInsts >= TII->getMaxAlusPerClause()) { in mergeIfPossible()
123 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_MODE0); in mergeIfPossible()
125 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_BANK0); in mergeIfPossible()
127 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_ADDR0); in mergeIfPossible()
139 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_MODE1); in mergeIfPossible()
[all …]
H A DSIShrinkInstructions.cpp33 const SIInstrInfo *TII; member in __anon1ecff9b30111::SIShrinkInstructions
91 assert(TII->isVOP1(MI) || TII->isVOP2(MI) || TII->isVOPC(MI)); in foldImmediates()
105 if (TII->isOperandLegal(MI, Src0Idx, &MovSrc)) { in foldImmediates()
131 if (TII->commuteInstruction(MI)) { in foldImmediates()
136 TII->commuteInstruction(MI); in foldImmediates()
162 !TII->isInlineConstant(*Src.getParent(), Src.getOperandNo()); in isKImmOperand()
167 !TII->isInlineConstant(*Src.getParent(), Src.getOperandNo()); in isKUImmOperand()
174 return !TII->isInlineConstant(Src); in isKImmOrKUImmOperand()
179 return !TII->isInlineConstant(Src); in isKImmOrKUImmOperand()
194 static unsigned canModifyToInlineImmOp32(const SIInstrInfo *TII, in canModifyToInlineImmOp32() argument
[all …]
H A DSIFoldOperands.cpp73 const SIInstrInfo *TII; member in __anon62acd4700111::SIFoldOperands
186 if (TII->isMUBUF(UseMI)) in frameIndexMayFold()
188 if (!TII->isFLATScratch(UseMI)) in frameIndexMayFold()
217 uint8_t OpType = TII->get(Opcode).operands()[OpNo].OperandType; in canUseImmWithOpSel()
238 uint8_t OpType = TII->get(Opcode).operands()[OpNo].OperandType; in tryFoldImmWithOpSel()
348 MI->setDesc(TII->get(NegOpcode)); in tryFoldImmWithOpSel()
370 if (!TII->isOperandLegal(*MI, OpNo, &New)) in updateOperand()
394 MachineInstr *Inst32 = TII->buildShrunkInst(*MI, Op32); in updateOperand()
397 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(AMDGPU::COPY), in updateOperand()
411 MI->setDesc(TII->get(AMDGPU::IMPLICIT_DEF)); in updateOperand()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchExpandAtomicPseudoInsts.cpp33 const LoongArchInstrInfo *TII; member in __anonc2e1364d0111::LoongArchExpandAtomicPseudo
66 TII = in runOnMachineFunction()
146 static void doAtomicBinOpExpansion(const LoongArchInstrInfo *TII, in doAtomicBinOpExpansion() argument
163 TII->get(Width == 32 ? LoongArch::LL_W : LoongArch::LL_D), DestReg) in doAtomicBinOpExpansion()
170 BuildMI(LoopMBB, DL, TII->get(LoongArch::OR), ScratchReg) in doAtomicBinOpExpansion()
175 BuildMI(LoopMBB, DL, TII->get(LoongArch::AND), ScratchReg) in doAtomicBinOpExpansion()
178 BuildMI(LoopMBB, DL, TII->get(LoongArch::NOR), ScratchReg) in doAtomicBinOpExpansion()
183 BuildMI(LoopMBB, DL, TII->get(LoongArch::ADD_W), ScratchReg) in doAtomicBinOpExpansion()
188 BuildMI(LoopMBB, DL, TII->get(LoongArch::SUB_W), ScratchReg) in doAtomicBinOpExpansion()
193 BuildMI(LoopMBB, DL, TII in doAtomicBinOpExpansion()
224 insertMaskedMerge(const LoongArchInstrInfo * TII,DebugLoc DL,MachineBasicBlock * MBB,Register DestReg,Register OldValReg,Register NewValReg,Register MaskReg,Register ScratchReg) insertMaskedMerge() argument
245 doMaskedAtomicBinOpExpansion(const LoongArchInstrInfo * TII,MachineInstr & MI,DebugLoc DL,MachineBasicBlock * ThisMBB,MachineBasicBlock * LoopMBB,MachineBasicBlock * DoneMBB,AtomicRMWInst::BinOp BinOp,int Width) doMaskedAtomicBinOpExpansion() argument
350 insertSext(const LoongArchInstrInfo * TII,DebugLoc DL,MachineBasicBlock * MBB,Register ValReg,Register ShamtReg) insertSext() argument
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsInstructionSelector.cpp61 const MipsInstrInfo &TII; member in __anonbf07d5ca0111::MipsInstructionSelector
83 : TM(TM), STI(STI), TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), in MipsInstructionSelector()
113 LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode()) in selectCopy()
152 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); in materialize32BitImm()
158 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); in materialize32BitImm()
165 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); in materialize32BitImm()
173 if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI)) in materialize32BitImm()
175 if (!constrainSelectedInstRegOperands(*ORi, TII, TRI, RBI)) in materialize32BitImm()
262 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opc)) in buildUnalignedStore()
267 if (!constrainSelectedInstRegOperands(*NewInst, TII, TRI, RBI)) in buildUnalignedStore()
[all …]
H A DMipsBranchExpansion.cpp172 const MipsInstrInfo *TII; member in __anone5a1286a0111::MipsBranchExpansion
303 MBBInfos[I].Size += TII->getInstSizeInBytes(MI); in initMBBInfo()
341 unsigned NewOpc = TII->getOppositeBranchOpc(Br->getOpcode()); in replaceBranch()
342 const MCInstrDesc &NewDesc = TII->get(NewOpc); in replaceBranch()
356 if (!TII->isBranchWithImm(Br->getOpcode())) in replaceBranch()
400 BuildMI(*MBB, Pos, DL, TII->get(JumpOp)).addReg(ATReg); in buildProperJumpMI()
469 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP) in expandToLongBranch()
472 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)) in expandToLongBranch()
493 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi), Mips::AT) in expandToLongBranch()
498 BuildMI(*MFp, DL, TII->get(BalOp)).addMBB(BalTgtMBB); in expandToLongBranch()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRFrameLowering.cpp55 const AVRInstrInfo &TII = *STI.getInstrInfo(); in emitPrologue()
62 BuildMI(MBB, MBBI, DL, TII.get(AVR::BSETs)) in emitPrologue()
70 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHRr)) in emitPrologue()
74 BuildMI(MBB, MBBI, DL, TII.get(AVR::INRdA), STI.getTmpRegister()) in emitPrologue()
77 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHRr)) in emitPrologue()
81 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHRr)) in emitPrologue()
84 BuildMI(MBB, MBBI, DL, TII.get(AVR::EORRdRr)) in emitPrologue()
108 BuildMI(MBB, MBBI, DL, TII.get(AVR::SPREAD), AVR::R29R28) in emitPrologue()
125 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opcode), AVR::R29R28) in emitPrologue()
133 BuildMI(MBB, MBBI, DL, TII in emitPrologue()
57 const AVRInstrInfo &TII = *STI.getInstrInfo(); emitPrologue() local
148 const AVRInstrInfo &TII = *STI.getInstrInfo(); restoreStatusRegister() local
182 const AVRInstrInfo &TII = *STI.getInstrInfo(); emitEpilogue() local
256 const TargetInstrInfo &TII = *STI.getInstrInfo(); spillCalleeSavedRegisters() local
305 const TargetInstrInfo &TII = *STI.getInstrInfo(); restoreCalleeSavedRegisters() local
323 fixStackStores(MachineBasicBlock & MBB,MachineBasicBlock::iterator StartMI,const TargetInstrInfo & TII) fixStackStores() argument
353 const AVRInstrInfo &TII = *STI.getInstrInfo(); eliminateCallFramePseudoInstr() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVExpandAtomicPseudoInsts.cpp34 const RISCVInstrInfo *TII;
67 Size += TII->getInstSizeInBytes(MI); in getInstSizeInBytes()
77 TII = STI->getInstrInfo(); in runOnMachineFunction()
259 static void doAtomicBinOpExpansion(const RISCVInstrInfo *TII, MachineInstr &MI, in doAtomicBinOpExpansion()
277 BuildMI(LoopMBB, DL, TII->get(getLRForRMW(Ordering, Width, STI)), DestReg) in insertMaskedMerge()
283 BuildMI(LoopMBB, DL, TII->get(RISCV::AND), ScratchReg) in insertMaskedMerge()
286 BuildMI(LoopMBB, DL, TII->get(RISCV::XORI), ScratchReg) in insertMaskedMerge()
291 BuildMI(LoopMBB, DL, TII->get(getSCForRMW(Ordering, Width, STI)), ScratchReg) in insertMaskedMerge()
294 BuildMI(LoopMBB, DL, TII->get(RISCV::BNE)) in insertMaskedMerge()
300 static void insertMaskedMerge(const RISCVInstrInfo *TII, DebugLo in doMaskedAtomicBinOpExpansion()
33 const RISCVInstrInfo *TII; global() member in __anon63aa91a10111::RISCVExpandAtomicPseudo
235 doAtomicBinOpExpansion(const RISCVInstrInfo * TII,MachineInstr & MI,DebugLoc DL,MachineBasicBlock * ThisMBB,MachineBasicBlock * LoopMBB,MachineBasicBlock * DoneMBB,AtomicRMWInst::BinOp BinOp,int Width) doAtomicBinOpExpansion() argument
275 insertMaskedMerge(const RISCVInstrInfo * TII,DebugLoc DL,MachineBasicBlock * MBB,Register DestReg,Register OldValReg,Register NewValReg,Register MaskReg,Register ScratchReg) insertMaskedMerge() argument
298 doMaskedAtomicBinOpExpansion(const RISCVInstrInfo * TII,MachineInstr & MI,DebugLoc DL,MachineBasicBlock * ThisMBB,MachineBasicBlock * LoopMBB,MachineBasicBlock * DoneMBB,AtomicRMWInst::BinOp BinOp,int Width) doMaskedAtomicBinOpExpansion() argument
398 insertSext(const RISCVInstrInfo * TII,DebugLoc DL,MachineBasicBlock * MBB,Register ValReg,Register ShamtReg) insertSext() argument
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreFrameLowering.cpp62 const DebugLoc &dl, const TargetInstrInfo &TII, in EmitDefCfaRegister() argument
66 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in EmitDefCfaRegister()
72 const DebugLoc &dl, const TargetInstrInfo &TII, in EmitDefCfaOffset() argument
77 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in EmitDefCfaOffset()
83 const TargetInstrInfo &TII, unsigned DRegNum, in EmitCfiOffset() argument
88 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in EmitCfiOffset()
100 const TargetInstrInfo &TII, int OffsetFromTop, in IfNeededExtSP() argument
107 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(OpImm); in IfNeededExtSP()
110 EmitDefCfaOffset(MBB, MBBI, dl, TII, Adjusted*4); in IfNeededExtSP()
123 const TargetInstrInfo &TII, int OffsetFromTop, in IfNeededLDAWSP() argument
[all …]
H A DXCoreRegisterInfo.cpp62 const XCoreInstrInfo &TII, in InsertFPImmInst() argument
70 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg) in InsertFPImmInst()
76 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus)) in InsertFPImmInst()
83 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg) in InsertFPImmInst()
93 const XCoreInstrInfo &TII, in InsertFPConstInst() argument
103 TII.loadImmediate(MBB, II, ScratchOffset, Offset); in InsertFPConstInst()
107 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg) in InsertFPConstInst()
113 BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r)) in InsertFPConstInst()
120 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg) in InsertFPConstInst()
130 const XCoreInstrInfo &TII, in InsertSPImmInst() argument
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEFrameLowering.cpp142 const VEInstrInfo &TII = *STI.getInstrInfo(); in emitPrologueInsns() local
152 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
157 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
164 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
169 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
176 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
190 const VEInstrInfo &TII = *STI.getInstrInfo(); in emitEpilogueInsns() local
200 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX17) in emitEpilogueInsns()
205 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX16) in emitEpilogueInsns()
209 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX15) in emitEpilogueInsns()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp73 const ARMBaseInstrInfo &TII; member in __anone228b8980111::ARMInstructionSelector
176 : TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), TM(TM), RBI(RBI), in ARMInstructionSelector()
213 static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII, in selectCopy() argument
226 LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode()) in selectCopy()
234 const ARMBaseInstrInfo &TII, in selectMergeValues() argument
238 assert(TII.getSubtarget().hasVFP2Base() && "Can't select merge without VFP"); in selectMergeValues()
258 MIB->setDesc(TII.get(ARM::VMOVDRR)); in selectMergeValues()
265 const ARMBaseInstrInfo &TII, in selectUnmergeValues() argument
269 assert(TII.getSubtarget().hasVFP2Base() && in selectUnmergeValues()
290 MIB->setDesc(TII.get(ARM::VMOVRRD)); in selectUnmergeValues()
[all …]
H A DARMFrameLowering.cpp293 const TargetInstrInfo &TII, in insertSEH() argument
307 report_fatal_error("No SEH Opcode for instruction " + TII.getName(Opc)); in insertSEH()
316 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop)) in insertSEH()
325 BuildMI(MF, DL, TII.get(ARM::tMOVi8)).setMIFlags(MBBI->getFlags()); in insertSEH()
334 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop)).addImm(Wide).setMIFlags(Flags); in insertSEH()
339 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop)) in insertSEH()
352 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop)) in insertSEH()
356 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop)) in insertSEH()
366 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_SaveRegs)) in insertSEH()
380 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_SaveRegs)) in insertSEH()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineCopyPropagation.cpp97 const TargetInstrInfo &TII, in isCopyInstr() argument
100 return TII.isCopyInstr(MI); in isCopyInstr()
135 const TargetInstrInfo &TII, bool UseCopyInstr) { in invalidateRegister() argument
143 isCopyInstr(*MI, TII, UseCopyInstr); in invalidateRegister()
167 const TargetInstrInfo &TII, bool UseCopyInstr) { in clobberRegister() argument
178 isCopyInstr(*MI, TII, UseCopyInstr); in clobberRegister()
228 const TargetInstrInfo &TII, bool UseCopyInstr) { in trackCopy() argument
230 isCopyInstr(*MI, TII, UseCopyInstr); in trackCopy()
279 const TargetInstrInfo &TII, in findAvailBackwardCopy() argument
288 isCopyInstr(*AvailCopy, TII, UseCopyInstr); in findAvailBackwardCopy()
[all …]
H A DXRayInstrumentation.cpp70 const TargetInstrInfo *TII,
82 const TargetInstrInfo *TII,
89 MachineFunction &MF, const TargetInstrInfo *TII, in replaceRetWithPatchableRet() argument
98 (op.HandleAllReturns || T.getOpcode() == TII->getReturnOpcode())) { in replaceRetWithPatchableRet()
103 if (TII->isTailCall(T) && op.HandleTailcall) { in replaceRetWithPatchableRet()
109 auto MIB = BuildMI(MBB, T, T.getDebugLoc(), TII->get(Opc)) in replaceRetWithPatchableRet()
125 MachineFunction &MF, const TargetInstrInfo *TII, in prependRetWithPatchableExit() argument
131 (op.HandleAllReturns || T.getOpcode() == TII->getReturnOpcode())) { in prependRetWithPatchableExit()
134 if (TII->isTailCall(T) && op.HandleTailcall) { in prependRetWithPatchableExit()
140 BuildMI(MBB, T, T.getDebugLoc(), TII->get(Opc)); in prependRetWithPatchableExit()
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