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Searched refs:TII (Results 1 – 25 of 550) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kExpandPseudo.cpp48 const M68kInstrInfo *TII; member in __anon49c204510111::M68kExpandPseudo
83 return TII->ExpandMOVI(MIB, MVT::i8); in INITIALIZE_PASS()
85 return TII->ExpandMOVI(MIB, MVT::i16); in INITIALIZE_PASS()
87 return TII->ExpandMOVI(MIB, MVT::i32); in INITIALIZE_PASS()
90 return TII->ExpandMOVX_RR(MIB, MVT::i16, MVT::i8); in INITIALIZE_PASS()
92 return TII->ExpandMOVX_RR(MIB, MVT::i32, MVT::i8); in INITIALIZE_PASS()
94 return TII->ExpandMOVX_RR(MIB, MVT::i32, MVT::i16); in INITIALIZE_PASS()
97 return TII->ExpandMOVSZX_RR(MIB, true, MVT::i16, MVT::i8); in INITIALIZE_PASS()
99 return TII->ExpandMOVSZX_RR(MIB, true, MVT::i32, MVT::i8); in INITIALIZE_PASS()
101 return TII->ExpandMOVSZX_RR(MIB, true, MVT::i32, MVT::i16); in INITIALIZE_PASS()
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/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyLowerBrUnless.cpp62 const auto &TII = *MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo(); in runOnMachineFunction() local
80 Def->setDesc(TII.get(NE_I32)); in runOnMachineFunction()
84 Def->setDesc(TII.get(EQ_I32)); in runOnMachineFunction()
88 Def->setDesc(TII.get(LE_S_I32)); in runOnMachineFunction()
92 Def->setDesc(TII.get(LT_S_I32)); in runOnMachineFunction()
96 Def->setDesc(TII.get(GE_S_I32)); in runOnMachineFunction()
100 Def->setDesc(TII.get(GT_S_I32)); in runOnMachineFunction()
104 Def->setDesc(TII.get(LE_U_I32)); in runOnMachineFunction()
108 Def->setDesc(TII.get(LT_U_I32)); in runOnMachineFunction()
112 Def->setDesc(TII.get(GE_U_I32)); in runOnMachineFunction()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIPeepholeSDWA.cpp42 const SIInstrInfo *TII);
53 const SIInstrInfo *TII; member in __anon5b8513100111::SIPeepholeSDWA
100 const SIInstrInfo *TII) = 0;
111 virtual MachineInstr *potentialToConvert(const SIInstrInfo *TII,
114 virtual bool convertToSDWA(MachineInstr &MI, const SIInstrInfo *TII) = 0;
144 MachineInstr *potentialToConvert(const SIInstrInfo *TII,
147 bool convertToSDWA(MachineInstr &MI, const SIInstrInfo *TII) override;
149 const SIInstrInfo *TII) override;
156 uint64_t getSrcMods(const SIInstrInfo *TII,
174 MachineInstr *potentialToConvert(const SIInstrInfo *TII,
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H A DAMDGPUIGroupLP.cpp90 const SIInstrInfo *TII; member in __anon5d856e630111::InstructionRule
103 InstructionRule(const SIInstrInfo *TII, unsigned SGID, in InstructionRule() argument
105 : TII(TII), SGID(SGID) { in InstructionRule()
154 const SIInstrInfo *TII; member in __anon5d856e630111::SchedGroup
230 ScheduleDAGInstrs *DAG, const SIInstrInfo *TII) in SchedGroup() argument
231 : SGMask(SGMask), MaxSize(MaxSize), DAG(DAG), TII(TII) { in SchedGroup()
236 ScheduleDAGInstrs *DAG, const SIInstrInfo *TII) in SchedGroup() argument
237 : SGMask(SGMask), MaxSize(MaxSize), SyncID(SyncID), DAG(DAG), TII(TII) { in SchedGroup()
822 const SIInstrInfo *TII; member in __anon5d856e630111::IGLPStrategy
837 IGLPStrategy(ScheduleDAGInstrs *DAG, const SIInstrInfo *TII) in IGLPStrategy() argument
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H A DR600ExpandSpecialInstrs.cpp31 const R600InstrInfo *TII = nullptr; member in __anondcd2053f0111::R600ExpandSpecialInstrsPass
66 int OpIdx = TII->getOperandIdx(*OldMI, Op); in SetFlagInNewMI()
69 TII->setImmOperand(*NewMI, Op, Val); in SetFlagInNewMI()
75 TII = ST.getInstrInfo(); in runOnMachineFunction()
77 const R600RegisterInfo &TRI = TII->getRegisterInfo(); in runOnMachineFunction()
86 if (TII->isLDSRetInstr(MI.getOpcode())) { in runOnMachineFunction()
87 int DstIdx = TII->getOperandIdx(MI.getOpcode(), R600::OpName::dst); in runOnMachineFunction()
90 MachineInstr *Mov = TII->buildMovInstr(&MBB, I, in runOnMachineFunction()
93 int LDSPredSelIdx = TII->getOperandIdx(MI.getOpcode(), in runOnMachineFunction()
95 int MovPredSelIdx = TII->getOperandIdx(Mov->getOpcode(), in runOnMachineFunction()
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H A DGCNDPPCombine.cpp57 const SIInstrInfo *TII; member in __anon1318784c0111::GCNDPPCombine
120 if (!TII->isVOP3(Op)) { in isShrinkable()
123 if (!TII->hasVALU32BitEncoding(Op)) { in isShrinkable()
131 if (const auto *SDst = TII->getNamedOperand(MI, AMDGPU::OpName::sdst)) { in isShrinkable()
159 if (DPP32 != -1 && TII->pseudoToMCOpcode(DPP32) != -1) in getDPPOp()
164 if (DPP64 != -1 && TII->pseudoToMCOpcode(DPP64) != -1) in getDPPOp()
229 auto *RowMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::row_mask); in createDPPInst()
231 auto *BankMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::bank_mask); in createDPPInst()
237 !(TII->isVOPC(DPPOp) || (TII->isVOP3(DPPOp) && OrigOpE32 != -1 && in createDPPInst()
238 TII->isVOPC(OrigOpE32)))) && in createDPPInst()
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H A DR600Packetizer.cpp52 const R600InstrInfo *TII; member in __anon0b5b71cd0111::R600PacketizerList
67 if (!TII->isALUInstr(I->getOpcode()) && !I->isBundle()) in getPreviousVector()
79 if (TII->isPredicated(*BI)) in getPreviousVector()
81 int OperandIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::write); in getPreviousVector()
84 int DstIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::dst); in getPreviousVector()
89 if (isTrans || TII->isTransOnly(*BI)) { in getPreviousVector()
128 int OperandIdx = TII->getOperandIdx(MI.getOpcode(), Op); in substitutePV()
142 TII(ST.getInstrInfo()), in R600PacketizerList()
143 TRI(TII->getRegisterInfo()) { in R600PacketizerList()
161 if (TII->isVector(MI)) in isSoloInstruction()
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H A DR600EmitClauseMarkers.cpp28 const R600InstrInfo *TII = nullptr; member in __anonc14e5a1c0111::R600EmitClauseMarkers
46 if (TII->isLDSRetInstr(MI.getOpcode())) in OccupiedDwords()
49 if (TII->isVector(MI) || TII->isCubeOp(MI.getOpcode()) || in OccupiedDwords()
50 TII->isReductionOp(MI.getOpcode())) in OccupiedDwords()
65 if (TII->isALUInstr(MI.getOpcode())) in isALU()
67 if (TII->isVector(MI) || TII->isCubeOp(MI.getOpcode())) in isALU()
113 if (!TII->isALUInstr(MI.getOpcode()) && MI.getOpcode() != R600::DOT_4) in SubstituteKCacheBank()
117 TII->getSrcs(MI); in SubstituteKCacheBank()
119 (TII->isALUInstr(MI.getOpcode()) || MI.getOpcode() == R600::DOT_4) && in SubstituteKCacheBank()
175 const R600RegisterInfo &TRI = TII->getRegisterInfo(); in canClauseLocalKillFitInClause()
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H A DSILateBranchLowering.cpp30 const SIInstrInfo *TII = nullptr; member in __anon03252fca0111::SILateBranchLowering
81 const SIInstrInfo *TII, MachineFunction &MF) { in generateEndPgm() argument
91 bool MustExport = !AMDGPU::isGFX10Plus(TII->getSubtarget()); in generateEndPgm()
100 BuildMI(MBB, I, DL, TII->get(AMDGPU::EXP_DONE)) in generateEndPgm()
112 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ENDPGM)).addImm(0); in generateEndPgm()
156 BuildMI(*MI.getParent(), MI, DL, TII->get(AMDGPU::S_ALLOC_VGPR)); in expandChainCall()
158 *TII->getNamedOperand(MI, AMDGPU::OpName::numvgprs)); in expandChainCall()
161 BuildMI(*MI.getParent(), MI, DL, TII->get(AMDGPU::S_CSELECT_B64)) in expandChainCall()
162 .addDef(TII->getNamedOperand(MI, AMDGPU::OpName::src0)->getReg()); in expandChainCall()
164 *TII->getNamedOperand(MI, AMDGPU::OpName::src0)); in expandChainCall()
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H A DGCNHazardRecognizer.cpp61 ST(MF.getSubtarget<GCNSubtarget>()), TII(*ST.getInstrInfo()), in GCNHazardRecognizer()
62 TRI(TII.getRegisterInfo()), TSchedModel(TII.getSchedModel()), in GCNHazardRecognizer()
119 static bool isSendMsgTraceDataOrGDS(const SIInstrInfo &TII, in isSendMsgTraceDataOrGDS() argument
121 if (TII.isAlwaysGDS(MI.getOpcode())) in isSendMsgTraceDataOrGDS()
135 if (TII.isDS(MI.getOpcode())) { in isSendMsgTraceDataOrGDS()
163 static unsigned getHWReg(const SIInstrInfo *TII, const MachineInstr &RegInstr) { in getHWReg() argument
164 const MachineOperand *RegOp = TII->getNamedOperand(RegInstr, in getHWReg()
221 (TII.isVINTRP(*MI) || isSMovRel(MI->getOpcode()) || in getHazardType()
224 (ST.hasReadM0SendMsgHazard() && isSendMsgTraceDataOrGDS(TII, *MI)) || in getHazardType()
244 static void insertNoopsInBundle(MachineInstr *MI, const SIInstrInfo &TII, in insertNoopsInBundle() argument
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H A DSIModeRegister.cpp128 void processBlockPhase1(MachineBasicBlock &MBB, const SIInstrInfo *TII);
130 void processBlockPhase2(MachineBasicBlock &MBB, const SIInstrInfo *TII);
132 void processBlockPhase3(MachineBasicBlock &MBB, const SIInstrInfo *TII);
134 Status getInstructionMode(MachineInstr &MI, const SIInstrInfo *TII);
137 const SIInstrInfo *TII, Status InstrMode);
171 const SIInstrInfo *TII) { in getInstructionMode() argument
173 if (TII->usesFPDPRounding(MI) || in getInstructionMode()
188 MI.setDesc(TII->get(AMDGPU::V_CVT_F16_F32_e32)); in getInstructionMode()
194 MI.setDesc(TII->get(AMDGPU::V_CVT_F16_F32_fake16_e32)); in getInstructionMode()
200 MI.setDesc(TII->get(AMDGPU::V_CVT_F16_F32_t16_e64)); in getInstructionMode()
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H A DR600ClauseMergePass.cpp39 const R600InstrInfo *TII; member in __anoncc0cd03f0111::R600ClauseMergePass
79 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::COUNT)) in getCFAluSize()
86 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::Enabled)) in isCFAluEnabled()
92 int CntIdx = TII->getOperandIdx(R600::CF_ALU, R600::OpName::COUNT); in cleanPotentialDisabledCFAlu()
111 int CntIdx = TII->getOperandIdx(R600::CF_ALU, R600::OpName::COUNT); in mergeIfPossible()
115 if (CumuledInsts >= TII->getMaxAlusPerClause()) { in mergeIfPossible()
123 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_MODE0); in mergeIfPossible()
125 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_BANK0); in mergeIfPossible()
127 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_ADDR0); in mergeIfPossible()
139 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_MODE1); in mergeIfPossible()
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H A DGCNVOPDUtils.cpp37 bool llvm::checkVOPDRegConstraints(const SIInstrInfo &TII, in checkVOPDRegConstraints() argument
47 if (!IsVOPD3 && (TII.isVOP3(FirstMI) || TII.isVOP3(SecondMI))) in checkVOPDRegConstraints()
49 if (TII.isDPP(FirstMI) || TII.isDPP(SecondMI)) in checkVOPDRegConstraints()
91 const MachineOperand &Src0 = *TII.getNamedOperand(MI, AMDGPU::OpName::src0); in checkVOPDRegConstraints()
97 } else if (!TII.isInlineConstant(Src0)) { in checkVOPDRegConstraints()
115 const MachineOperand *Src = TII.getNamedOperand(MI, OpName); in checkVOPDRegConstraints()
132 if (TII.hasModifiersSet(MI, OpName)) in checkVOPDRegConstraints()
141 const MachineOperand *Mods = TII.getNamedOperand(MI, OpName); in checkVOPDRegConstraints()
168 *TII.getNamedOperand(SecondMI, AMDGPU::OpName::src2); in checkVOPDRegConstraints()
174 *TII.getNamedOperand(FirstMI, AMDGPU::OpName::src2); in checkVOPDRegConstraints()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCInstructionSelector.cpp70 const PPCInstrInfo &TII; member in __anone05d911e0111::PPCInstructionSelector
92 : TM(TM), STI(STI), TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), in PPCInstructionSelector()
130 static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII, in selectCopy() argument
146 LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode()) in selectCopy()
197 BuildMI(MBB, I, DbgLoc, TII.get(PPC::MTVSRD), MoveReg).addReg(SrcReg); in selectIntToFP()
205 BuildMI(MBB, I, DbgLoc, TII.get(ConvOp), DstReg).addReg(MoveReg); in selectIntToFP()
208 return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI); in selectIntToFP()
222 BuildMI(MBB, I, DbgLoc, TII.get(TargetOpcode::COPY), CopyReg).addReg(SrcReg); in selectFPToInt()
232 BuildMI(MBB, I, DbgLoc, TII.get(ConvOp), ConvReg).addReg(CopyReg); in selectFPToInt()
235 BuildMI(MBB, I, DbgLoc, TII.get(PPC::MFVSRD), DstReg).addReg(ConvReg); in selectFPToInt()
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/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchExpandAtomicPseudoInsts.cpp33 const LoongArchInstrInfo *TII; member in __anonc2e1364d0111::LoongArchExpandAtomicPseudo
67 TII = in runOnMachineFunction()
162 static void doAtomicBinOpExpansion(const LoongArchInstrInfo *TII, in doAtomicBinOpExpansion() argument
179 TII->get(Width == 32 ? LoongArch::LL_W : LoongArch::LL_D), DestReg) in doAtomicBinOpExpansion()
186 BuildMI(LoopMBB, DL, TII->get(LoongArch::OR), ScratchReg) in doAtomicBinOpExpansion()
191 BuildMI(LoopMBB, DL, TII->get(LoongArch::AND), ScratchReg) in doAtomicBinOpExpansion()
194 BuildMI(LoopMBB, DL, TII->get(LoongArch::NOR), ScratchReg) in doAtomicBinOpExpansion()
199 BuildMI(LoopMBB, DL, TII->get(LoongArch::ADD_W), ScratchReg) in doAtomicBinOpExpansion()
204 BuildMI(LoopMBB, DL, TII->get(LoongArch::SUB_W), ScratchReg) in doAtomicBinOpExpansion()
209 BuildMI(LoopMBB, DL, TII->get(LoongArch::AND), ScratchReg) in doAtomicBinOpExpansion()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsInstructionSelector.cpp61 const MipsInstrInfo &TII; member in __anonbf07d5ca0111::MipsInstructionSelector
83 : TM(TM), STI(STI), TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), in MipsInstructionSelector()
113 LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode()) in selectCopy()
152 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); in materialize32BitImm()
158 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); in materialize32BitImm()
165 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); in materialize32BitImm()
173 if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI)) in materialize32BitImm()
175 if (!constrainSelectedInstRegOperands(*ORi, TII, TRI, RBI)) in materialize32BitImm()
262 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opc)) in buildUnalignedStore()
267 if (!constrainSelectedInstRegOperands(*NewInst, TII, TRI, RBI)) in buildUnalignedStore()
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H A DMipsBranchExpansion.cpp172 const MipsInstrInfo *TII; member in __anone5a1286a0111::MipsBranchExpansion
303 MBBInfos[I].Size += TII->getInstSizeInBytes(MI); in initMBBInfo()
341 unsigned NewOpc = TII->getOppositeBranchOpc(Br->getOpcode()); in replaceBranch()
342 const MCInstrDesc &NewDesc = TII->get(NewOpc); in replaceBranch()
356 if (!TII->isBranchWithImm(Br->getOpcode())) in replaceBranch()
400 BuildMI(*MBB, Pos, DL, TII->get(JumpOp)).addReg(ATReg); in buildProperJumpMI()
469 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP) in expandToLongBranch()
472 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)) in expandToLongBranch()
493 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi), Mips::AT) in expandToLongBranch()
498 BuildMI(*MFp, DL, TII->get(BalOp)).addMBB(BalTgtMBB); in expandToLongBranch()
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H A DMipsExpandPseudo.cpp38 const MipsInstrInfo *TII; member in __anonca8aa8970111::MipsExpandPseudo
144 BuildMI(loop1MBB, DL, TII->get(LL), Scratch).addReg(Ptr).addImm(0); in expandAtomicCmpSwapSubword()
145 BuildMI(loop1MBB, DL, TII->get(Mips::AND), Scratch2) in expandAtomicCmpSwapSubword()
148 BuildMI(loop1MBB, DL, TII->get(BNE)) in expandAtomicCmpSwapSubword()
156 BuildMI(loop2MBB, DL, TII->get(Mips::AND), Scratch) in expandAtomicCmpSwapSubword()
159 BuildMI(loop2MBB, DL, TII->get(Mips::OR), Scratch) in expandAtomicCmpSwapSubword()
162 BuildMI(loop2MBB, DL, TII->get(SC), Scratch) in expandAtomicCmpSwapSubword()
166 BuildMI(loop2MBB, DL, TII->get(BEQ)) in expandAtomicCmpSwapSubword()
174 BuildMI(sinkMBB, DL, TII->get(Mips::SRLV), Dest) in expandAtomicCmpSwapSubword()
178 BuildMI(sinkMBB, DL, TII->get(SEOp), Dest).addReg(Dest); in expandAtomicCmpSwapSubword()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRFrameLowering.cpp54 const AVRInstrInfo &TII = *STI.getInstrInfo(); in emitPrologue() local
61 BuildMI(MBB, MBBI, DL, TII.get(AVR::BSETs)) in emitPrologue()
69 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHRr)) in emitPrologue()
73 BuildMI(MBB, MBBI, DL, TII.get(AVR::INRdA), STI.getTmpRegister()) in emitPrologue()
76 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHRr)) in emitPrologue()
80 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHRr)) in emitPrologue()
83 BuildMI(MBB, MBBI, DL, TII.get(AVR::EORRdRr)) in emitPrologue()
107 BuildMI(MBB, MBBI, DL, TII.get(AVR::SPREAD), AVR::R29R28) in emitPrologue()
124 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opcode), AVR::R29R28) in emitPrologue()
132 BuildMI(MBB, MBBI, DL, TII.get(AVR::SPWRITE), AVR::SP) in emitPrologue()
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/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreFrameLowering.cpp60 const DebugLoc &dl, const TargetInstrInfo &TII, in EmitDefCfaRegister() argument
64 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in EmitDefCfaRegister()
70 const DebugLoc &dl, const TargetInstrInfo &TII, in EmitDefCfaOffset() argument
75 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in EmitDefCfaOffset()
81 const TargetInstrInfo &TII, unsigned DRegNum, in EmitCfiOffset() argument
86 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in EmitCfiOffset()
98 const TargetInstrInfo &TII, int OffsetFromTop, in IfNeededExtSP() argument
105 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(OpImm); in IfNeededExtSP()
108 EmitDefCfaOffset(MBB, MBBI, dl, TII, Adjusted*4); in IfNeededExtSP()
121 const TargetInstrInfo &TII, int OffsetFromTop, in IfNeededLDAWSP() argument
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H A DXCoreRegisterInfo.cpp57 const XCoreInstrInfo &TII, in InsertFPImmInst() argument
65 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg) in InsertFPImmInst()
71 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus)) in InsertFPImmInst()
78 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg) in InsertFPImmInst()
88 const XCoreInstrInfo &TII, in InsertFPConstInst() argument
98 TII.loadImmediate(MBB, II, ScratchOffset, Offset); in InsertFPConstInst()
102 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg) in InsertFPConstInst()
108 BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r)) in InsertFPConstInst()
115 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg) in InsertFPConstInst()
125 const XCoreInstrInfo &TII, in InsertSPImmInst() argument
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVExpandAtomicPseudoInsts.cpp34 const RISCVInstrInfo *TII; member in __anon63aa91a10111::RISCVExpandAtomicPseudo
65 Size += TII->getInstSizeInBytes(MI); in getInstSizeInBytes()
75 TII = STI->getInstrInfo(); in runOnMachineFunction()
257 static void doAtomicBinOpExpansion(const RISCVInstrInfo *TII, MachineInstr &MI, in doAtomicBinOpExpansion() argument
275 BuildMI(LoopMBB, DL, TII->get(getLRForRMW(Ordering, Width, STI)), DestReg) in doAtomicBinOpExpansion()
281 BuildMI(LoopMBB, DL, TII->get(RISCV::AND), ScratchReg) in doAtomicBinOpExpansion()
284 BuildMI(LoopMBB, DL, TII->get(RISCV::XORI), ScratchReg) in doAtomicBinOpExpansion()
289 BuildMI(LoopMBB, DL, TII->get(getSCForRMW(Ordering, Width, STI)), ScratchReg) in doAtomicBinOpExpansion()
292 BuildMI(LoopMBB, DL, TII->get(RISCV::BNE)) in doAtomicBinOpExpansion()
298 static void insertMaskedMerge(const RISCVInstrInfo *TII, DebugLoc DL, in insertMaskedMerge() argument
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/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEFrameLowering.cpp139 const VEInstrInfo &TII = *STI.getInstrInfo(); in emitPrologueInsns() local
149 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
154 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
161 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
166 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
173 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
187 const VEInstrInfo &TII = *STI.getInstrInfo(); in emitEpilogueInsns() local
197 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX17) in emitEpilogueInsns()
202 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX16) in emitEpilogueInsns()
206 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX15) in emitEpilogueInsns()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp73 const ARMBaseInstrInfo &TII; member in __anone228b8980111::ARMInstructionSelector
176 : TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), TM(TM), RBI(RBI), in ARMInstructionSelector()
213 static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII, in selectCopy() argument
226 LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode()) in selectCopy()
234 const ARMBaseInstrInfo &TII, in selectMergeValues() argument
238 assert(TII.getSubtarget().hasVFP2Base() && "Can't select merge without VFP"); in selectMergeValues()
258 MIB->setDesc(TII.get(ARM::VMOVDRR)); in selectMergeValues()
265 const ARMBaseInstrInfo &TII, in selectUnmergeValues() argument
269 assert(TII.getSubtarget().hasVFP2Base() && in selectUnmergeValues()
290 MIB->setDesc(TII.get(ARM::VMOVRRD)); in selectUnmergeValues()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaFrameLowering.cpp35 STI(STI), TII(*STI.getInstrInfo()), TRI(STI.getRegisterInfo()) {} in XtensaFrameLowering()
68 BuildMI(MBB, MBBI, DL, TII.get(Xtensa::ENTRY)) in emitPrologue()
75 BuildMI(MBB, MBBI, DL, TII.get(Xtensa::ENTRY)) in emitPrologue()
78 TII.loadImmediate(MBB, MBBI, &TmpReg, StackSize - MIN_FRAME_SIZE); in emitPrologue()
79 BuildMI(MBB, MBBI, DL, TII.get(Xtensa::SUB), TmpReg) in emitPrologue()
82 BuildMI(MBB, MBBI, DL, TII.get(Xtensa::MOVSP), SP).addReg(TmpReg); in emitPrologue()
93 TII.loadImmediate(MBB, MBBI, &RegMisAlign, MaxAlignment - 1); in emitPrologue()
94 TII.loadImmediate(MBB, MBBI, &Reg, MaxAlignment); in emitPrologue()
95 BuildMI(MBB, MBBI, DL, TII.get(Xtensa::AND)) in emitPrologue()
99 BuildMI(MBB, MBBI, DL, TII.get(Xtensa::SUB), RegMisAlign) in emitPrologue()
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