Lines Matching refs:TII
33 const SIInstrInfo *TII; member in __anon1ecff9b30111::SIShrinkInstructions
91 assert(TII->isVOP1(MI) || TII->isVOP2(MI) || TII->isVOPC(MI)); in foldImmediates()
105 if (TII->isOperandLegal(MI, Src0Idx, &MovSrc)) { in foldImmediates()
131 if (TII->commuteInstruction(MI)) { in foldImmediates()
136 TII->commuteInstruction(MI); in foldImmediates()
162 !TII->isInlineConstant(*Src.getParent(), Src.getOperandNo()); in isKImmOperand()
167 !TII->isInlineConstant(*Src.getParent(), Src.getOperandNo()); in isKUImmOperand()
174 return !TII->isInlineConstant(Src); in isKImmOrKUImmOperand()
179 return !TII->isInlineConstant(Src); in isKImmOrKUImmOperand()
194 static unsigned canModifyToInlineImmOp32(const SIInstrInfo *TII, in canModifyToInlineImmOp32() argument
197 if (TII->isInlineConstant(Src)) in canModifyToInlineImmOp32()
206 if (TII->isInlineConstant(APInt(32, ModifiedImm))) in canModifyToInlineImmOp32()
211 if (TII->isInlineConstant(APInt(32, ModifiedImm))) in canModifyToInlineImmOp32()
240 TII->commuteInstruction(MI, false, 0, 1); in shrinkScalarCompare()
266 MI.setDesc(TII->get(SOPKOpc)); in shrinkScalarCompare()
272 const MCInstrDesc &NewDesc = TII->get(SOPKOpc); in shrinkScalarCompare()
387 MI.setDesc(TII->get(NewOpcode)); in shrinkMIMG()
414 if (TII->hasAnyModifiersSet(MI)) in shrinkMadFma()
418 MachineOperand &Src0 = *TII->getNamedOperand(MI, AMDGPU::OpName::src0); in shrinkMadFma()
419 MachineOperand &Src1 = *TII->getNamedOperand(MI, AMDGPU::OpName::src1); in shrinkMadFma()
420 MachineOperand &Src2 = *TII->getNamedOperand(MI, AMDGPU::OpName::src2); in shrinkMadFma()
426 if (Src2.isImm() && !TII->isInlineConstant(Src2)) { in shrinkMadFma()
456 if (Src1.isImm() && !TII->isInlineConstant(Src1)) in shrinkMadFma()
458 else if (Src0.isImm() && !TII->isInlineConstant(Src0)) in shrinkMadFma()
491 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), TII->get(NewOpcode), in shrinkMadFma()
499 TII->removeModOperands(MI); in shrinkMadFma()
500 MI.setDesc(TII->get(NewOpcode)); in shrinkMadFma()
559 MI.setDesc(TII->get(Opc)); in shrinkScalarLogicOp()
633 TII->get(AMDGPU::IMPLICIT_DEF), Op.getReg()); in dropInstructionKeepingImpDefs()
671 unsigned Size = TII->getOpSize(MovT, 0) / 4; in matchSwap()
741 TII->get(AMDGPU::V_SWAP_B32)) in matchSwap()
779 MachineOperand *Op = TII->getNamedOperand(MI, AMDGPU::OpName::sdst); in tryReplaceDeadSDST()
797 TII = ST->getInstrInfo(); in runOnMachineFunction()
798 TRI = &TII->getRegisterInfo(); in runOnMachineFunction()
826 canModifyToInlineImmOp32(TII, Src, ModImm, /*Scalar=*/false); in runOnMachineFunction()
828 MI.setDesc(TII->get(ModOpcode)); in runOnMachineFunction()
851 if (TII->commuteInstruction(MI, false, 1, 2)) in runOnMachineFunction()
870 MI.setDesc(TII->get(Opc)); in runOnMachineFunction()
877 if (MI.isCompare() && TII->isSOPC(MI)) { in runOnMachineFunction()
891 MI.setDesc(TII->get(AMDGPU::S_MOVK_I32)); in runOnMachineFunction()
893 } else if ((ModOpc = canModifyToInlineImmOp32(TII, Src, ModImm, in runOnMachineFunction()
895 MI.setDesc(TII->get(ModOpc)); in runOnMachineFunction()
911 if (TII->isMIMG(MI.getOpcode()) && in runOnMachineFunction()
919 if (!TII->isVOP3(MI)) in runOnMachineFunction()
931 if (!TII->hasVALU32BitEncoding(MI.getOpcode())) { in runOnMachineFunction()
938 if (!TII->canShrink(MI, *MRI)) { in runOnMachineFunction()
941 if (!MI.isCommutable() || !TII->commuteInstruction(MI) || in runOnMachineFunction()
942 !TII->canShrink(MI, *MRI)) { in runOnMachineFunction()
950 if (TII->isVOPC(Op32)) { in runOnMachineFunction()
978 TII->getNamedOperand(MI, AMDGPU::OpName::src2); in runOnMachineFunction()
991 const MachineOperand *SDst = TII->getNamedOperand(MI, in runOnMachineFunction()
1005 const MachineOperand *Src2 = TII->getNamedOperand(MI, in runOnMachineFunction()
1033 MachineInstr *Inst32 = TII->buildShrunkInst(MI, Op32); in runOnMachineFunction()