Lines Matching refs:TII
293 const TargetInstrInfo &TII, in insertSEH() argument
307 report_fatal_error("No SEH Opcode for instruction " + TII.getName(Opc)); in insertSEH()
316 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop)) in insertSEH()
325 BuildMI(MF, DL, TII.get(ARM::tMOVi8)).setMIFlags(MBBI->getFlags()); in insertSEH()
334 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop)).addImm(Wide).setMIFlags(Flags); in insertSEH()
339 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop)) in insertSEH()
352 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop)) in insertSEH()
356 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop)) in insertSEH()
366 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_SaveRegs)) in insertSEH()
380 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_SaveRegs)) in insertSEH()
423 BuildMI(MF, DL, TII.get(NewOpc)).setMIFlags(MBBI->getFlags()); in insertSEH()
432 MIB = BuildMI(MF, DL, TII.get(SEHOpc)) in insertSEH()
447 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_SaveFRegs)) in insertSEH()
455 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_StackAlloc)) in insertSEH()
464 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_StackAlloc)) in insertSEH()
474 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_SaveSP)) in insertSEH()
480 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_SaveSP)) in insertSEH()
491 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop_Ret)) in insertSEH()
497 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop_Ret)) in insertSEH()
515 const ARMBaseInstrInfo &TII, unsigned MIFlags) { in insertSEHRange() argument
531 insertSEH(MI, TII, MIFlags); in insertSEHRange()
538 const DebugLoc &dl, const ARMBaseInstrInfo &TII, unsigned DestReg, in emitRegPlusImmediate() argument
543 Pred, PredReg, TII, MIFlags); in emitRegPlusImmediate()
546 Pred, PredReg, TII, MIFlags); in emitRegPlusImmediate()
551 const ARMBaseInstrInfo &TII, int NumBytes, in emitSPUpdate() argument
555 emitRegPlusImmediate(isARM, MBB, MBBI, dl, TII, ARM::SP, ARM::SP, NumBytes, in emitSPUpdate()
621 const ARMBaseInstrInfo &TII, bool HasFP) { in emitDefCFAOffsets()
632 TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitDefCFAOffsets()
649 const TargetInstrInfo &TII, in emitAligningInstructions() argument
671 BuildMI(MBB, MBBI, DL, TII.get(ARM::BFC), Reg) in emitAligningInstructions()
676 BuildMI(MBB, MBBI, DL, TII.get(ARM::BICri), Reg) in emitAligningInstructions()
686 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg) in emitAligningInstructions()
691 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg) in emitAligningInstructions()
701 BuildMI(MBB, MBBI, DL, TII.get(ARM::t2BFC), Reg) in emitAligningInstructions()
742 const ARMBaseInstrInfo &TII = *STI.getInstrInfo(); in emitPrologue() local
776 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes, in emitPrologue()
781 DefCFAOffsetCandidates.emitDefCFAOffsets(MBB, dl, TII, HasFP); in emitPrologue()
783 insertSEHRange(MBB, {}, MBBI, TII, MachineInstr::FrameSetup); in emitPrologue()
784 BuildMI(MBB, MBBI, dl, TII.get(ARM::SEH_PrologEnd)) in emitPrologue()
883 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -ArgRegsSaveSize, in emitPrologue()
940 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRGapSize, in emitPrologue()
980 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), ARM::R4) in emitPrologue()
988 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), ARM::R4) in emitPrologue()
992 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), ARM::R4) in emitPrologue()
1005 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBL)) in emitPrologue()
1012 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R12) in emitPrologue()
1016 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBLXr)) in emitPrologue()
1025 Instr = BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), ARM::SP) in emitPrologue()
1032 SEH = BuildMI(MF, dl, TII.get(ARM::SEH_StackAlloc)) in emitPrologue()
1047 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes, in emitPrologue()
1080 emitRegPlusImmediate(!AFI->isThumbFunction(), MBB, AfterPush, dl, TII, in emitPrologue()
1083 emitRegPlusImmediate(!AFI->isThumbFunction(), MBB, AfterPush, dl, TII, in emitPrologue()
1092 BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
1099 BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
1112 insertSEHRange(MBB, {}, End, TII, MachineInstr::FrameSetup); in emitPrologue()
1113 BuildMI(MBB, End, dl, TII.get(ARM::SEH_PrologEnd)) in emitPrologue()
1147 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
1172 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
1194 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
1206 DefCFAOffsetCandidates.emitDefCFAOffsets(MBB, dl, TII, HasFP); in emitPrologue()
1226 emitAligningInstructions(MF, AFI, TII, MBB, MBBI, dl, ARM::SP, MaxAlign, in emitPrologue()
1236 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4) in emitPrologue()
1239 emitAligningInstructions(MF, AFI, TII, MBB, MBBI, dl, ARM::R4, MaxAlign, in emitPrologue()
1241 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP) in emitPrologue()
1256 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), RegInfo->getBaseRegister()) in emitPrologue()
1261 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), RegInfo->getBaseRegister()) in emitPrologue()
1278 const ARMBaseInstrInfo &TII = in emitEpilogue() local
1306 BuildMI(MBB, MBBI, dl, TII.get(ARM::SEH_EpilogStart)) in emitEpilogue()
1312 emitSPUpdate(isARM, MBB, MBBI, dl, TII, in emitEpilogue()
1327 BuildMI(MBB, MBBI, dl, TII.get(ARM::SEH_EpilogStart)) in emitEpilogue()
1347 ARMCC::AL, 0, TII, in emitEpilogue()
1360 ARMCC::AL, 0, TII, MachineInstr::FrameDestroy); in emitEpilogue()
1361 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP) in emitEpilogue()
1369 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP) in emitEpilogue()
1375 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP) in emitEpilogue()
1382 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes, in emitEpilogue()
1399 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedGapSize(), in emitEpilogue()
1410 emitSPUpdate(isARM, MBB, MBBI, dl, TII, in emitEpilogue()
1424 insertSEHRange(MBB, RangeStart, MBB.end(), TII, MachineInstr::FrameDestroy); in emitEpilogue()
1425 BuildMI(MBB, MBB.end(), dl, TII.get(ARM::SEH_EpilogEnd)) in emitEpilogue()
1530 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); in emitPushInst() local
1575 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP) in emitPushInst()
1582 BuildMI(MBB, MI, DL, TII.get(StrOpc), ARM::SP) in emitPushInst()
1607 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); in emitPopInst() local
1671 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP) in emitPopInst()
1690 BuildMI(MBB, MI, DL, TII.get(LdrOpc), Regs[0]) in emitPopInst()
1723 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); in emitAlignedDPRCS2Spills() local
1762 BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4) in emitAlignedDPRCS2Spills()
1774 emitAligningInstructions(MF, AFI, TII, MBB, MI, DL, ARM::R4, MaxAlign, true); in emitAlignedDPRCS2Spills()
1781 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(Opc), ARM::SP) in emitAlignedDPRCS2Spills()
1797 BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Qwb_fixed), ARM::R4) in emitAlignedDPRCS2Spills()
1816 BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Q)) in emitAlignedDPRCS2Spills()
1831 BuildMI(MBB, MI, DL, TII.get(ARM::VST1q64)) in emitAlignedDPRCS2Spills()
1844 BuildMI(MBB, MI, DL, TII.get(ARM::VSTRD)) in emitAlignedDPRCS2Spills()
1896 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); in emitAlignedDPRCS2Restores() local
1915 BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4) in emitAlignedDPRCS2Restores()
1928 BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Qwb_fixed), NextReg) in emitAlignedDPRCS2Restores()
1946 BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Q), NextReg) in emitAlignedDPRCS2Restores()
1959 BuildMI(MBB, MI, DL, TII.get(ARM::VLD1q64), SupReg) in emitAlignedDPRCS2Restores()
1969 BuildMI(MBB, MI, DL, TII.get(ARM::VLDRD), NextReg) in emitAlignedDPRCS2Restores()
2073 const ARMBaseInstrInfo &TII) { in EstimateFunctionSizeInBytes() argument
2077 FnSize += TII.getInstSizeInBytes(MI); in EstimateFunctionSizeInBytes()
2094 const ARMBaseInstrInfo &TII = in estimateRSStackSizeLimit() local
2118 const TargetRegisterClass *RegClass = TII.getRegClass(MCID, i, TRI, MF); in estimateRSStackSizeLimit()
2282 const ARMBaseInstrInfo &TII = in determineCalleeSaves() local
2412 unsigned FnSize = EstimateFunctionSizeInBytes(MF, TII); in determineCalleeSaves()
2873 const ARMBaseInstrInfo &TII = in eliminateCallFramePseudoInstr() local
2879 bool IsDestroy = Opc == TII.getCallFrameDestroyOpcode(); in eliminateCallFramePseudoInstr()
2889 unsigned PredReg = TII.getFramePred(*I); in eliminateCallFramePseudoInstr()
2899 unsigned Amount = TII.getFrameSize(*I); in eliminateCallFramePseudoInstr()
2907 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, MachineInstr::NoFlags, in eliminateCallFramePseudoInstr()
2911 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, MachineInstr::NoFlags, in eliminateCallFramePseudoInstr()
2918 emitSPUpdate(isARM, MBB, I, dl, TII, -CalleePopAmount, in eliminateCallFramePseudoInstr()
2999 const ARMBaseInstrInfo &TII = in adjustForSegmentedStacks() local
3081 BuildMI(PrevStackMBB, DL, TII.get(ARM::tPUSH)) in adjustForSegmentedStacks()
3086 BuildMI(PrevStackMBB, DL, TII.get(ARM::STMDB_UPD)) in adjustForSegmentedStacks()
3098 BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) in adjustForSegmentedStacks()
3102 BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) in adjustForSegmentedStacks()
3106 BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) in adjustForSegmentedStacks()
3112 BuildMI(McrMBB, DL, TII.get(ARM::tMOVr), ScratchReg1) in adjustForSegmentedStacks()
3116 BuildMI(McrMBB, DL, TII.get(ARM::MOVr), ScratchReg1) in adjustForSegmentedStacks()
3125 BuildMI(McrMBB, DL, TII.get(ARM::tSUBi8), ScratchReg1) in adjustForSegmentedStacks()
3132 BuildMI(McrMBB, DL, TII.get(MovOp), ScratchReg0) in adjustForSegmentedStacks()
3140 BuildMI(McrMBB, DL, TII.get(ARM::tSUBrr), ScratchReg1) in adjustForSegmentedStacks()
3148 BuildMI(McrMBB, DL, TII.get(ARM::SUBri), ScratchReg1) in adjustForSegmentedStacks()
3158 BuildMI(McrMBB, DL, TII.get(ARM::SUBrr), ScratchReg1) in adjustForSegmentedStacks()
3168 BuildMI(GetMBB, DL, TII.get(MovOp), ScratchReg0) in adjustForSegmentedStacks()
3178 BuildMI(GetMBB, DL, TII.get(ARM::tLDRpci), ScratchReg0) in adjustForSegmentedStacks()
3184 BuildMI(GetMBB, DL, TII.get(ARM::tLDRi), ScratchReg0) in adjustForSegmentedStacks()
3191 BuildMI(McrMBB, DL, TII.get(Thumb ? ARM::t2MRC : ARM::MRC), in adjustForSegmentedStacks()
3206 BuildMI(GetMBB, DL, TII.get(Thumb ? ARM::t2LDRi12 : ARM::LDRi12), in adjustForSegmentedStacks()
3216 BuildMI(GetMBB, DL, TII.get(Opcode)) in adjustForSegmentedStacks()
3223 BuildMI(GetMBB, DL, TII.get(Opcode)) in adjustForSegmentedStacks()
3236 BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8), ScratchReg0) in adjustForSegmentedStacks()
3242 BuildMI(AllocMBB, DL, TII.get(MovOp), ScratchReg0) in adjustForSegmentedStacks()
3253 BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg0) in adjustForSegmentedStacks()
3269 BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8), ScratchReg1) in adjustForSegmentedStacks()
3275 BuildMI(AllocMBB, DL, TII.get(MovOp), ScratchReg1) in adjustForSegmentedStacks()
3287 BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg1) in adjustForSegmentedStacks()
3302 BuildMI(AllocMBB, DL, TII.get(ARM::tPUSH)) in adjustForSegmentedStacks()
3306 BuildMI(AllocMBB, DL, TII.get(ARM::STMDB_UPD)) in adjustForSegmentedStacks()
3317 BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) in adjustForSegmentedStacks()
3321 BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) in adjustForSegmentedStacks()
3327 BuildMI(AllocMBB, DL, TII.get(ARM::tBL)) in adjustForSegmentedStacks()
3331 BuildMI(AllocMBB, DL, TII.get(ARM::BL)) in adjustForSegmentedStacks()
3338 BuildMI(AllocMBB, DL, TII.get(ARM::tPOP)) in adjustForSegmentedStacks()
3341 BuildMI(AllocMBB, DL, TII.get(ARM::tMOVr), ARM::LR) in adjustForSegmentedStacks()
3345 BuildMI(AllocMBB, DL, TII.get(ARM::t2LDR_POST)) in adjustForSegmentedStacks()
3353 BuildMI(AllocMBB, DL, TII.get(ARM::LDMIA_UPD)) in adjustForSegmentedStacks()
3365 BuildMI(AllocMBB, DL, TII.get(ARM::tPOP)) in adjustForSegmentedStacks()
3370 BuildMI(AllocMBB, DL, TII.get(ARM::LDMIA_UPD)) in adjustForSegmentedStacks()
3381 BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) in adjustForSegmentedStacks()
3386 BuildMI(AllocMBB, DL, TII.get(ST->getReturnOpcode())).add(predOps(ARMCC::AL)); in adjustForSegmentedStacks()
3391 BuildMI(PostStackMBB, DL, TII.get(ARM::tPOP)) in adjustForSegmentedStacks()
3396 BuildMI(PostStackMBB, DL, TII.get(ARM::LDMIA_UPD)) in adjustForSegmentedStacks()
3407 BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) in adjustForSegmentedStacks()
3414 BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) in adjustForSegmentedStacks()
3418 BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) in adjustForSegmentedStacks()