Lines Matching refs:TII
61 const MipsInstrInfo &TII; member in __anonbf07d5ca0111::MipsInstructionSelector
83 : TM(TM), STI(STI), TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), in MipsInstructionSelector()
113 LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode()) in selectCopy()
152 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); in materialize32BitImm()
158 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); in materialize32BitImm()
165 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); in materialize32BitImm()
173 if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI)) in materialize32BitImm()
175 if (!constrainSelectedInstRegOperands(*ORi, TII, TRI, RBI)) in materialize32BitImm()
262 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opc)) in buildUnalignedStore()
267 if (!constrainSelectedInstRegOperands(*NewInst, TII, TRI, RBI)) in buildUnalignedStore()
276 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opc)) in buildUnalignedLoad()
282 if (!constrainSelectedInstRegOperands(*NewInst, TII, TRI, RBI)) in buildUnalignedLoad()
302 MachineInstr *Mul = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MUL)) in select()
306 if (!constrainSelectedInstRegOperands(*Mul, TII, TRI, RBI)) in select()
326 PseudoMULTu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoMULTu)) in select()
330 if (!constrainSelectedInstRegOperands(*PseudoMULTu, TII, TRI, RBI)) in select()
333 PseudoMove = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoMFHI)) in select()
336 if (!constrainSelectedInstRegOperands(*PseudoMove, TII, TRI, RBI)) in select()
343 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu)) in select()
351 I.setDesc(TII.get(COPY)); in select()
355 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu)) in select()
368 MachineInstr *SLL = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SLL)) in select()
372 if (!constrainSelectedInstRegOperands(*SLL, TII, TRI, RBI)) in select()
376 MachineInstr *ADDu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu)) in select()
380 if (!constrainSelectedInstRegOperands(*ADDu, TII, TRI, RBI)) in select()
385 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW)) in select()
391 if (!constrainSelectedInstRegOperands(*LW, TII, TRI, RBI)) in select()
397 MachineInstr *ADDu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu)) in select()
402 if (!constrainSelectedInstRegOperands(*ADDu, TII, TRI, RBI)) in select()
407 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoIndirectBranch)) in select()
409 if (!constrainSelectedInstRegOperands(*Branch, TII, TRI, RBI)) in select()
416 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoIndirectBranch)) in select()
429 I.setDesc(TII.get(TargetOpcode::PHI)); in select()
476 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::IMPLICIT_DEF)) in select()
496 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(NewOpc)) in select()
513 TII.get(IsSigned ? Mips::PseudoSDIV : Mips::PseudoUDIV)) in select()
517 if (!constrainSelectedInstRegOperands(*PseudoDIV, TII, TRI, RBI)) in select()
521 TII.get(IsDiv ? Mips::PseudoMFLO : Mips::PseudoMFHI)) in select()
524 if (!constrainSelectedInstRegOperands(*PseudoMove, TII, TRI, RBI)) in select()
532 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MOVN_I_I)) in select()
552 MachineInstr *ExtractLo = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode)) in select()
556 if (!constrainSelectedInstRegOperands(*ExtractLo, TII, TRI, RBI)) in select()
559 MachineInstr *ExtractHi = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode)) in select()
563 if (!constrainSelectedInstRegOperands(*ExtractHi, TII, TRI, RBI)) in select()
571 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::IMPLICIT_DEF)) in select()
600 if (!MTC1.constrainAllUses(TII, TRI, RBI)) in select()
615 if (!PairF64.constrainAllUses(TII, TRI, RBI)) in select()
627 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(FABSOpcode)) in select()
646 MachineInstr *Trunc = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode)) in select()
649 if (!constrainSelectedInstRegOperands(*Trunc, TII, TRI, RBI)) in select()
652 MachineInstr *Move = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MFC1)) in select()
655 if (!constrainSelectedInstRegOperands(*Move, TII, TRI, RBI)) in select()
664 MachineInstr *LWGOT = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW)) in select()
680 if (!constrainSelectedInstRegOperands(*LWGOT, TII, TRI, RBI)) in select()
688 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu)) in select()
693 if (!constrainSelectedInstRegOperands(*ADDiu, TII, TRI, RBI)) in select()
699 MachineInstr *LUi = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi)) in select()
703 if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI)) in select()
707 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu)) in select()
712 if (!constrainSelectedInstRegOperands(*ADDiu, TII, TRI, RBI)) in select()
720 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW)) in select()
730 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi)) in select()
809 if (!MIB.constrainAllUses(TII, TRI, RBI)) in select()
867 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu)) in select()
876 MachineInstr *FCMP = BuildMI(MBB, I, I.getDebugLoc(), TII.get(FCMPOpcode)) in select()
880 if (!constrainSelectedInstRegOperands(*FCMP, TII, TRI, RBI)) in select()
883 MachineInstr *Move = BuildMI(MBB, I, I.getDebugLoc(), TII.get(MoveOpcode)) in select()
888 if (!constrainSelectedInstRegOperands(*Move, TII, TRI, RBI)) in select()
895 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SYNC)).addImm(0); in select()
904 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LEA_ADDiu)) in select()
908 if (!constrainSelectedInstRegOperands(*LEA_ADDiu, TII, TRI, RBI)) in select()
911 MachineInstr *Store = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SW)) in select()
915 if (!constrainSelectedInstRegOperands(*Store, TII, TRI, RBI)) in select()
926 return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI); in select()