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Searched refs:SDValue (Results 1 – 25 of 162) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypes.h86 // Bijection from SDValue to unique id. As each created node gets a
93 SmallDenseMap<SDValue, TableId, 8> ValueToIdMap;
94 SmallDenseMap<TableId, SDValue, 8> IdToValueMap;
140 TableId getTableId(SDValue V) { in getTableId()
141 assert(V.getNode() && "Getting TableId on SDValue()"); in getTableId()
159 const SDValue &getSDValue(TableId &Id) { in getSDValue()
181 TableId NewId = getTableId(SDValue(New, i)); in NoteDeletion()
182 TableId OldId = getTableId(SDValue(Old, i)); in NoteDeletion()
202 ValueToIdMap.erase(SDValue(Old, i)); in NoteDeletion()
210 void AnalyzeNewValue(SDValue
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.h27 static inline bool getConstantValue(SDValue N, uint32_t &Out) { in getConstantValue()
96 std::pair<SDValue, SDValue> foldFrameIndex(SDValue N) const;
116 bool isBaseWithConstantOffset64(SDValue Addr, SDValue &LHS,
117 SDValue &RHS) const;
121 SDNode *glueCopyToOp(SDNode *N, SDValue NewChain, SDValue Glue) const;
122 SDNode *glueCopyToM0(SDNode *N, SDValue Val) const;
126 virtual bool SelectADDRVTX_READ(SDValue Addr, SDValue &Base, SDValue &Offset);
127 virtual bool SelectADDRIndirect(SDValue Addr, SDValue &Base, SDValue &Offset);
128 bool isDSOffsetLegal(SDValue Base, unsigned Offset) const;
129 bool isDSOffset2Legal(SDValue Base, unsigned Offset0, unsigned Offset1,
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H A DSIISelLowering.h48 SDValue lowerKernArgParameterPtr(SelectionDAG &DAG, const SDLoc &SL,
49 SDValue Chain, uint64_t Offset) const;
50 SDValue getImplicitArgPtr(SelectionDAG &DAG, const SDLoc &SL) const;
51 SDValue getLDSKernelId(SelectionDAG &DAG, const SDLoc &SL) const;
52 SDValue lowerKernargMemParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
53 const SDLoc &SL, SDValue Chain,
57 SDValue loadImplicitKernelArgument(SelectionDAG &DAG, MVT VT, const SDLoc &DL,
61 SDValue lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA,
62 const SDLoc &SL, SDValue Chain,
64 SDValue getPreloadedValue(SelectionDAG &DAG,
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H A DAMDGPUISelLowering.h35 SDValue getFFBX_U32(SelectionDAG &DAG, SDValue Op, const SDLoc &DL, unsigned Opc) const;
41 static unsigned numBitsUnsigned(SDValue Op, SelectionDAG &DAG);
46 static unsigned numBitsSigned(SDValue Op, SelectionDAG &DAG);
49 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
50 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
54 SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
55 SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
56 SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
57 SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
58 SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
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H A DR600ISelLowering.h35 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
36 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
38 SmallVectorImpl<SDValue> &Results,
41 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
45 SmallVectorImpl<SDValue> &InVals) const override;
72 SDValue LowerImplicitParameter(SelectionDAG &DAG, EVT VT, const SDLoc &DL,
77 SDValue OptimizeSwizzle(SDValue BuildVector, SDValue Swz[],
79 SDValue vectorToVerticalVector(SelectionDAG &DAG, SDValue Vector) const;
81 SDValue lowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
82 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.h139 bool IsEligibleForTailCallOptimization(SDValue Callee,
142 const SmallVectorImpl<SDValue> &OutVals,
156 bool hasBitTest(SDValue X, SDValue Y) const override;
173 bool isTargetCanonicalConstantNode(SDValue Op) const override;
179 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
180 void LowerOperationWrapper(SDNode *N, SmallVectorImpl<SDValue> &Results,
182 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
187 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
188 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
189 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelDAGToDAG.h33 unsigned getMSACtrlReg(const SDValue RegIdx) const;
43 bool selectAddrFrameIndex(SDValue Addr, SDValue &Base, SDValue &Offset) const;
44 bool selectAddrFrameIndexOffset(SDValue Addr, SDValue &Base, SDValue &Offset,
48 bool selectAddrRegImm(SDValue Addr, SDValue &Base,
49 SDValue &Offset) const override;
51 bool selectAddrDefault(SDValue Addr, SDValue &Base,
52 SDValue &Offset) const override;
54 bool selectIntAddr(SDValue Addr, SDValue &Base,
55 SDValue &Offset) const override;
57 bool selectAddrRegImm9(SDValue Addr, SDValue &Base,
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H A DMipsISelDAGToDAG.h53 virtual bool selectAddrRegImm(SDValue Addr, SDValue &Base,
54 SDValue &Offset) const;
57 virtual bool selectAddrDefault(SDValue Addr, SDValue &Base,
58 SDValue &Offset) const;
61 virtual bool selectIntAddr(SDValue Addr, SDValue &Base,
62 SDValue &Offset) const;
64 virtual bool selectIntAddr11MM(SDValue Addr, SDValue &Base,
65 SDValue &Offset) const;
67 virtual bool selectIntAddr12MM(SDValue Addr, SDValue &Base,
68 SDValue &Offset) const;
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H A DMipsISelDAGToDAG.cpp79 bool MipsDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base, in selectAddrRegImm()
80 SDValue &Offset) const { in selectAddrRegImm()
85 bool MipsDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base, in selectAddrDefault()
86 SDValue &Offset) const { in selectAddrDefault()
91 bool MipsDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base, in selectIntAddr()
92 SDValue &Offset) const { in selectIntAddr()
97 bool MipsDAGToDAGISel::selectIntAddr11MM(SDValue Addr, SDValue &Base, in selectIntAddr11MM()
98 SDValue &Offset) const { in selectIntAddr11MM()
103 bool MipsDAGToDAGISel::selectIntAddr12MM(SDValue Addr, SDValue &Base, in selectIntAddr12MM()
104 SDValue &Offset) const { in selectIntAddr12MM()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAG.h259 SDValue Root;
436 void createOperands(SDNode *Node, ArrayRef<SDValue> Vals);
565 const SDValue &getRoot() const { return Root; }
568 SDValue getEntryNode() const {
569 return SDValue(const_cast<SDNode *>(&EntryNode), 0);
574 const SDValue &setRoot(SDValue N) {
668 SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT,
670 SDValue getConstant(const APInt &Val, const SDLoc &DL, EVT VT,
673 SDValue getAllOnesConstant(const SDLoc &DL, EVT VT, bool IsTarget = false,
679 SDValue getConstant(const ConstantInt &Val, const SDLoc &DL, EVT VT,
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H A DSelectionDAGTargetInfo.h42 /// SDValue if the target declines to use custom code and a different
51 virtual SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl, in EmitTargetCodeForMemcpy()
52 SDValue Chain, SDValue Op1, in EmitTargetCodeForMemcpy()
53 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcpy()
58 return SDValue(); in EmitTargetCodeForMemcpy()
65 /// SDValue if the target declines to use custom code and a different
67 virtual SDValue EmitTargetCodeForMemmove( in EmitTargetCodeForMemmove()
68 SelectionDAG &DAG, const SDLoc &dl, SDValue Chai in EmitTargetCodeForMemmove()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h566 bool isReassocProfitable(SelectionDAG &DAG, SDValue N0,
567 SDValue N1) const override;
577 void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
582 unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
595 bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits,
614 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
618 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
642 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
678 bool shouldRemoveRedundantExtend(SDValue Op) const override;
687 bool isZExtFree(SDValue Val, EVT VT2) const override;
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/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVECustomDAG.h36 bool isMaskArithmetic(SDValue Op);
44 bool maySafelyIgnoreMask(SDValue Op);
77 bool isLegalAVL(SDValue AVL);
80 SDValue getNodeAVL(SDValue);
85 SDValue getNodeMask(SDValue);
89 std::pair<SDValue, bool> getAnnotatedNodeAVL(SDValue);
97 SDValue getLoadStoreStride(SDValue Op, VECustomDAG &CDAG);
99 SDValue getMemoryPtr(SDValue Op);
101 SDValue getNodeChain(SDValue Op);
103 SDValue getStoredValue(SDValue Op);
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H A DVEISelLowering.h182 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
186 SmallVectorImpl<SDValue> &InVals) const override;
188 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
189 SmallVectorImpl<SDValue> &InVals) const override;
195 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
197 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl,
219 SDValue LowerOperation(SDValue O
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.h697 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
818 bool hasAndNotCompare(SDValue) const override { in hasAndNotCompare() argument
828 SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps,
844 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
845 SDValue &Offset,
851 bool SelectAddressEVXRegReg(SDValue N, SDValue &Base, SDValue &Index,
858 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
867 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
870 bool SelectAddressRegImm34(SDValue N, SDValue &Disp, SDValue &Base,
875 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.h44 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
46 std::vector<SDValue> &OutOps) override;
48 bool SelectAddrFrameIndex(SDValue Addr, SDValue &Base, SDValue &Offset);
49 bool SelectFrameAddrRegImm(SDValue Addr, SDValue &Base, SDValue &Offset);
50 bool SelectAddrRegImm(SDValue Addr, SDValue &Base, SDValue &Offset,
52 bool SelectAddrRegImmINX(SDValue Addr, SDValue &Base, SDValue &Offset) { in SelectAddrRegImmINX()
55 bool SelectAddrRegImmLsb00000(SDValue Addr, SDValue &Base, SDValue &Offset);
57 bool SelectAddrRegRegScale(SDValue Addr, unsigned MaxShiftAmount,
58 SDValue &Base, SDValue &Index, SDValue &Scale);
61 bool SelectAddrRegRegScale(SDValue Addr, SDValue &Base, SDValue &Index, in SelectAddrRegRegScale()
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H A DRISCVISelLowering.h500 bool isTruncateFree(SDValue Val, EVT VT2) const override;
501 bool isZExtFree(SDValue Val, EVT VT2) const override;
507 bool hasAndNotCompare(SDValue Y) const override;
508 bool hasBitTest(SDValue X, SDValue Y) const override;
510 SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y,
521 bool shouldScalarizeBinop(SDValue VecOp) const override;
590 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
591 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
594 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
596 bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits,
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/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.h95 bool isZExtFree(SDValue Val, EVT VT2) const override;
104 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
109 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
143 SDValue LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv,
147 SmallVectorImpl<SDValue> &InVals) const;
148 SDValue LowerCCCCallTo(SDValue Chain, SDValue Calle
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/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.h137 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
150 SDValue getPICJumpTableRelocBase(SDValue Table,
166 void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint,
167 std::vector<SDValue> &Ops,
206 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
210 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
211 SDValue Chai
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.h521 void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint,
522 std::vector<SDValue> &Ops,
582 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
583 void LowerOperationWrapper(SDNode *N, SmallVectorImpl<SDValue> &Results,
585 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
591 SelectionDAG & DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
594 SDValue joinRegisterPartsIntoValue(
595 SelectionDAG & DAG, const SDLoc &DL, const SDValue *Parts,
598 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
602 SmallVectorImpl<SDValue> &InVals) const override;
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H A DSystemZSelectionDAGInfo.h24 SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &DL,
25 SDValue Chain, SDValue Dst, SDValue Src,
26 SDValue Size, Align Alignment,
31 SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, const SDLoc &DL,
32 SDValue Chain, SDValue Dst, SDValue Byte,
33 SDValue Size, Align Alignment,
37 std::pair<SDValue, SDValue>
38 EmitTargetCodeForMemcmp(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain,
39 SDValue Src1, SDValue Src2, SDValue Size,
43 std::pair<SDValue, SDValue>
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H A DSystemZSelectionDAGInfo.cpp24 static SDValue createMemMemNode(SelectionDAG &DAG, const SDLoc &DL, unsigned Op, in createMemMemNode()
25 SDValue Chain, SDValue Dst, SDValue Src, in createMemMemNode()
26 SDValue LenAdj, SDValue Byte) { in createMemMemNode()
29 SmallVector<SDValue, 6> Ops; in createMemMemNode()
41 static SDValue emitMemMemImm(SelectionDAG &DAG, const SDLoc &DL, unsigned Op, in emitMemMemImm()
42 SDValue Chain, SDValue Dst, SDValue Src, in emitMemMemImm()
43 uint64_t Size, SDValue Byte = SDValue()) { in emitMemMemImm()
46 SDValue LenAdj = DAG.getConstant(Size - Adj, DL, Dst.getValueType()); in emitMemMemImm()
50 static SDValue emitMemMemReg(SelectionDAG &DAG, const SDLoc &DL, unsigned Op, in emitMemMemReg()
51 SDValue Chain, SDValue Dst, SDValue Src, in emitMemMemReg()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.h72 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
78 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
79 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
80 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
81 SDValue LowerDYNAMIC_STACKALLOC(SDValue O
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.h405 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
409 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
432 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
433 SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const;
434 SDValue PerformCMOVToBFICombine(SDNode *N, SelectionDAG &DAG) const;
435 SDValue PerformIntrinsicCombine(SDNode *N, DAGCombinerInfo &DCI) const;
436 SDValue PerformMVEExtCombine(SDNode *N, DAGCombinerInfo &DCI) const;
437 SDValue PerformMVETruncCombine(SDNode *N, DAGCombinerInfo &DCI) const;
438 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
440 bool SimplifyDemandedBitsForTargetNode(SDValue Op,
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/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.h57 bool shouldScalarizeBinop(SDValue VecOp) const override;
77 bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
87 void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
95 SDValue LowerCall(CallLoweringInfo &CLI,
96 SmallVectorImpl<SDValue> &InVals) const override;
101 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
103 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl,
105 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
109 SmallVectorImpl<SDValue> &InVals) const override;
111 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
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