Lines Matching refs:SDValue
35 SDValue getFFBX_U32(SelectionDAG &DAG, SDValue Op, const SDLoc &DL, unsigned Opc) const;
41 static unsigned numBitsUnsigned(SDValue Op, SelectionDAG &DAG);
46 static unsigned numBitsSigned(SDValue Op, SelectionDAG &DAG);
49 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
50 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
54 SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
55 SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
56 SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
57 SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
58 SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
60 SDValue LowerFROUNDEVEN(SDValue Op, SelectionDAG &DAG) const;
61 SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
62 SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
65 static bool needsDenormHandlingF32(const SelectionDAG &DAG, SDValue Src,
67 SDValue getIsLtSmallestNormal(SelectionDAG &DAG, SDValue Op,
69 SDValue getIsFinite(SelectionDAG &DAG, SDValue Op, SDNodeFlags Flags) const;
70 std::pair<SDValue, SDValue> getScaledLogInput(SelectionDAG &DAG,
71 const SDLoc SL, SDValue Op,
74 SDValue LowerFLOG2(SDValue Op, SelectionDAG &DAG) const;
75 SDValue LowerFLOGCommon(SDValue Op, SelectionDAG &DAG) const;
76 SDValue LowerFLOG10(SDValue Op, SelectionDAG &DAG) const;
77 SDValue LowerFLOGUnsafe(SDValue Op, const SDLoc &SL, SelectionDAG &DAG,
79 SDValue lowerFEXP2(SDValue Op, SelectionDAG &DAG) const;
81 SDValue lowerFEXPUnsafe(SDValue Op, const SDLoc &SL, SelectionDAG &DAG,
83 SDValue lowerFEXP10Unsafe(SDValue Op, const SDLoc &SL, SelectionDAG &DAG,
85 SDValue lowerFEXP(SDValue Op, SelectionDAG &DAG) const;
87 SDValue lowerCTLZResults(SDValue Op, SelectionDAG &DAG) const;
89 SDValue LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const;
91 SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const;
92 SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
93 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
94 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
96 SDValue LowerFP_TO_INT64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
97 SDValue LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const;
98 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
100 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
104 SDValue performLoadCombine(SDNode *N, DAGCombinerInfo &DCI) const;
105 SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const;
106 SDValue performAssertSZExtCombine(SDNode *N, DAGCombinerInfo &DCI) const;
107 SDValue performIntrinsicWOChainCombine(SDNode *N, DAGCombinerInfo &DCI) const;
109 SDValue splitBinaryBitConstantOpImpl(DAGCombinerInfo &DCI, const SDLoc &SL,
110 unsigned Opc, SDValue LHS,
112 SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
113 SDValue performSraCombine(SDNode *N, DAGCombinerInfo &DCI) const;
114 SDValue performSrlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
115 SDValue performTruncateCombine(SDNode *N, DAGCombinerInfo &DCI) const;
116 SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const;
117 SDValue performMulLoHiCombine(SDNode *N, DAGCombinerInfo &DCI) const;
118 SDValue performMulhsCombine(SDNode *N, DAGCombinerInfo &DCI) const;
119 SDValue performMulhuCombine(SDNode *N, DAGCombinerInfo &DCI) const;
120 SDValue performCtlz_CttzCombine(const SDLoc &SL, SDValue Cond, SDValue LHS,
121 SDValue RHS, DAGCombinerInfo &DCI) const;
123 SDValue foldFreeOpFromSelect(TargetLowering::DAGCombinerInfo &DCI,
124 SDValue N) const;
125 SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const;
130 bool isConstantCostlierToNegate(SDValue N) const;
131 bool isConstantCheaperToNegate(SDValue N) const;
132 SDValue performFNegCombine(SDNode *N, DAGCombinerInfo &DCI) const;
133 SDValue performFAbsCombine(SDNode *N, DAGCombinerInfo &DCI) const;
134 SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const;
138 virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
142 std::pair<SDValue, SDValue> split64BitValue(SDValue Op,
144 SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const;
145 SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const;
154 std::pair<SDValue, SDValue> splitVector(const SDValue &N, const SDLoc &DL,
159 SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const;
163 SDValue WidenOrSplitVectorLoad(SDValue Op, SelectionDAG &DAG) const;
166 SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const;
168 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
169 SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
170 SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
171 SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const;
172 void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG,
173 SmallVectorImpl<SDValue> &Results) const;
182 bool mayIgnoreSignedZero(SDValue Op) const;
184 static inline SDValue stripBitcast(SDValue Val) { in stripBitcast()
188 static bool shouldFoldFNegIntoSrc(SDNode *FNeg, SDValue FNegSrc);
199 SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG,
250 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
252 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
255 SDValue addTokenForArgument(SDValue Chain,
260 SDValue lowerUnhandledCall(CallLoweringInfo &CLI,
261 SmallVectorImpl<SDValue> &InVals,
263 SDValue LowerCall(CallLoweringInfo &CLI,
264 SmallVectorImpl<SDValue> &InVals) const override;
266 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
267 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
268 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
270 SmallVectorImpl<SDValue> &Results,
273 SDValue combineFMinMaxLegacyImpl(const SDLoc &DL, EVT VT, SDValue LHS,
274 SDValue RHS, SDValue True, SDValue False,
275 SDValue CC, DAGCombinerInfo &DCI) const;
277 SDValue combineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS,
278 SDValue RHS, SDValue True, SDValue False,
279 SDValue CC, DAGCombinerInfo &DCI) const;
293 bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override { in isFsqrtCheap()
296 SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
299 SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
308 void computeKnownBitsForTargetNode(const SDValue Op,
314 unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts,
324 bool isKnownNeverNaNForTargetNode(SDValue Op,
337 SDValue CreateLiveInRegister(SelectionDAG &DAG,
342 SDValue CreateLiveInRegister(SelectionDAG &DAG, in CreateLiveInRegister()
349 SDValue CreateLiveInRegisterRaw(SelectionDAG &DAG, in CreateLiveInRegisterRaw()
357 SDValue loadStackInputValue(SelectionDAG &DAG,
362 SDValue storeStackInputValue(SelectionDAG &DAG,
364 SDValue Chain,
365 SDValue ArgVal,
368 SDValue loadInputValue(SelectionDAG &DAG,