Lines Matching refs:SDValue
35 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
36 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
38 SmallVectorImpl<SDValue> &Results,
41 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
45 SmallVectorImpl<SDValue> &InVals) const override;
72 SDValue LowerImplicitParameter(SelectionDAG &DAG, EVT VT, const SDLoc &DL,
77 SDValue OptimizeSwizzle(SDValue BuildVector, SDValue Swz[],
79 SDValue vectorToVerticalVector(SelectionDAG &DAG, SDValue Vector) const;
81 SDValue lowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
82 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
83 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
84 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
86 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
88 SDValue lowerPrivateTruncStore(StoreSDNode *Store, SelectionDAG &DAG) const;
89 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
90 SDValue lowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
91 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
93 SDValue lowerPrivateExtLoad(SDValue Op, SelectionDAG &DAG) const;
94 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
95 SDValue lowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) const;
96 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
97 SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
98 SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) const;
99 SDValue LowerUADDSUBO(SDValue Op, SelectionDAG &DAG,
102 SDValue stackPtrToRegIndex(SDValue Ptr, unsigned StackWidth,
106 bool isZero(SDValue Op) const;
107 bool isHWTrueValue(SDValue Op) const;
108 bool isHWFalseValue(SDValue Op) const;
110 bool FoldOperand(SDNode *ParentNode, unsigned SrcIdx, SDValue &Src,
111 SDValue &Neg, SDValue &Abs, SDValue &Sel, SDValue &Imm,
113 SDValue constBufferLoad(LoadSDNode *LoadNode, int Block,