Lines Matching refs:SDValue
500 bool isTruncateFree(SDValue Val, EVT VT2) const override;
501 bool isZExtFree(SDValue Val, EVT VT2) const override;
507 bool hasAndNotCompare(SDValue Y) const override;
508 bool hasBitTest(SDValue X, SDValue Y) const override;
510 SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y,
521 bool shouldScalarizeBinop(SDValue VecOp) const override;
590 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
591 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
594 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
596 bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits,
600 void computeKnownBitsForTargetNode(const SDValue Op,
605 unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
610 bool canCreateUndefOrPoisonForTargetNode(SDValue Op,
640 void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint,
641 std::vector<SDValue> &Ops,
733 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
737 SmallVectorImpl<SDValue> &InVals) const override;
742 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
744 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
746 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
747 SmallVectorImpl<SDValue> &InVals) const override;
751 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
756 SDValue C) const override;
758 bool isMulAddWithConstProfitable(SDValue AddNode,
759 SDValue ConstNode) const override;
786 SelectionDAG & DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
790 SDValue joinRegisterPartsIntoValue(
791 SelectionDAG & DAG, const SDLoc &DL, const SDValue *Parts,
796 SDValue computeVLMax(MVT VecVT, const SDLoc &DL, SelectionDAG &DAG) const;
823 bool shouldRemoveExtendFromGSIndex(SDValue Extend, EVT DataVT) const override;
838 bool getIndexedAddressParts(SDNode *Op, SDValue &Base, SDValue &Offset,
840 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
843 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
844 SDValue &Offset, ISD::MemIndexedMode &AM,
887 SDValue expandIndirectJTBranch(const SDLoc &dl, SDValue Value, SDValue Addr,
915 SDValue getAddr(NodeTy *N, SelectionDAG &DAG, bool IsLocal = true,
917 SDValue getStaticTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG,
919 SDValue getDynamicTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG) const;
920 SDValue getTLSDescAddr(GlobalAddressSDNode *N, SelectionDAG &DAG) const;
922 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
923 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
924 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
925 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
926 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
927 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
928 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
929 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
930 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
931 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
932 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
933 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const;
934 SDValue lowerSPLAT_VECTOR_PARTS(SDValue Op, SelectionDAG &DAG) const;
935 SDValue lowerVectorMaskSplat(SDValue Op, SelectionDAG &DAG) const;
936 SDValue lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG,
938 SDValue lowerVectorMaskTruncLike(SDValue Op, SelectionDAG &DAG) const;
939 SDValue lowerVectorTruncLike(SDValue Op, SelectionDAG &DAG) const;
940 SDValue lowerVectorFPExtendOrRoundLike(SDValue Op, SelectionDAG &DAG) const;
941 SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
942 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
943 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
944 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
945 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
946 SDValue lowerVPREDUCE(SDValue Op, SelectionDAG &DAG) const;
947 SDValue lowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
948 SDValue lowerVectorMaskVecReduction(SDValue Op, SelectionDAG &DAG,
950 SDValue lowerFPVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
951 SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
952 SDValue lowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
953 SDValue lowerVECTOR_DEINTERLEAVE(SDValue Op, SelectionDAG &DAG) const;
954 SDValue lowerVECTOR_INTERLEAVE(SDValue Op, SelectionDAG &DAG) const;
955 SDValue lowerSTEP_VECTOR(SDValue Op, SelectionDAG &DAG) const;
956 SDValue lowerVECTOR_REVERSE(SDValue Op, SelectionDAG &DAG) const;
957 SDValue lowerVECTOR_SPLICE(SDValue Op, SelectionDAG &DAG) const;
958 SDValue lowerABS(SDValue Op, SelectionDAG &DAG) const;
959 SDValue lowerMaskedLoad(SDValue Op, SelectionDAG &DAG) const;
960 SDValue lowerMaskedStore(SDValue Op, SelectionDAG &DAG) const;
961 SDValue lowerFixedLengthVectorFCOPYSIGNToRVV(SDValue Op,
963 SDValue lowerMaskedGather(SDValue Op, SelectionDAG &DAG) const;
964 SDValue lowerMaskedScatter(SDValue Op, SelectionDAG &DAG) const;
965 SDValue lowerFixedLengthVectorLoadToRVV(SDValue Op, SelectionDAG &DAG) const;
966 SDValue lowerFixedLengthVectorStoreToRVV(SDValue Op, SelectionDAG &DAG) const;
967 SDValue lowerFixedLengthVectorSetccToRVV(SDValue Op, SelectionDAG &DAG) const;
968 SDValue lowerFixedLengthVectorSelectToRVV(SDValue Op,
970 SDValue lowerToScalableOp(SDValue Op, SelectionDAG &DAG) const;
971 SDValue LowerIS_FPCLASS(SDValue Op, SelectionDAG &DAG) const;
972 SDValue lowerVPOp(SDValue Op, SelectionDAG &DAG) const;
973 SDValue lowerLogicVPOp(SDValue Op, SelectionDAG &DAG) const;
974 SDValue lowerVPExtMaskOp(SDValue Op, SelectionDAG &DAG) const;
975 SDValue lowerVPSetCCMaskOp(SDValue Op, SelectionDAG &DAG) const;
976 SDValue lowerVPSplatExperimental(SDValue Op, SelectionDAG &DAG) const;
977 SDValue lowerVPSpliceExperimental(SDValue Op, SelectionDAG &DAG) const;
978 SDValue lowerVPReverseExperimental(SDValue Op, SelectionDAG &DAG) const;
979 SDValue lowerVPFPIntConvOp(SDValue Op, SelectionDAG &DAG) const;
980 SDValue lowerVPStridedLoad(SDValue Op, SelectionDAG &DAG) const;
981 SDValue lowerVPStridedStore(SDValue Op, SelectionDAG &DAG) const;
982 SDValue lowerVPCttzElements(SDValue Op, SelectionDAG &DAG) const;
983 SDValue lowerFixedLengthVectorExtendToRVV(SDValue Op, SelectionDAG &DAG,
985 SDValue lowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
986 SDValue lowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
988 SDValue lowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
989 SDValue lowerCTLZ_CTTZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) const;
991 SDValue lowerStrictFPExtendOrRoundLike(SDValue Op, SelectionDAG &DAG) const;
993 SDValue lowerVectorStrictFSetcc(SDValue Op, SelectionDAG &DAG) const;
995 SDValue expandUnalignedRVVLoad(SDValue Op, SelectionDAG &DAG) const;
996 SDValue expandUnalignedRVVStore(SDValue Op, SelectionDAG &DAG) const;
1005 const SmallVectorImpl<std::pair<llvm::Register, llvm::SDValue>> &Regs,
1035 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
1043 SDValue emitFlushICache(SelectionDAG &DAG, SDValue InChain, SDValue Start,
1044 SDValue End, SDValue Flags, SDLoc DL) const;