10b57cec5SDimitry Andric //==-- AArch64ISelLowering.h - AArch64 DAG Lowering Interface ----*- C++ -*-==// 20b57cec5SDimitry Andric // 30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric // 70b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric // 90b57cec5SDimitry Andric // This file defines the interfaces that AArch64 uses to lower LLVM code into a 100b57cec5SDimitry Andric // selection DAG. 110b57cec5SDimitry Andric // 120b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 130b57cec5SDimitry Andric 140b57cec5SDimitry Andric #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H 150b57cec5SDimitry Andric #define LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H 160b57cec5SDimitry Andric 170b57cec5SDimitry Andric #include "AArch64.h" 18bdd1243dSDimitry Andric #include "Utils/AArch64SMEAttributes.h" 190b57cec5SDimitry Andric #include "llvm/CodeGen/CallingConvLower.h" 20fe6060f1SDimitry Andric #include "llvm/CodeGen/MachineFunction.h" 210b57cec5SDimitry Andric #include "llvm/CodeGen/SelectionDAG.h" 220b57cec5SDimitry Andric #include "llvm/CodeGen/TargetLowering.h" 230b57cec5SDimitry Andric #include "llvm/IR/CallingConv.h" 240b57cec5SDimitry Andric #include "llvm/IR/Instruction.h" 250b57cec5SDimitry Andric 260b57cec5SDimitry Andric namespace llvm { 270b57cec5SDimitry Andric 280b57cec5SDimitry Andric namespace AArch64ISD { 290b57cec5SDimitry Andric 305ffd83dbSDimitry Andric // For predicated nodes where the result is a vector, the operation is 315ffd83dbSDimitry Andric // controlled by a governing predicate and the inactive lanes are explicitly 325ffd83dbSDimitry Andric // defined with a value, please stick the following naming convention: 335ffd83dbSDimitry Andric // 345ffd83dbSDimitry Andric // _MERGE_OP<n> The result value is a vector with inactive lanes equal 355ffd83dbSDimitry Andric // to source operand OP<n>. 365ffd83dbSDimitry Andric // 375ffd83dbSDimitry Andric // _MERGE_ZERO The result value is a vector with inactive lanes 385ffd83dbSDimitry Andric // actively zeroed. 395ffd83dbSDimitry Andric // 405ffd83dbSDimitry Andric // _MERGE_PASSTHRU The result value is a vector with inactive lanes equal 415ffd83dbSDimitry Andric // to the last source operand which only purpose is being 425ffd83dbSDimitry Andric // a passthru value. 435ffd83dbSDimitry Andric // 445ffd83dbSDimitry Andric // For other cases where no explicit action is needed to set the inactive lanes, 455ffd83dbSDimitry Andric // or when the result is not a vector and it is needed or helpful to 465ffd83dbSDimitry Andric // distinguish a node from similar unpredicated nodes, use: 475ffd83dbSDimitry Andric // 485ffd83dbSDimitry Andric // _PRED 495ffd83dbSDimitry Andric // 500b57cec5SDimitry Andric enum NodeType : unsigned { 510b57cec5SDimitry Andric FIRST_NUMBER = ISD::BUILTIN_OP_END, 520b57cec5SDimitry Andric WrapperLarge, // 4-instruction MOVZ/MOVK sequence for 64-bit addresses. 530b57cec5SDimitry Andric CALL, // Function call. 540b57cec5SDimitry Andric 55fe6060f1SDimitry Andric // Pseudo for a OBJC call that gets emitted together with a special `mov 56fe6060f1SDimitry Andric // x29, x29` marker instruction. 57fe6060f1SDimitry Andric CALL_RVMARKER, 58fe6060f1SDimitry Andric 593a9a9c0cSDimitry Andric CALL_BTI, // Function call followed by a BTI instruction. 603a9a9c0cSDimitry Andric 610fca6ea1SDimitry Andric // Function call, authenticating the callee value first: 620fca6ea1SDimitry Andric // AUTH_CALL chain, callee, auth key #, int disc, addr disc, operands. 630fca6ea1SDimitry Andric AUTH_CALL, 640fca6ea1SDimitry Andric // AUTH_TC_RETURN chain, callee, fpdiff, auth key #, int disc, addr disc, 650fca6ea1SDimitry Andric // operands. 660fca6ea1SDimitry Andric AUTH_TC_RETURN, 670fca6ea1SDimitry Andric 680fca6ea1SDimitry Andric // Authenticated variant of CALL_RVMARKER. 690fca6ea1SDimitry Andric AUTH_CALL_RVMARKER, 700fca6ea1SDimitry Andric 71b3edf446SDimitry Andric COALESCER_BARRIER, 72b3edf446SDimitry Andric 730fca6ea1SDimitry Andric VG_SAVE, 740fca6ea1SDimitry Andric VG_RESTORE, 750fca6ea1SDimitry Andric 76bdd1243dSDimitry Andric SMSTART, 77bdd1243dSDimitry Andric SMSTOP, 78bdd1243dSDimitry Andric RESTORE_ZA, 797a6dacacSDimitry Andric RESTORE_ZT, 807a6dacacSDimitry Andric SAVE_ZT, 817a6dacacSDimitry Andric 827a6dacacSDimitry Andric // A call with the callee in x16, i.e. "blr x16". 837a6dacacSDimitry Andric CALL_ARM64EC_TO_X64, 84bdd1243dSDimitry Andric 850b57cec5SDimitry Andric // Produces the full sequence of instructions for getting the thread pointer 860b57cec5SDimitry Andric // offset of a variable into X0, using the TLSDesc model. 870b57cec5SDimitry Andric TLSDESC_CALLSEQ, 880b57cec5SDimitry Andric ADRP, // Page address of a TargetGlobalAddress operand. 890b57cec5SDimitry Andric ADR, // ADR 900b57cec5SDimitry Andric ADDlow, // Add the low 12 bits of a TargetGlobalAddress operand. 910b57cec5SDimitry Andric LOADgot, // Load from automatically generated descriptor (e.g. Global 920b57cec5SDimitry Andric // Offset Table, TLS record). 9306c3fb27SDimitry Andric RET_GLUE, // Return with a glue operand. Operand 0 is the chain operand. 940b57cec5SDimitry Andric BRCOND, // Conditional branch instruction; "b.cond". 950b57cec5SDimitry Andric CSEL, 960b57cec5SDimitry Andric CSINV, // Conditional select invert. 970b57cec5SDimitry Andric CSNEG, // Conditional select negate. 980b57cec5SDimitry Andric CSINC, // Conditional select increment. 990b57cec5SDimitry Andric 1000b57cec5SDimitry Andric // Pointer to the thread's local storage area. Materialised from TPIDR_EL0 on 1010b57cec5SDimitry Andric // ELF. 1020b57cec5SDimitry Andric THREAD_POINTER, 1030b57cec5SDimitry Andric ADC, 1040b57cec5SDimitry Andric SBC, // adc, sbc instructions 1050b57cec5SDimitry Andric 1065f757f3fSDimitry Andric // To avoid stack clash, allocation is performed by block and each block is 1075f757f3fSDimitry Andric // probed. 1085f757f3fSDimitry Andric PROBED_ALLOCA, 1095f757f3fSDimitry Andric 110e8d8bef9SDimitry Andric // Predicated instructions where inactive lanes produce undefined results. 11104eeddc0SDimitry Andric ABDS_PRED, 11204eeddc0SDimitry Andric ABDU_PRED, 1135ffd83dbSDimitry Andric FADD_PRED, 114e8d8bef9SDimitry Andric FDIV_PRED, 1155ffd83dbSDimitry Andric FMA_PRED, 116fe6060f1SDimitry Andric FMAX_PRED, 11704eeddc0SDimitry Andric FMAXNM_PRED, 118fe6060f1SDimitry Andric FMIN_PRED, 11904eeddc0SDimitry Andric FMINNM_PRED, 120e8d8bef9SDimitry Andric FMUL_PRED, 121e8d8bef9SDimitry Andric FSUB_PRED, 122bdd1243dSDimitry Andric HADDS_PRED, 123bdd1243dSDimitry Andric HADDU_PRED, 124e8d8bef9SDimitry Andric MUL_PRED, 125fe6060f1SDimitry Andric MULHS_PRED, 126fe6060f1SDimitry Andric MULHU_PRED, 127bdd1243dSDimitry Andric RHADDS_PRED, 128bdd1243dSDimitry Andric RHADDU_PRED, 129e8d8bef9SDimitry Andric SDIV_PRED, 130e8d8bef9SDimitry Andric SHL_PRED, 131e8d8bef9SDimitry Andric SMAX_PRED, 132e8d8bef9SDimitry Andric SMIN_PRED, 133e8d8bef9SDimitry Andric SRA_PRED, 134e8d8bef9SDimitry Andric SRL_PRED, 135e8d8bef9SDimitry Andric UDIV_PRED, 136e8d8bef9SDimitry Andric UMAX_PRED, 137e8d8bef9SDimitry Andric UMIN_PRED, 138e8d8bef9SDimitry Andric 139fe6060f1SDimitry Andric // Unpredicated vector instructions 140fe6060f1SDimitry Andric BIC, 141fe6060f1SDimitry Andric 1424824e7fdSDimitry Andric SRAD_MERGE_OP1, 1434824e7fdSDimitry Andric 144e8d8bef9SDimitry Andric // Predicated instructions with the result of inactive lanes provided by the 145e8d8bef9SDimitry Andric // last operand. 146e8d8bef9SDimitry Andric FABS_MERGE_PASSTHRU, 147e8d8bef9SDimitry Andric FCEIL_MERGE_PASSTHRU, 148e8d8bef9SDimitry Andric FFLOOR_MERGE_PASSTHRU, 149e8d8bef9SDimitry Andric FNEARBYINT_MERGE_PASSTHRU, 150e8d8bef9SDimitry Andric FNEG_MERGE_PASSTHRU, 151e8d8bef9SDimitry Andric FRECPX_MERGE_PASSTHRU, 152e8d8bef9SDimitry Andric FRINT_MERGE_PASSTHRU, 153e8d8bef9SDimitry Andric FROUND_MERGE_PASSTHRU, 154e8d8bef9SDimitry Andric FROUNDEVEN_MERGE_PASSTHRU, 155e8d8bef9SDimitry Andric FSQRT_MERGE_PASSTHRU, 156e8d8bef9SDimitry Andric FTRUNC_MERGE_PASSTHRU, 157e8d8bef9SDimitry Andric FP_ROUND_MERGE_PASSTHRU, 158e8d8bef9SDimitry Andric FP_EXTEND_MERGE_PASSTHRU, 159e8d8bef9SDimitry Andric UINT_TO_FP_MERGE_PASSTHRU, 160e8d8bef9SDimitry Andric SINT_TO_FP_MERGE_PASSTHRU, 161e8d8bef9SDimitry Andric FCVTZU_MERGE_PASSTHRU, 162e8d8bef9SDimitry Andric FCVTZS_MERGE_PASSTHRU, 163e8d8bef9SDimitry Andric SIGN_EXTEND_INREG_MERGE_PASSTHRU, 164e8d8bef9SDimitry Andric ZERO_EXTEND_INREG_MERGE_PASSTHRU, 165e8d8bef9SDimitry Andric ABS_MERGE_PASSTHRU, 166e8d8bef9SDimitry Andric NEG_MERGE_PASSTHRU, 1675ffd83dbSDimitry Andric 1685ffd83dbSDimitry Andric SETCC_MERGE_ZERO, 1695ffd83dbSDimitry Andric 1700b57cec5SDimitry Andric // Arithmetic instructions which write flags. 1710b57cec5SDimitry Andric ADDS, 1720b57cec5SDimitry Andric SUBS, 1730b57cec5SDimitry Andric ADCS, 1740b57cec5SDimitry Andric SBCS, 1750b57cec5SDimitry Andric ANDS, 1760b57cec5SDimitry Andric 1770b57cec5SDimitry Andric // Conditional compares. Operands: left,right,falsecc,cc,flags 1780b57cec5SDimitry Andric CCMP, 1790b57cec5SDimitry Andric CCMN, 1800b57cec5SDimitry Andric FCCMP, 1810b57cec5SDimitry Andric 1820b57cec5SDimitry Andric // Floating point comparison 1830b57cec5SDimitry Andric FCMP, 1840b57cec5SDimitry Andric 1850b57cec5SDimitry Andric // Scalar-to-vector duplication 1860b57cec5SDimitry Andric DUP, 1870b57cec5SDimitry Andric DUPLANE8, 1880b57cec5SDimitry Andric DUPLANE16, 1890b57cec5SDimitry Andric DUPLANE32, 1900b57cec5SDimitry Andric DUPLANE64, 19181ad6265SDimitry Andric DUPLANE128, 1920b57cec5SDimitry Andric 1930b57cec5SDimitry Andric // Vector immedate moves 1940b57cec5SDimitry Andric MOVI, 1950b57cec5SDimitry Andric MOVIshift, 1960b57cec5SDimitry Andric MOVIedit, 1970b57cec5SDimitry Andric MOVImsl, 1980b57cec5SDimitry Andric FMOV, 1990b57cec5SDimitry Andric MVNIshift, 2000b57cec5SDimitry Andric MVNImsl, 2010b57cec5SDimitry Andric 2020b57cec5SDimitry Andric // Vector immediate ops 2030b57cec5SDimitry Andric BICi, 2040b57cec5SDimitry Andric ORRi, 2050b57cec5SDimitry Andric 2065ffd83dbSDimitry Andric // Vector bitwise select: similar to ISD::VSELECT but not all bits within an 2070b57cec5SDimitry Andric // element must be identical. 2085ffd83dbSDimitry Andric BSP, 2090b57cec5SDimitry Andric 2100b57cec5SDimitry Andric // Vector shuffles 2110b57cec5SDimitry Andric ZIP1, 2120b57cec5SDimitry Andric ZIP2, 2130b57cec5SDimitry Andric UZP1, 2140b57cec5SDimitry Andric UZP2, 2150b57cec5SDimitry Andric TRN1, 2160b57cec5SDimitry Andric TRN2, 2170b57cec5SDimitry Andric REV16, 2180b57cec5SDimitry Andric REV32, 2190b57cec5SDimitry Andric REV64, 2200b57cec5SDimitry Andric EXT, 221fe6060f1SDimitry Andric SPLICE, 2220b57cec5SDimitry Andric 2230b57cec5SDimitry Andric // Vector shift by scalar 2240b57cec5SDimitry Andric VSHL, 2250b57cec5SDimitry Andric VLSHR, 2260b57cec5SDimitry Andric VASHR, 2270b57cec5SDimitry Andric 2280b57cec5SDimitry Andric // Vector shift by scalar (again) 2290b57cec5SDimitry Andric SQSHL_I, 2300b57cec5SDimitry Andric UQSHL_I, 2310b57cec5SDimitry Andric SQSHLU_I, 2320b57cec5SDimitry Andric SRSHR_I, 2330b57cec5SDimitry Andric URSHR_I, 2340fca6ea1SDimitry Andric URSHR_I_PRED, 2350b57cec5SDimitry Andric 2365f757f3fSDimitry Andric // Vector narrowing shift by immediate (bottom) 2375f757f3fSDimitry Andric RSHRNB_I, 2385f757f3fSDimitry Andric 2395ffd83dbSDimitry Andric // Vector shift by constant and insert 2405ffd83dbSDimitry Andric VSLI, 2415ffd83dbSDimitry Andric VSRI, 2425ffd83dbSDimitry Andric 2430b57cec5SDimitry Andric // Vector comparisons 2440b57cec5SDimitry Andric CMEQ, 2450b57cec5SDimitry Andric CMGE, 2460b57cec5SDimitry Andric CMGT, 2470b57cec5SDimitry Andric CMHI, 2480b57cec5SDimitry Andric CMHS, 2490b57cec5SDimitry Andric FCMEQ, 2500b57cec5SDimitry Andric FCMGE, 2510b57cec5SDimitry Andric FCMGT, 2520b57cec5SDimitry Andric 2530b57cec5SDimitry Andric // Vector zero comparisons 2540b57cec5SDimitry Andric CMEQz, 2550b57cec5SDimitry Andric CMGEz, 2560b57cec5SDimitry Andric CMGTz, 2570b57cec5SDimitry Andric CMLEz, 2580b57cec5SDimitry Andric CMLTz, 2590b57cec5SDimitry Andric FCMEQz, 2600b57cec5SDimitry Andric FCMGEz, 2610b57cec5SDimitry Andric FCMGTz, 2620b57cec5SDimitry Andric FCMLEz, 2630b57cec5SDimitry Andric FCMLTz, 2640b57cec5SDimitry Andric 2650fca6ea1SDimitry Andric // Round wide FP to narrow FP with inexact results to odd. 2660fca6ea1SDimitry Andric FCVTXN, 2670fca6ea1SDimitry Andric 2680b57cec5SDimitry Andric // Vector across-lanes addition 2690b57cec5SDimitry Andric // Only the lower result lane is defined. 2700b57cec5SDimitry Andric SADDV, 2710b57cec5SDimitry Andric UADDV, 2720b57cec5SDimitry Andric 2735f757f3fSDimitry Andric // Unsigned sum Long across Vector 2745f757f3fSDimitry Andric UADDLV, 2757a6dacacSDimitry Andric SADDLV, 2765f757f3fSDimitry Andric 27781ad6265SDimitry Andric // Add Pairwise of two vectors 27881ad6265SDimitry Andric ADDP, 27981ad6265SDimitry Andric // Add Long Pairwise 28081ad6265SDimitry Andric SADDLP, 281fe6060f1SDimitry Andric UADDLP, 282fe6060f1SDimitry Andric 283fe6060f1SDimitry Andric // udot/sdot instructions 284fe6060f1SDimitry Andric UDOT, 285fe6060f1SDimitry Andric SDOT, 286e8d8bef9SDimitry Andric 2870b57cec5SDimitry Andric // Vector across-lanes min/max 2880b57cec5SDimitry Andric // Only the lower result lane is defined. 2890b57cec5SDimitry Andric SMINV, 2900b57cec5SDimitry Andric UMINV, 2910b57cec5SDimitry Andric SMAXV, 2920b57cec5SDimitry Andric UMAXV, 2930b57cec5SDimitry Andric 294e8d8bef9SDimitry Andric SADDV_PRED, 295e8d8bef9SDimitry Andric UADDV_PRED, 296480093f4SDimitry Andric SMAXV_PRED, 297480093f4SDimitry Andric UMAXV_PRED, 298480093f4SDimitry Andric SMINV_PRED, 299480093f4SDimitry Andric UMINV_PRED, 300480093f4SDimitry Andric ORV_PRED, 301480093f4SDimitry Andric EORV_PRED, 302480093f4SDimitry Andric ANDV_PRED, 303480093f4SDimitry Andric 3040b57cec5SDimitry Andric // Compare-and-branch 3050b57cec5SDimitry Andric CBZ, 3060b57cec5SDimitry Andric CBNZ, 3070b57cec5SDimitry Andric TBZ, 3080b57cec5SDimitry Andric TBNZ, 3090b57cec5SDimitry Andric 3100b57cec5SDimitry Andric // Tail calls 3110b57cec5SDimitry Andric TC_RETURN, 3120b57cec5SDimitry Andric 3130b57cec5SDimitry Andric // Custom prefetch handling 3140b57cec5SDimitry Andric PREFETCH, 3150b57cec5SDimitry Andric 3160b57cec5SDimitry Andric // {s|u}int to FP within a FP register. 3170b57cec5SDimitry Andric SITOF, 3180b57cec5SDimitry Andric UITOF, 3190b57cec5SDimitry Andric 3200b57cec5SDimitry Andric /// Natural vector cast. ISD::BITCAST is not natural in the big-endian 3210b57cec5SDimitry Andric /// world w.r.t vectors; which causes additional REV instructions to be 3220b57cec5SDimitry Andric /// generated to compensate for the byte-swapping. But sometimes we do 3230b57cec5SDimitry Andric /// need to re-interpret the data in SIMD vector registers in big-endian 3240b57cec5SDimitry Andric /// mode without emitting such REV instructions. 3250b57cec5SDimitry Andric NVCAST, 3260b57cec5SDimitry Andric 327fe6060f1SDimitry Andric MRS, // MRS, also sets the flags via a glue. 328fe6060f1SDimitry Andric 3290b57cec5SDimitry Andric SMULL, 3300b57cec5SDimitry Andric UMULL, 3310b57cec5SDimitry Andric 332bdd1243dSDimitry Andric PMULL, 333bdd1243dSDimitry Andric 3340b57cec5SDimitry Andric // Reciprocal estimates and steps. 3355ffd83dbSDimitry Andric FRECPE, 3365ffd83dbSDimitry Andric FRECPS, 3375ffd83dbSDimitry Andric FRSQRTE, 3385ffd83dbSDimitry Andric FRSQRTS, 3390b57cec5SDimitry Andric 3408bcb0991SDimitry Andric SUNPKHI, 3418bcb0991SDimitry Andric SUNPKLO, 3428bcb0991SDimitry Andric UUNPKHI, 3438bcb0991SDimitry Andric UUNPKLO, 3448bcb0991SDimitry Andric 345480093f4SDimitry Andric CLASTA_N, 346480093f4SDimitry Andric CLASTB_N, 347480093f4SDimitry Andric LASTA, 348480093f4SDimitry Andric LASTB, 349480093f4SDimitry Andric TBL, 350480093f4SDimitry Andric 3515ffd83dbSDimitry Andric // Floating-point reductions. 3525ffd83dbSDimitry Andric FADDA_PRED, 3535ffd83dbSDimitry Andric FADDV_PRED, 3545ffd83dbSDimitry Andric FMAXV_PRED, 3555ffd83dbSDimitry Andric FMAXNMV_PRED, 3565ffd83dbSDimitry Andric FMINV_PRED, 3575ffd83dbSDimitry Andric FMINNMV_PRED, 3585ffd83dbSDimitry Andric 359480093f4SDimitry Andric INSR, 360480093f4SDimitry Andric PTEST, 361bdd1243dSDimitry Andric PTEST_ANY, 362480093f4SDimitry Andric PTRUE, 363480093f4SDimitry Andric 3645f757f3fSDimitry Andric CTTZ_ELTS, 3655f757f3fSDimitry Andric 366e8d8bef9SDimitry Andric BITREVERSE_MERGE_PASSTHRU, 367e8d8bef9SDimitry Andric BSWAP_MERGE_PASSTHRU, 3680eae32dcSDimitry Andric REVH_MERGE_PASSTHRU, 3690eae32dcSDimitry Andric REVW_MERGE_PASSTHRU, 370e8d8bef9SDimitry Andric CTLZ_MERGE_PASSTHRU, 371e8d8bef9SDimitry Andric CTPOP_MERGE_PASSTHRU, 3725ffd83dbSDimitry Andric DUP_MERGE_PASSTHRU, 3735ffd83dbSDimitry Andric INDEX_VECTOR, 3745ffd83dbSDimitry Andric 375e8d8bef9SDimitry Andric // Cast between vectors of the same element type but differ in length. 3765ffd83dbSDimitry Andric REINTERPRET_CAST, 3775ffd83dbSDimitry Andric 3786e75b2fbSDimitry Andric // Nodes to build an LD64B / ST64B 64-bit quantity out of i64, and vice versa 3796e75b2fbSDimitry Andric LS64_BUILD, 3806e75b2fbSDimitry Andric LS64_EXTRACT, 3816e75b2fbSDimitry Andric 3825ffd83dbSDimitry Andric LD1_MERGE_ZERO, 3835ffd83dbSDimitry Andric LD1S_MERGE_ZERO, 3845ffd83dbSDimitry Andric LDNF1_MERGE_ZERO, 3855ffd83dbSDimitry Andric LDNF1S_MERGE_ZERO, 3865ffd83dbSDimitry Andric LDFF1_MERGE_ZERO, 3875ffd83dbSDimitry Andric LDFF1S_MERGE_ZERO, 3885ffd83dbSDimitry Andric LD1RQ_MERGE_ZERO, 3895ffd83dbSDimitry Andric LD1RO_MERGE_ZERO, 3905ffd83dbSDimitry Andric 3915ffd83dbSDimitry Andric // Structured loads. 3925ffd83dbSDimitry Andric SVE_LD2_MERGE_ZERO, 3935ffd83dbSDimitry Andric SVE_LD3_MERGE_ZERO, 3945ffd83dbSDimitry Andric SVE_LD4_MERGE_ZERO, 3955ffd83dbSDimitry Andric 396480093f4SDimitry Andric // Unsigned gather loads. 3975ffd83dbSDimitry Andric GLD1_MERGE_ZERO, 3985ffd83dbSDimitry Andric GLD1_SCALED_MERGE_ZERO, 3995ffd83dbSDimitry Andric GLD1_UXTW_MERGE_ZERO, 4005ffd83dbSDimitry Andric GLD1_SXTW_MERGE_ZERO, 4015ffd83dbSDimitry Andric GLD1_UXTW_SCALED_MERGE_ZERO, 4025ffd83dbSDimitry Andric GLD1_SXTW_SCALED_MERGE_ZERO, 4035ffd83dbSDimitry Andric GLD1_IMM_MERGE_ZERO, 4045f757f3fSDimitry Andric GLD1Q_MERGE_ZERO, 4055f757f3fSDimitry Andric GLD1Q_INDEX_MERGE_ZERO, 406480093f4SDimitry Andric 407480093f4SDimitry Andric // Signed gather loads 4085ffd83dbSDimitry Andric GLD1S_MERGE_ZERO, 4095ffd83dbSDimitry Andric GLD1S_SCALED_MERGE_ZERO, 4105ffd83dbSDimitry Andric GLD1S_UXTW_MERGE_ZERO, 4115ffd83dbSDimitry Andric GLD1S_SXTW_MERGE_ZERO, 4125ffd83dbSDimitry Andric GLD1S_UXTW_SCALED_MERGE_ZERO, 4135ffd83dbSDimitry Andric GLD1S_SXTW_SCALED_MERGE_ZERO, 4145ffd83dbSDimitry Andric GLD1S_IMM_MERGE_ZERO, 4155ffd83dbSDimitry Andric 4165ffd83dbSDimitry Andric // Unsigned gather loads. 4175ffd83dbSDimitry Andric GLDFF1_MERGE_ZERO, 4185ffd83dbSDimitry Andric GLDFF1_SCALED_MERGE_ZERO, 4195ffd83dbSDimitry Andric GLDFF1_UXTW_MERGE_ZERO, 4205ffd83dbSDimitry Andric GLDFF1_SXTW_MERGE_ZERO, 4215ffd83dbSDimitry Andric GLDFF1_UXTW_SCALED_MERGE_ZERO, 4225ffd83dbSDimitry Andric GLDFF1_SXTW_SCALED_MERGE_ZERO, 4235ffd83dbSDimitry Andric GLDFF1_IMM_MERGE_ZERO, 4245ffd83dbSDimitry Andric 4255ffd83dbSDimitry Andric // Signed gather loads. 4265ffd83dbSDimitry Andric GLDFF1S_MERGE_ZERO, 4275ffd83dbSDimitry Andric GLDFF1S_SCALED_MERGE_ZERO, 4285ffd83dbSDimitry Andric GLDFF1S_UXTW_MERGE_ZERO, 4295ffd83dbSDimitry Andric GLDFF1S_SXTW_MERGE_ZERO, 4305ffd83dbSDimitry Andric GLDFF1S_UXTW_SCALED_MERGE_ZERO, 4315ffd83dbSDimitry Andric GLDFF1S_SXTW_SCALED_MERGE_ZERO, 4325ffd83dbSDimitry Andric GLDFF1S_IMM_MERGE_ZERO, 4335ffd83dbSDimitry Andric 4345ffd83dbSDimitry Andric // Non-temporal gather loads 4355ffd83dbSDimitry Andric GLDNT1_MERGE_ZERO, 4365ffd83dbSDimitry Andric GLDNT1_INDEX_MERGE_ZERO, 4375ffd83dbSDimitry Andric GLDNT1S_MERGE_ZERO, 4385ffd83dbSDimitry Andric 4395ffd83dbSDimitry Andric // Contiguous masked store. 4405ffd83dbSDimitry Andric ST1_PRED, 4415ffd83dbSDimitry Andric 442480093f4SDimitry Andric // Scatter store 4435ffd83dbSDimitry Andric SST1_PRED, 4445ffd83dbSDimitry Andric SST1_SCALED_PRED, 4455ffd83dbSDimitry Andric SST1_UXTW_PRED, 4465ffd83dbSDimitry Andric SST1_SXTW_PRED, 4475ffd83dbSDimitry Andric SST1_UXTW_SCALED_PRED, 4485ffd83dbSDimitry Andric SST1_SXTW_SCALED_PRED, 4495ffd83dbSDimitry Andric SST1_IMM_PRED, 4505f757f3fSDimitry Andric SST1Q_PRED, 4515f757f3fSDimitry Andric SST1Q_INDEX_PRED, 4525ffd83dbSDimitry Andric 4535ffd83dbSDimitry Andric // Non-temporal scatter store 4545ffd83dbSDimitry Andric SSTNT1_PRED, 4555ffd83dbSDimitry Andric SSTNT1_INDEX_PRED, 456480093f4SDimitry Andric 45781ad6265SDimitry Andric // SME 45881ad6265SDimitry Andric RDSVL, 45981ad6265SDimitry Andric REVD_MERGE_PASSTHRU, 4600fca6ea1SDimitry Andric ALLOCATE_ZA_BUFFER, 4610fca6ea1SDimitry Andric INIT_TPIDR2OBJ, 46281ad6265SDimitry Andric 463349cc55cSDimitry Andric // Asserts that a function argument (i32) is zero-extended to i8 by 464349cc55cSDimitry Andric // the caller 465349cc55cSDimitry Andric ASSERT_ZEXT_BOOL, 466349cc55cSDimitry Andric 467bdd1243dSDimitry Andric // 128-bit system register accesses 468bdd1243dSDimitry Andric // lo64, hi64, chain = MRRS(chain, sysregname) 469bdd1243dSDimitry Andric MRRS, 470bdd1243dSDimitry Andric // chain = MSRR(chain, sysregname, lo64, hi64) 471bdd1243dSDimitry Andric MSRR, 472bdd1243dSDimitry Andric 47347395794SDimitry Andric // Strict (exception-raising) floating point comparison 47447395794SDimitry Andric STRICT_FCMP = ISD::FIRST_TARGET_STRICTFP_OPCODE, 47547395794SDimitry Andric STRICT_FCMPE, 47647395794SDimitry Andric 4775f757f3fSDimitry Andric // SME ZA loads and stores 4785f757f3fSDimitry Andric SME_ZA_LDR, 4795f757f3fSDimitry Andric SME_ZA_STR, 4805f757f3fSDimitry Andric 4810b57cec5SDimitry Andric // NEON Load/Store with post-increment base updates 4820b57cec5SDimitry Andric LD2post = ISD::FIRST_TARGET_MEMORY_OPCODE, 4830b57cec5SDimitry Andric LD3post, 4840b57cec5SDimitry Andric LD4post, 4850b57cec5SDimitry Andric ST2post, 4860b57cec5SDimitry Andric ST3post, 4870b57cec5SDimitry Andric ST4post, 4880b57cec5SDimitry Andric LD1x2post, 4890b57cec5SDimitry Andric LD1x3post, 4900b57cec5SDimitry Andric LD1x4post, 4910b57cec5SDimitry Andric ST1x2post, 4920b57cec5SDimitry Andric ST1x3post, 4930b57cec5SDimitry Andric ST1x4post, 4940b57cec5SDimitry Andric LD1DUPpost, 4950b57cec5SDimitry Andric LD2DUPpost, 4960b57cec5SDimitry Andric LD3DUPpost, 4970b57cec5SDimitry Andric LD4DUPpost, 4980b57cec5SDimitry Andric LD1LANEpost, 4990b57cec5SDimitry Andric LD2LANEpost, 5000b57cec5SDimitry Andric LD3LANEpost, 5010b57cec5SDimitry Andric LD4LANEpost, 5020b57cec5SDimitry Andric ST2LANEpost, 5030b57cec5SDimitry Andric ST3LANEpost, 5040b57cec5SDimitry Andric ST4LANEpost, 5050b57cec5SDimitry Andric 5060b57cec5SDimitry Andric STG, 5070b57cec5SDimitry Andric STZG, 5080b57cec5SDimitry Andric ST2G, 509480093f4SDimitry Andric STZ2G, 5100b57cec5SDimitry Andric 511480093f4SDimitry Andric LDP, 51206c3fb27SDimitry Andric LDIAPP, 513bdd1243dSDimitry Andric LDNP, 5145ffd83dbSDimitry Andric STP, 51506c3fb27SDimitry Andric STILP, 516e8d8bef9SDimitry Andric STNP, 5171fd87a68SDimitry Andric 5181fd87a68SDimitry Andric // Memory Operations 5191fd87a68SDimitry Andric MOPS_MEMSET, 5201fd87a68SDimitry Andric MOPS_MEMSET_TAGGING, 5211fd87a68SDimitry Andric MOPS_MEMCOPY, 5221fd87a68SDimitry Andric MOPS_MEMMOVE, 5230b57cec5SDimitry Andric }; 5240b57cec5SDimitry Andric 5250b57cec5SDimitry Andric } // end namespace AArch64ISD 5260b57cec5SDimitry Andric 527fe6060f1SDimitry Andric namespace AArch64 { 528fe6060f1SDimitry Andric /// Possible values of current rounding mode, which is specified in bits 529fe6060f1SDimitry Andric /// 23:22 of FPCR. 530fe6060f1SDimitry Andric enum Rounding { 531fe6060f1SDimitry Andric RN = 0, // Round to Nearest 532fe6060f1SDimitry Andric RP = 1, // Round towards Plus infinity 533fe6060f1SDimitry Andric RM = 2, // Round towards Minus infinity 534fe6060f1SDimitry Andric RZ = 3, // Round towards Zero 535fe6060f1SDimitry Andric rmMask = 3 // Bit mask selecting rounding mode 536fe6060f1SDimitry Andric }; 537fe6060f1SDimitry Andric 538fe6060f1SDimitry Andric // Bit position of rounding mode bits in FPCR. 539fe6060f1SDimitry Andric const unsigned RoundingBitsPos = 22; 54006c3fb27SDimitry Andric 5410fca6ea1SDimitry Andric // Reserved bits should be preserved when modifying FPCR. 5420fca6ea1SDimitry Andric const uint64_t ReservedFPControlBits = 0xfffffffff80040f8; 5430fca6ea1SDimitry Andric 54406c3fb27SDimitry Andric // Registers used to pass function arguments. 5455f757f3fSDimitry Andric ArrayRef<MCPhysReg> getGPRArgRegs(); 5465f757f3fSDimitry Andric ArrayRef<MCPhysReg> getFPRArgRegs(); 5475f757f3fSDimitry Andric 5485f757f3fSDimitry Andric /// Maximum allowed number of unprobed bytes above SP at an ABI 5495f757f3fSDimitry Andric /// boundary. 5505f757f3fSDimitry Andric const unsigned StackProbeMaxUnprobedStack = 1024; 5515f757f3fSDimitry Andric 5525f757f3fSDimitry Andric /// Maximum number of iterations to unroll for a constant size probing loop. 5535f757f3fSDimitry Andric const unsigned StackProbeMaxLoopUnroll = 4; 55406c3fb27SDimitry Andric 555fe6060f1SDimitry Andric } // namespace AArch64 556fe6060f1SDimitry Andric 5570b57cec5SDimitry Andric class AArch64Subtarget; 5580b57cec5SDimitry Andric 5590b57cec5SDimitry Andric class AArch64TargetLowering : public TargetLowering { 5600b57cec5SDimitry Andric public: 5610b57cec5SDimitry Andric explicit AArch64TargetLowering(const TargetMachine &TM, 5620b57cec5SDimitry Andric const AArch64Subtarget &STI); 5630b57cec5SDimitry Andric 56481ad6265SDimitry Andric /// Control the following reassociation of operands: (op (op x, c1), y) -> (op 56581ad6265SDimitry Andric /// (op x, y), c1) where N0 is (op x, c1) and N1 is y. 56681ad6265SDimitry Andric bool isReassocProfitable(SelectionDAG &DAG, SDValue N0, 56781ad6265SDimitry Andric SDValue N1) const override; 56881ad6265SDimitry Andric 5690b57cec5SDimitry Andric /// Selects the correct CCAssignFn for a given CallingConvention value. 5700b57cec5SDimitry Andric CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const; 5710b57cec5SDimitry Andric 5720b57cec5SDimitry Andric /// Selects the correct CCAssignFn for a given CallingConvention value. 5730b57cec5SDimitry Andric CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC) const; 5740b57cec5SDimitry Andric 5750b57cec5SDimitry Andric /// Determine which of the bits specified in Mask are known to be either zero 5760b57cec5SDimitry Andric /// or one and return them in the KnownZero/KnownOne bitsets. 5770b57cec5SDimitry Andric void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, 5780b57cec5SDimitry Andric const APInt &DemandedElts, 5790b57cec5SDimitry Andric const SelectionDAG &DAG, 5800b57cec5SDimitry Andric unsigned Depth = 0) const override; 5810b57cec5SDimitry Andric 58206c3fb27SDimitry Andric unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 58306c3fb27SDimitry Andric const APInt &DemandedElts, 58406c3fb27SDimitry Andric const SelectionDAG &DAG, 58506c3fb27SDimitry Andric unsigned Depth) const override; 58606c3fb27SDimitry Andric 5878bcb0991SDimitry Andric MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const override { 5888bcb0991SDimitry Andric // Returning i64 unconditionally here (i.e. even for ILP32) means that the 5898bcb0991SDimitry Andric // *DAG* representation of pointers will always be 64-bits. They will be 5908bcb0991SDimitry Andric // truncated and extended when transferred to memory, but the 64-bit DAG 5918bcb0991SDimitry Andric // allows us to use AArch64's addressing modes much more easily. 5928bcb0991SDimitry Andric return MVT::getIntegerVT(64); 5938bcb0991SDimitry Andric } 5948bcb0991SDimitry Andric 5955ffd83dbSDimitry Andric bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, 5965ffd83dbSDimitry Andric const APInt &DemandedElts, 5970b57cec5SDimitry Andric TargetLoweringOpt &TLO) const override; 5980b57cec5SDimitry Andric 5990b57cec5SDimitry Andric MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override; 6000b57cec5SDimitry Andric 6010b57cec5SDimitry Andric /// Returns true if the target allows unaligned memory accesses of the 6020b57cec5SDimitry Andric /// specified type. 6030b57cec5SDimitry Andric bool allowsMisalignedMemoryAccesses( 604fe6060f1SDimitry Andric EVT VT, unsigned AddrSpace = 0, Align Alignment = Align(1), 6050b57cec5SDimitry Andric MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 606bdd1243dSDimitry Andric unsigned *Fast = nullptr) const override; 6078bcb0991SDimitry Andric /// LLT variant. 6085ffd83dbSDimitry Andric bool allowsMisalignedMemoryAccesses(LLT Ty, unsigned AddrSpace, 6095ffd83dbSDimitry Andric Align Alignment, 6105ffd83dbSDimitry Andric MachineMemOperand::Flags Flags, 611bdd1243dSDimitry Andric unsigned *Fast = nullptr) const override; 6120b57cec5SDimitry Andric 6130b57cec5SDimitry Andric /// Provide custom lowering hooks for some operations. 6140b57cec5SDimitry Andric SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 6150b57cec5SDimitry Andric 6160b57cec5SDimitry Andric const char *getTargetNodeName(unsigned Opcode) const override; 6170b57cec5SDimitry Andric 6180b57cec5SDimitry Andric SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 6190b57cec5SDimitry Andric 6200b57cec5SDimitry Andric /// This method returns a target specific FastISel object, or null if the 6210b57cec5SDimitry Andric /// target does not support "fast" ISel. 6220b57cec5SDimitry Andric FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 6230b57cec5SDimitry Andric const TargetLibraryInfo *libInfo) const override; 6240b57cec5SDimitry Andric 6250b57cec5SDimitry Andric bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 6260b57cec5SDimitry Andric 6270b57cec5SDimitry Andric bool isFPImmLegal(const APFloat &Imm, EVT VT, 6280b57cec5SDimitry Andric bool ForCodeSize) const override; 6290b57cec5SDimitry Andric 6300b57cec5SDimitry Andric /// Return true if the given shuffle mask can be codegen'd directly, or if it 6310b57cec5SDimitry Andric /// should be stack expanded. 6320b57cec5SDimitry Andric bool isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override; 6330b57cec5SDimitry Andric 634fcaf7f86SDimitry Andric /// Similar to isShuffleMaskLegal. Return true is the given 'select with zero' 635fcaf7f86SDimitry Andric /// shuffle mask can be codegen'd directly. 636fcaf7f86SDimitry Andric bool isVectorClearMaskLegal(ArrayRef<int> M, EVT VT) const override; 637fcaf7f86SDimitry Andric 6380b57cec5SDimitry Andric /// Return the ISD::SETCC ValueType. 6390b57cec5SDimitry Andric EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 6400b57cec5SDimitry Andric EVT VT) const override; 6410b57cec5SDimitry Andric 6420b57cec5SDimitry Andric SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const; 6430b57cec5SDimitry Andric 6440b57cec5SDimitry Andric MachineBasicBlock *EmitF128CSEL(MachineInstr &MI, 6450b57cec5SDimitry Andric MachineBasicBlock *BB) const; 6460b57cec5SDimitry Andric 6470b57cec5SDimitry Andric MachineBasicBlock *EmitLoweredCatchRet(MachineInstr &MI, 6480b57cec5SDimitry Andric MachineBasicBlock *BB) const; 6490b57cec5SDimitry Andric 6505f757f3fSDimitry Andric MachineBasicBlock *EmitDynamicProbedAlloc(MachineInstr &MI, 6515f757f3fSDimitry Andric MachineBasicBlock *MBB) const; 6525f757f3fSDimitry Andric 65381ad6265SDimitry Andric MachineBasicBlock *EmitTileLoad(unsigned Opc, unsigned BaseReg, 65481ad6265SDimitry Andric MachineInstr &MI, 65581ad6265SDimitry Andric MachineBasicBlock *BB) const; 65681ad6265SDimitry Andric MachineBasicBlock *EmitFill(MachineInstr &MI, MachineBasicBlock *BB) const; 657bdd1243dSDimitry Andric MachineBasicBlock *EmitZAInstr(unsigned Opc, unsigned BaseReg, 6580fca6ea1SDimitry Andric MachineInstr &MI, MachineBasicBlock *BB) const; 6595f757f3fSDimitry Andric MachineBasicBlock *EmitZTInstr(MachineInstr &MI, MachineBasicBlock *BB, 6605f757f3fSDimitry Andric unsigned Opcode, bool Op0IsDef) const; 66181ad6265SDimitry Andric MachineBasicBlock *EmitZero(MachineInstr &MI, MachineBasicBlock *BB) const; 6620fca6ea1SDimitry Andric MachineBasicBlock *EmitInitTPIDR2Object(MachineInstr &MI, 6630fca6ea1SDimitry Andric MachineBasicBlock *BB) const; 6640fca6ea1SDimitry Andric MachineBasicBlock *EmitAllocateZABuffer(MachineInstr &MI, 6650fca6ea1SDimitry Andric MachineBasicBlock *BB) const; 66681ad6265SDimitry Andric 6670b57cec5SDimitry Andric MachineBasicBlock * 6680b57cec5SDimitry Andric EmitInstrWithCustomInserter(MachineInstr &MI, 6690b57cec5SDimitry Andric MachineBasicBlock *MBB) const override; 6700b57cec5SDimitry Andric 6710b57cec5SDimitry Andric bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, 6720b57cec5SDimitry Andric MachineFunction &MF, 6730b57cec5SDimitry Andric unsigned Intrinsic) const override; 6740b57cec5SDimitry Andric 6750b57cec5SDimitry Andric bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, 6760b57cec5SDimitry Andric EVT NewVT) const override; 6770b57cec5SDimitry Andric 67806c3fb27SDimitry Andric bool shouldRemoveRedundantExtend(SDValue Op) const override; 67906c3fb27SDimitry Andric 6800b57cec5SDimitry Andric bool isTruncateFree(Type *Ty1, Type *Ty2) const override; 6810b57cec5SDimitry Andric bool isTruncateFree(EVT VT1, EVT VT2) const override; 6820b57cec5SDimitry Andric 6830b57cec5SDimitry Andric bool isProfitableToHoist(Instruction *I) const override; 6840b57cec5SDimitry Andric 6850b57cec5SDimitry Andric bool isZExtFree(Type *Ty1, Type *Ty2) const override; 6860b57cec5SDimitry Andric bool isZExtFree(EVT VT1, EVT VT2) const override; 6870b57cec5SDimitry Andric bool isZExtFree(SDValue Val, EVT VT2) const override; 6880b57cec5SDimitry Andric 6890b57cec5SDimitry Andric bool shouldSinkOperands(Instruction *I, 6900b57cec5SDimitry Andric SmallVectorImpl<Use *> &Ops) const override; 6910b57cec5SDimitry Andric 69206c3fb27SDimitry Andric bool optimizeExtendOrTruncateConversion( 69306c3fb27SDimitry Andric Instruction *I, Loop *L, const TargetTransformInfo &TTI) const override; 694bdd1243dSDimitry Andric 6955ffd83dbSDimitry Andric bool hasPairedLoad(EVT LoadedType, Align &RequiredAligment) const override; 6960b57cec5SDimitry Andric getMaxSupportedInterleaveFactor()6970b57cec5SDimitry Andric unsigned getMaxSupportedInterleaveFactor() const override { return 4; } 6980b57cec5SDimitry Andric 6990b57cec5SDimitry Andric bool lowerInterleavedLoad(LoadInst *LI, 7000b57cec5SDimitry Andric ArrayRef<ShuffleVectorInst *> Shuffles, 7010b57cec5SDimitry Andric ArrayRef<unsigned> Indices, 7020b57cec5SDimitry Andric unsigned Factor) const override; 7030b57cec5SDimitry Andric bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, 7040b57cec5SDimitry Andric unsigned Factor) const override; 7050b57cec5SDimitry Andric 70606c3fb27SDimitry Andric bool lowerDeinterleaveIntrinsicToLoad(IntrinsicInst *DI, 70706c3fb27SDimitry Andric LoadInst *LI) const override; 70806c3fb27SDimitry Andric 70906c3fb27SDimitry Andric bool lowerInterleaveIntrinsicToStore(IntrinsicInst *II, 71006c3fb27SDimitry Andric StoreInst *SI) const override; 71106c3fb27SDimitry Andric 7120b57cec5SDimitry Andric bool isLegalAddImmediate(int64_t) const override; 7130fca6ea1SDimitry Andric bool isLegalAddScalableImmediate(int64_t) const override; 7140b57cec5SDimitry Andric bool isLegalICmpImmediate(int64_t) const override; 7150b57cec5SDimitry Andric 71681ad6265SDimitry Andric bool isMulAddWithConstProfitable(SDValue AddNode, 71781ad6265SDimitry Andric SDValue ConstNode) const override; 718349cc55cSDimitry Andric 7190b57cec5SDimitry Andric bool shouldConsiderGEPOffsetSplit() const override; 7200b57cec5SDimitry Andric 7215ffd83dbSDimitry Andric EVT getOptimalMemOpType(const MemOp &Op, 7220b57cec5SDimitry Andric const AttributeList &FuncAttributes) const override; 7230b57cec5SDimitry Andric 7245ffd83dbSDimitry Andric LLT getOptimalMemOpLLT(const MemOp &Op, 7258bcb0991SDimitry Andric const AttributeList &FuncAttributes) const override; 7268bcb0991SDimitry Andric 7270b57cec5SDimitry Andric /// Return true if the addressing mode represented by AM is legal for this 7280b57cec5SDimitry Andric /// target, for a load/store of the specified type. 7290b57cec5SDimitry Andric bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, 7300b57cec5SDimitry Andric unsigned AS, 7310b57cec5SDimitry Andric Instruction *I = nullptr) const override; 7320b57cec5SDimitry Andric 7335f757f3fSDimitry Andric int64_t getPreferredLargeGEPBaseOffset(int64_t MinOffset, 7345f757f3fSDimitry Andric int64_t MaxOffset) const override; 7355f757f3fSDimitry Andric 7360b57cec5SDimitry Andric /// Return true if an FMA operation is faster than a pair of fmul and fadd 7370b57cec5SDimitry Andric /// instructions. fmuladd intrinsics will be expanded to FMAs when this method 7380b57cec5SDimitry Andric /// returns true, otherwise fmuladd is expanded to fmul + fadd. 739480093f4SDimitry Andric bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, 740480093f4SDimitry Andric EVT VT) const override; 741480093f4SDimitry Andric bool isFMAFasterThanFMulAndFAdd(const Function &F, Type *Ty) const override; 7420b57cec5SDimitry Andric 743fe6060f1SDimitry Andric bool generateFMAsInMachineCombiner(EVT VT, 7445f757f3fSDimitry Andric CodeGenOptLevel OptLevel) const override; 745fe6060f1SDimitry Andric 7460b57cec5SDimitry Andric const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override; 74706c3fb27SDimitry Andric ArrayRef<MCPhysReg> getRoundingControlRegisters() const override; 7480b57cec5SDimitry Andric 7490b57cec5SDimitry Andric /// Returns false if N is a bit extraction pattern of (X >> C) & Mask. 7500b57cec5SDimitry Andric bool isDesirableToCommuteWithShift(const SDNode *N, 7510b57cec5SDimitry Andric CombineLevel Level) const override; 7520b57cec5SDimitry Andric isDesirableToPullExtFromShl(const MachineInstr & MI)7535f757f3fSDimitry Andric bool isDesirableToPullExtFromShl(const MachineInstr &MI) const override { 7545f757f3fSDimitry Andric return false; 7555f757f3fSDimitry Andric } 7565f757f3fSDimitry Andric 757fcaf7f86SDimitry Andric /// Returns false if N is a bit extraction pattern of (X >> C) & Mask. 758fcaf7f86SDimitry Andric bool isDesirableToCommuteXorWithShift(const SDNode *N) const override; 759fcaf7f86SDimitry Andric 76081ad6265SDimitry Andric /// Return true if it is profitable to fold a pair of shifts into a mask. 76181ad6265SDimitry Andric bool shouldFoldConstantShiftPairToMask(const SDNode *N, 76281ad6265SDimitry Andric CombineLevel Level) const override; 76381ad6265SDimitry Andric 76406c3fb27SDimitry Andric bool shouldFoldSelectWithIdentityConstant(unsigned BinOpcode, 76506c3fb27SDimitry Andric EVT VT) const override; 76606c3fb27SDimitry Andric 7670b57cec5SDimitry Andric /// Returns true if it is beneficial to convert a load of a constant 7680b57cec5SDimitry Andric /// to just the constant itself. 7690b57cec5SDimitry Andric bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 7700b57cec5SDimitry Andric Type *Ty) const override; 7710b57cec5SDimitry Andric 7720b57cec5SDimitry Andric /// Return true if EXTRACT_SUBVECTOR is cheap for this result type 7730b57cec5SDimitry Andric /// with this index. 7740b57cec5SDimitry Andric bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, 7750b57cec5SDimitry Andric unsigned Index) const override; 7760b57cec5SDimitry Andric shouldFormOverflowOp(unsigned Opcode,EVT VT,bool MathUsed)7775ffd83dbSDimitry Andric bool shouldFormOverflowOp(unsigned Opcode, EVT VT, 7785ffd83dbSDimitry Andric bool MathUsed) const override { 7795ffd83dbSDimitry Andric // Using overflow ops for overflow checks only should beneficial on 7805ffd83dbSDimitry Andric // AArch64. 7815ffd83dbSDimitry Andric return TargetLowering::shouldFormOverflowOp(Opcode, VT, true); 7825ffd83dbSDimitry Andric } 7835ffd83dbSDimitry Andric 784fe6060f1SDimitry Andric Value *emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy, Value *Addr, 7850b57cec5SDimitry Andric AtomicOrdering Ord) const override; 786fe6060f1SDimitry Andric Value *emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr, 787fe6060f1SDimitry Andric AtomicOrdering Ord) const override; 7880b57cec5SDimitry Andric 789fe6060f1SDimitry Andric void emitAtomicCmpXchgNoStoreLLBalance(IRBuilderBase &Builder) const override; 7900b57cec5SDimitry Andric 791349cc55cSDimitry Andric bool isOpSuitableForLDPSTP(const Instruction *I) const; 79206c3fb27SDimitry Andric bool isOpSuitableForLSE128(const Instruction *I) const; 79306c3fb27SDimitry Andric bool isOpSuitableForRCPC3(const Instruction *I) const; 794349cc55cSDimitry Andric bool shouldInsertFencesForAtomic(const Instruction *I) const override; 795bdd1243dSDimitry Andric bool 796bdd1243dSDimitry Andric shouldInsertTrailingFenceForAtomicStore(const Instruction *I) const override; 797349cc55cSDimitry Andric 7980b57cec5SDimitry Andric TargetLoweringBase::AtomicExpansionKind 7990b57cec5SDimitry Andric shouldExpandAtomicLoadInIR(LoadInst *LI) const override; 80081ad6265SDimitry Andric TargetLoweringBase::AtomicExpansionKind 80181ad6265SDimitry Andric shouldExpandAtomicStoreInIR(StoreInst *SI) const override; 8020b57cec5SDimitry Andric TargetLoweringBase::AtomicExpansionKind 8030b57cec5SDimitry Andric shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override; 8040b57cec5SDimitry Andric 8050b57cec5SDimitry Andric TargetLoweringBase::AtomicExpansionKind 8060b57cec5SDimitry Andric shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override; 8070b57cec5SDimitry Andric 8080b57cec5SDimitry Andric bool useLoadStackGuardNode() const override; 8090b57cec5SDimitry Andric TargetLoweringBase::LegalizeTypeAction 8100b57cec5SDimitry Andric getPreferredVectorAction(MVT VT) const override; 8110b57cec5SDimitry Andric 8120b57cec5SDimitry Andric /// If the target has a standard location for the stack protector cookie, 8130b57cec5SDimitry Andric /// returns the address of that location. Otherwise, returns nullptr. 814fe6060f1SDimitry Andric Value *getIRStackGuard(IRBuilderBase &IRB) const override; 8150b57cec5SDimitry Andric 8160b57cec5SDimitry Andric void insertSSPDeclarations(Module &M) const override; 8170b57cec5SDimitry Andric Value *getSDagStackGuard(const Module &M) const override; 8180b57cec5SDimitry Andric Function *getSSPStackGuardCheck(const Module &M) const override; 8190b57cec5SDimitry Andric 8200b57cec5SDimitry Andric /// If the target has a standard location for the unsafe stack pointer, 8210b57cec5SDimitry Andric /// returns the address of that location. Otherwise, returns nullptr. 822fe6060f1SDimitry Andric Value *getSafeStackPointerLocation(IRBuilderBase &IRB) const override; 8230b57cec5SDimitry Andric 8240b57cec5SDimitry Andric /// If a physical register, this returns the register that receives the 8250b57cec5SDimitry Andric /// exception address on entry to an EH pad. 8265ffd83dbSDimitry Andric Register getExceptionPointerRegister(const Constant * PersonalityFn)8270b57cec5SDimitry Andric getExceptionPointerRegister(const Constant *PersonalityFn) const override { 8280b57cec5SDimitry Andric // FIXME: This is a guess. Has this been defined yet? 8290b57cec5SDimitry Andric return AArch64::X0; 8300b57cec5SDimitry Andric } 8310b57cec5SDimitry Andric 8320b57cec5SDimitry Andric /// If a physical register, this returns the register that receives the 8330b57cec5SDimitry Andric /// exception typeid on entry to a landing pad. 8345ffd83dbSDimitry Andric Register getExceptionSelectorRegister(const Constant * PersonalityFn)8350b57cec5SDimitry Andric getExceptionSelectorRegister(const Constant *PersonalityFn) const override { 8360b57cec5SDimitry Andric // FIXME: This is a guess. Has this been defined yet? 8370b57cec5SDimitry Andric return AArch64::X1; 8380b57cec5SDimitry Andric } 8390b57cec5SDimitry Andric 8400b57cec5SDimitry Andric bool isIntDivCheap(EVT VT, AttributeList Attr) const override; 8410b57cec5SDimitry Andric canMergeStoresTo(unsigned AddressSpace,EVT MemVT,const MachineFunction & MF)8420b57cec5SDimitry Andric bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT, 843349cc55cSDimitry Andric const MachineFunction &MF) const override { 8440b57cec5SDimitry Andric // Do not merge to float value size (128 bytes) if no implicit 8450b57cec5SDimitry Andric // float attribute is set. 8460b57cec5SDimitry Andric 847349cc55cSDimitry Andric bool NoFloat = MF.getFunction().hasFnAttribute(Attribute::NoImplicitFloat); 8480b57cec5SDimitry Andric 8490b57cec5SDimitry Andric if (NoFloat) 8500b57cec5SDimitry Andric return (MemVT.getSizeInBits() <= 64); 8510b57cec5SDimitry Andric return true; 8520b57cec5SDimitry Andric } 8530b57cec5SDimitry Andric isCheapToSpeculateCttz(Type *)854bdd1243dSDimitry Andric bool isCheapToSpeculateCttz(Type *) const override { 8550b57cec5SDimitry Andric return true; 8560b57cec5SDimitry Andric } 8570b57cec5SDimitry Andric isCheapToSpeculateCtlz(Type *)858bdd1243dSDimitry Andric bool isCheapToSpeculateCtlz(Type *) const override { 8590b57cec5SDimitry Andric return true; 8600b57cec5SDimitry Andric } 8610b57cec5SDimitry Andric 8620b57cec5SDimitry Andric bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override; 8630b57cec5SDimitry Andric hasAndNotCompare(SDValue V)8640b57cec5SDimitry Andric bool hasAndNotCompare(SDValue V) const override { 8650b57cec5SDimitry Andric // We can use bics for any scalar. 8660b57cec5SDimitry Andric return V.getValueType().isScalarInteger(); 8670b57cec5SDimitry Andric } 8680b57cec5SDimitry Andric hasAndNot(SDValue Y)8690b57cec5SDimitry Andric bool hasAndNot(SDValue Y) const override { 8700b57cec5SDimitry Andric EVT VT = Y.getValueType(); 8710b57cec5SDimitry Andric 8720b57cec5SDimitry Andric if (!VT.isVector()) 8730b57cec5SDimitry Andric return hasAndNotCompare(Y); 8740b57cec5SDimitry Andric 875349cc55cSDimitry Andric TypeSize TS = VT.getSizeInBits(); 876349cc55cSDimitry Andric // TODO: We should be able to use bic/bif too for SVE. 877349cc55cSDimitry Andric return !TS.isScalable() && TS.getFixedValue() >= 64; // vector 'bic' 8780b57cec5SDimitry Andric } 8790b57cec5SDimitry Andric 8808bcb0991SDimitry Andric bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd( 8818bcb0991SDimitry Andric SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y, 8828bcb0991SDimitry Andric unsigned OldShiftOpcode, unsigned NewShiftOpcode, 8838bcb0991SDimitry Andric SelectionDAG &DAG) const override; 8848bcb0991SDimitry Andric 885bdd1243dSDimitry Andric ShiftLegalizationStrategy 886bdd1243dSDimitry Andric preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N, 887bdd1243dSDimitry Andric unsigned ExpansionFactor) const override; 8880b57cec5SDimitry Andric shouldTransformSignedTruncationCheck(EVT XVT,unsigned KeptBits)8890b57cec5SDimitry Andric bool shouldTransformSignedTruncationCheck(EVT XVT, 8900b57cec5SDimitry Andric unsigned KeptBits) const override { 8910b57cec5SDimitry Andric // For vectors, we don't have a preference.. 8920b57cec5SDimitry Andric if (XVT.isVector()) 8930b57cec5SDimitry Andric return false; 8940b57cec5SDimitry Andric 8950b57cec5SDimitry Andric auto VTIsOk = [](EVT VT) -> bool { 8960b57cec5SDimitry Andric return VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 || 8970b57cec5SDimitry Andric VT == MVT::i64; 8980b57cec5SDimitry Andric }; 8990b57cec5SDimitry Andric 9000b57cec5SDimitry Andric // We are ok with KeptBitsVT being byte/word/dword, what SXT supports. 9010b57cec5SDimitry Andric // XVT will be larger than KeptBitsVT. 9020b57cec5SDimitry Andric MVT KeptBitsVT = MVT::getIntegerVT(KeptBits); 9030b57cec5SDimitry Andric return VTIsOk(XVT) && VTIsOk(KeptBitsVT); 9040b57cec5SDimitry Andric } 9050b57cec5SDimitry Andric 9060b57cec5SDimitry Andric bool preferIncOfAddToSubOfNot(EVT VT) const override; 9070b57cec5SDimitry Andric 9084824e7fdSDimitry Andric bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override; 9094824e7fdSDimitry Andric shouldExpandCmpUsingSelects()9100fca6ea1SDimitry Andric bool shouldExpandCmpUsingSelects() const override { return true; } 9110fca6ea1SDimitry Andric 912bdd1243dSDimitry Andric bool isComplexDeinterleavingSupported() const override; 913bdd1243dSDimitry Andric bool isComplexDeinterleavingOperationSupported( 914bdd1243dSDimitry Andric ComplexDeinterleavingOperation Operation, Type *Ty) const override; 915bdd1243dSDimitry Andric 916bdd1243dSDimitry Andric Value *createComplexDeinterleavingIR( 91706c3fb27SDimitry Andric IRBuilderBase &B, ComplexDeinterleavingOperation OperationType, 918bdd1243dSDimitry Andric ComplexDeinterleavingRotation Rotation, Value *InputA, Value *InputB, 919bdd1243dSDimitry Andric Value *Accumulator = nullptr) const override; 920bdd1243dSDimitry Andric supportSplitCSR(MachineFunction * MF)9210b57cec5SDimitry Andric bool supportSplitCSR(MachineFunction *MF) const override { 9220b57cec5SDimitry Andric return MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS && 9230b57cec5SDimitry Andric MF->getFunction().hasFnAttribute(Attribute::NoUnwind); 9240b57cec5SDimitry Andric } 9250b57cec5SDimitry Andric void initializeSplitCSR(MachineBasicBlock *Entry) const override; 9260b57cec5SDimitry Andric void insertCopiesSplitCSR( 9270b57cec5SDimitry Andric MachineBasicBlock *Entry, 9280b57cec5SDimitry Andric const SmallVectorImpl<MachineBasicBlock *> &Exits) const override; 9290b57cec5SDimitry Andric supportSwiftError()9300b57cec5SDimitry Andric bool supportSwiftError() const override { 9310b57cec5SDimitry Andric return true; 9320b57cec5SDimitry Andric } 9330b57cec5SDimitry Andric supportPtrAuthBundles()9340fca6ea1SDimitry Andric bool supportPtrAuthBundles() const override { return true; } 9350fca6ea1SDimitry Andric supportKCFIBundles()936bdd1243dSDimitry Andric bool supportKCFIBundles() const override { return true; } 937bdd1243dSDimitry Andric 93806c3fb27SDimitry Andric MachineInstr *EmitKCFICheck(MachineBasicBlock &MBB, 93906c3fb27SDimitry Andric MachineBasicBlock::instr_iterator &MBBI, 94006c3fb27SDimitry Andric const TargetInstrInfo *TII) const override; 94106c3fb27SDimitry Andric 9420b57cec5SDimitry Andric /// Enable aggressive FMA fusion on targets that want it. 9430b57cec5SDimitry Andric bool enableAggressiveFMAFusion(EVT VT) const override; 9440b57cec5SDimitry Andric 9450b57cec5SDimitry Andric /// Returns the size of the platform's va_list object. 9460b57cec5SDimitry Andric unsigned getVaListSizeInBits(const DataLayout &DL) const override; 9470b57cec5SDimitry Andric 9480b57cec5SDimitry Andric /// Returns true if \p VecTy is a legal interleaved access type. This 9490b57cec5SDimitry Andric /// function checks the vector element type and the overall width of the 9500b57cec5SDimitry Andric /// vector. 951349cc55cSDimitry Andric bool isLegalInterleavedAccessType(VectorType *VecTy, const DataLayout &DL, 952349cc55cSDimitry Andric bool &UseScalable) const; 9530b57cec5SDimitry Andric 9540b57cec5SDimitry Andric /// Returns the number of interleaved accesses that will be generated when 9550b57cec5SDimitry Andric /// lowering accesses of the given type. 956349cc55cSDimitry Andric unsigned getNumInterleavedAccesses(VectorType *VecTy, const DataLayout &DL, 957349cc55cSDimitry Andric bool UseScalable) const; 9580b57cec5SDimitry Andric 9595ffd83dbSDimitry Andric MachineMemOperand::Flags getTargetMMOFlags( 9605ffd83dbSDimitry Andric const Instruction &I) const override; 9610b57cec5SDimitry Andric 962fe6060f1SDimitry Andric bool functionArgumentNeedsConsecutiveRegisters( 963fe6060f1SDimitry Andric Type *Ty, CallingConv::ID CallConv, bool isVarArg, 964fe6060f1SDimitry Andric const DataLayout &DL) const override; 965fe6060f1SDimitry Andric 9660b57cec5SDimitry Andric /// Used for exception handling on Win64. 9670b57cec5SDimitry Andric bool needsFixedCatchObjects() const override; 9685ffd83dbSDimitry Andric 9695ffd83dbSDimitry Andric bool fallBackToDAGISel(const Instruction &Inst) const override; 9705ffd83dbSDimitry Andric 9715ffd83dbSDimitry Andric /// SVE code generation for fixed length vectors does not custom lower 9725ffd83dbSDimitry Andric /// BUILD_VECTOR. This makes BUILD_VECTOR legalisation a source of stores to 9735ffd83dbSDimitry Andric /// merge. However, merging them creates a BUILD_VECTOR that is just as 9745ffd83dbSDimitry Andric /// illegal as the original, thus leading to an infinite legalisation loop. 9755ffd83dbSDimitry Andric /// NOTE: Once BUILD_VECTOR is legal or can be custom lowered for all legal 9765ffd83dbSDimitry Andric /// vector types this override can be removed. 977e8d8bef9SDimitry Andric bool mergeStoresAfterLegalization(EVT VT) const override; 9785ffd83dbSDimitry Andric 979fe6060f1SDimitry Andric // If the platform/function should have a redzone, return the size in bytes. getRedZoneSize(const Function & F)980fe6060f1SDimitry Andric unsigned getRedZoneSize(const Function &F) const { 981fe6060f1SDimitry Andric if (F.hasFnAttribute(Attribute::NoRedZone)) 982fe6060f1SDimitry Andric return 0; 983fe6060f1SDimitry Andric return 128; 984fe6060f1SDimitry Andric } 985fe6060f1SDimitry Andric 98604eeddc0SDimitry Andric bool isAllActivePredicate(SelectionDAG &DAG, SDValue N) const; 987fe6060f1SDimitry Andric EVT getPromotedVTForPredicate(EVT VT) const; 988fe6060f1SDimitry Andric 9896e75b2fbSDimitry Andric EVT getAsmOperandValueType(const DataLayout &DL, Type *Ty, 9906e75b2fbSDimitry Andric bool AllowUnknown = false) const override; 9916e75b2fbSDimitry Andric 9924824e7fdSDimitry Andric bool shouldExpandGetActiveLaneMask(EVT VT, EVT OpVT) const override; 9934824e7fdSDimitry Andric 9945f757f3fSDimitry Andric bool shouldExpandCttzElements(EVT VT) const override; 9955f757f3fSDimitry Andric 996bdd1243dSDimitry Andric /// If a change in streaming mode is required on entry to/return from a 9970fca6ea1SDimitry Andric /// function call it emits and returns the corresponding SMSTART or SMSTOP 9980fca6ea1SDimitry Andric /// node. \p Condition should be one of the enum values from 9990fca6ea1SDimitry Andric /// AArch64SME::ToggleCondition. 1000bdd1243dSDimitry Andric SDValue changeStreamingMode(SelectionDAG &DAG, SDLoc DL, bool Enable, 10010fca6ea1SDimitry Andric SDValue Chain, SDValue InGlue, unsigned Condition, 10020fca6ea1SDimitry Andric SDValue PStateSM = SDValue()) const; 1003bdd1243dSDimitry Andric isVScaleKnownToBeAPowerOfTwo()100406c3fb27SDimitry Andric bool isVScaleKnownToBeAPowerOfTwo() const override { return true; } 1005bdd1243dSDimitry Andric 1006bdd1243dSDimitry Andric // Normally SVE is only used for byte size vectors that do not fit within a 1007bdd1243dSDimitry Andric // NEON vector. This changes when OverrideNEON is true, allowing SVE to be 1008bdd1243dSDimitry Andric // used for 64bit and 128bit vectors as well. 1009bdd1243dSDimitry Andric bool useSVEForFixedLengthVectorVT(EVT VT, bool OverrideNEON = false) const; 1010bdd1243dSDimitry Andric 10115f757f3fSDimitry Andric // Follow NEON ABI rules even when using SVE for fixed length vectors. 10125f757f3fSDimitry Andric MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, 10135f757f3fSDimitry Andric EVT VT) const override; 10145f757f3fSDimitry Andric unsigned getNumRegistersForCallingConv(LLVMContext &Context, 10155f757f3fSDimitry Andric CallingConv::ID CC, 10165f757f3fSDimitry Andric EVT VT) const override; 10175f757f3fSDimitry Andric unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, 10185f757f3fSDimitry Andric CallingConv::ID CC, EVT VT, 10195f757f3fSDimitry Andric EVT &IntermediateVT, 10205f757f3fSDimitry Andric unsigned &NumIntermediates, 10215f757f3fSDimitry Andric MVT &RegisterVT) const override; 10225f757f3fSDimitry Andric 10235f757f3fSDimitry Andric /// True if stack clash protection is enabled for this functions. 10245f757f3fSDimitry Andric bool hasInlineStackProbe(const MachineFunction &MF) const override; 10255f757f3fSDimitry Andric 10260fca6ea1SDimitry Andric #ifndef NDEBUG 10270fca6ea1SDimitry Andric void verifyTargetSDNode(const SDNode *N) const override; 10280fca6ea1SDimitry Andric #endif 10290fca6ea1SDimitry Andric 10300b57cec5SDimitry Andric private: 10310b57cec5SDimitry Andric /// Keep a pointer to the AArch64Subtarget around so that we can 10320b57cec5SDimitry Andric /// make the right decision when generating code for different targets. 10330b57cec5SDimitry Andric const AArch64Subtarget *Subtarget; 10340b57cec5SDimitry Andric 1035dfa39133SDimitry Andric llvm::BumpPtrAllocator BumpAlloc; 1036dfa39133SDimitry Andric llvm::StringSaver Saver{BumpAlloc}; 1037dfa39133SDimitry Andric 10380b57cec5SDimitry Andric bool isExtFreeImpl(const Instruction *Ext) const override; 10390b57cec5SDimitry Andric 1040fe6060f1SDimitry Andric void addTypeForNEON(MVT VT); 10410fca6ea1SDimitry Andric void addTypeForFixedLengthSVE(MVT VT); 10420fca6ea1SDimitry Andric void addDRType(MVT VT); 10430fca6ea1SDimitry Andric void addQRType(MVT VT); 10440b57cec5SDimitry Andric 10450fca6ea1SDimitry Andric bool shouldExpandBuildVectorWithShuffles(EVT, unsigned) const override; 1046bdd1243dSDimitry Andric 10470b57cec5SDimitry Andric SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, 10480b57cec5SDimitry Andric bool isVarArg, 10490b57cec5SDimitry Andric const SmallVectorImpl<ISD::InputArg> &Ins, 10500b57cec5SDimitry Andric const SDLoc &DL, SelectionDAG &DAG, 10510b57cec5SDimitry Andric SmallVectorImpl<SDValue> &InVals) const override; 10520b57cec5SDimitry Andric 10535f757f3fSDimitry Andric void AdjustInstrPostInstrSelection(MachineInstr &MI, 10545f757f3fSDimitry Andric SDNode *Node) const override; 10555f757f3fSDimitry Andric 10560b57cec5SDimitry Andric SDValue LowerCall(CallLoweringInfo & /*CLI*/, 10570b57cec5SDimitry Andric SmallVectorImpl<SDValue> &InVals) const override; 10580b57cec5SDimitry Andric 105906c3fb27SDimitry Andric SDValue LowerCallResult(SDValue Chain, SDValue InGlue, 10600b57cec5SDimitry Andric CallingConv::ID CallConv, bool isVarArg, 1061f3fd488fSDimitry Andric const SmallVectorImpl<CCValAssign> &RVLocs, 10620b57cec5SDimitry Andric const SDLoc &DL, SelectionDAG &DAG, 10630b57cec5SDimitry Andric SmallVectorImpl<SDValue> &InVals, bool isThisReturn, 1064b3edf446SDimitry Andric SDValue ThisVal, bool RequiresSMChange) const; 10650b57cec5SDimitry Andric 1066fe6060f1SDimitry Andric SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; 10670b57cec5SDimitry Andric SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 1068349cc55cSDimitry Andric SDValue LowerStore128(SDValue Op, SelectionDAG &DAG) const; 1069e8d8bef9SDimitry Andric SDValue LowerABS(SDValue Op, SelectionDAG &DAG) const; 1070e8d8bef9SDimitry Andric 1071e8d8bef9SDimitry Andric SDValue LowerMGATHER(SDValue Op, SelectionDAG &DAG) const; 1072e8d8bef9SDimitry Andric SDValue LowerMSCATTER(SDValue Op, SelectionDAG &DAG) const; 10730b57cec5SDimitry Andric 1074fe6060f1SDimitry Andric SDValue LowerMLOAD(SDValue Op, SelectionDAG &DAG) const; 1075fe6060f1SDimitry Andric 10761fd87a68SDimitry Andric SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; 10770b57cec5SDimitry Andric SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 1078bdd1243dSDimitry Andric SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const; 10790b57cec5SDimitry Andric 10803a9a9c0cSDimitry Andric bool 10813a9a9c0cSDimitry Andric isEligibleForTailCallOptimization(const CallLoweringInfo &CLI) const; 10820b57cec5SDimitry Andric 10830b57cec5SDimitry Andric /// Finds the incoming stack arguments which overlap the given fixed stack 10840b57cec5SDimitry Andric /// object and incorporates their load into the current chain. This prevents 10850b57cec5SDimitry Andric /// an upcoming store from clobbering the stack argument before it's used. 10860b57cec5SDimitry Andric SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG, 10870b57cec5SDimitry Andric MachineFrameInfo &MFI, int ClobberedFI) const; 10880b57cec5SDimitry Andric 10890b57cec5SDimitry Andric bool DoesCalleeRestoreStack(CallingConv::ID CallCC, bool TailCallOpt) const; 10900b57cec5SDimitry Andric 10910b57cec5SDimitry Andric void saveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &DL, 10920b57cec5SDimitry Andric SDValue &Chain) const; 10930b57cec5SDimitry Andric 10940b57cec5SDimitry Andric bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 10950b57cec5SDimitry Andric bool isVarArg, 10960b57cec5SDimitry Andric const SmallVectorImpl<ISD::OutputArg> &Outs, 10970b57cec5SDimitry Andric LLVMContext &Context) const override; 10980b57cec5SDimitry Andric 10990b57cec5SDimitry Andric SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 11000b57cec5SDimitry Andric const SmallVectorImpl<ISD::OutputArg> &Outs, 11010b57cec5SDimitry Andric const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, 11020b57cec5SDimitry Andric SelectionDAG &DAG) const override; 11030b57cec5SDimitry Andric 11040b57cec5SDimitry Andric SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG, 11050b57cec5SDimitry Andric unsigned Flag) const; 11060b57cec5SDimitry Andric SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG, 11070b57cec5SDimitry Andric unsigned Flag) const; 11080b57cec5SDimitry Andric SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG, 11090b57cec5SDimitry Andric unsigned Flag) const; 11100b57cec5SDimitry Andric SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG, 11110b57cec5SDimitry Andric unsigned Flag) const; 11127a6dacacSDimitry Andric SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG, 11137a6dacacSDimitry Andric unsigned Flag) const; 11140b57cec5SDimitry Andric template <class NodeTy> 11150b57cec5SDimitry Andric SDValue getGOT(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const; 11160b57cec5SDimitry Andric template <class NodeTy> 11170b57cec5SDimitry Andric SDValue getAddrLarge(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const; 11180b57cec5SDimitry Andric template <class NodeTy> 11190b57cec5SDimitry Andric SDValue getAddr(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const; 11200b57cec5SDimitry Andric template <class NodeTy> 11210b57cec5SDimitry Andric SDValue getAddrTiny(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const; 11220b57cec5SDimitry Andric SDValue LowerADDROFRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 11230b57cec5SDimitry Andric SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 11240b57cec5SDimitry Andric SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 11250b57cec5SDimitry Andric SDValue LowerDarwinGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 11260b57cec5SDimitry Andric SDValue LowerELFGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 1127480093f4SDimitry Andric SDValue LowerELFTLSLocalExec(const GlobalValue *GV, SDValue ThreadBase, 1128480093f4SDimitry Andric const SDLoc &DL, SelectionDAG &DAG) const; 11290b57cec5SDimitry Andric SDValue LowerELFTLSDescCallSeq(SDValue SymAddr, const SDLoc &DL, 11300b57cec5SDimitry Andric SelectionDAG &DAG) const; 11310b57cec5SDimitry Andric SDValue LowerWindowsGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 11320fca6ea1SDimitry Andric SDValue LowerPtrAuthGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 11330fca6ea1SDimitry Andric SDValue LowerPtrAuthGlobalAddressStatically(SDValue TGA, SDLoc DL, EVT VT, 11340fca6ea1SDimitry Andric AArch64PACKey::ID Key, 11350fca6ea1SDimitry Andric SDValue Discriminator, 11360fca6ea1SDimitry Andric SDValue AddrDiscriminator, 11370fca6ea1SDimitry Andric SelectionDAG &DAG) const; 11380b57cec5SDimitry Andric SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; 1139bdd1243dSDimitry Andric SDValue LowerSETCCCARRY(SDValue Op, SelectionDAG &DAG) const; 11400b57cec5SDimitry Andric SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 11410b57cec5SDimitry Andric SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 11420b57cec5SDimitry Andric SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 11430b57cec5SDimitry Andric SDValue LowerSELECT_CC(ISD::CondCode CC, SDValue LHS, SDValue RHS, 11440b57cec5SDimitry Andric SDValue TVal, SDValue FVal, const SDLoc &dl, 11450b57cec5SDimitry Andric SelectionDAG &DAG) const; 1146*36b606aeSDimitry Andric SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 1147*36b606aeSDimitry Andric SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 11480b57cec5SDimitry Andric SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 11490b57cec5SDimitry Andric SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const; 11500fca6ea1SDimitry Andric SDValue LowerBRIND(SDValue Op, SelectionDAG &DAG) const; 11510b57cec5SDimitry Andric SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 11520b57cec5SDimitry Andric SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 11530b57cec5SDimitry Andric SDValue LowerAAPCS_VASTART(SDValue Op, SelectionDAG &DAG) const; 11540b57cec5SDimitry Andric SDValue LowerDarwin_VASTART(SDValue Op, SelectionDAG &DAG) const; 11550b57cec5SDimitry Andric SDValue LowerWin64_VASTART(SDValue Op, SelectionDAG &DAG) const; 11560b57cec5SDimitry Andric SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; 11570b57cec5SDimitry Andric SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const; 11580b57cec5SDimitry Andric SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const; 11590b57cec5SDimitry Andric SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 11600b57cec5SDimitry Andric SDValue LowerSPONENTRY(SDValue Op, SelectionDAG &DAG) const; 11610b57cec5SDimitry Andric SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 1162bdd1243dSDimitry Andric SDValue LowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const; 1163fe6060f1SDimitry Andric SDValue LowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const; 11640fca6ea1SDimitry Andric SDValue LowerGET_FPMODE(SDValue Op, SelectionDAG &DAG) const; 11650fca6ea1SDimitry Andric SDValue LowerSET_FPMODE(SDValue Op, SelectionDAG &DAG) const; 11660fca6ea1SDimitry Andric SDValue LowerRESET_FPMODE(SDValue Op, SelectionDAG &DAG) const; 11670b57cec5SDimitry Andric SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 11680b57cec5SDimitry Andric SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 11690b57cec5SDimitry Andric SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 1170bdd1243dSDimitry Andric SDValue LowerZERO_EXTEND_VECTOR_INREG(SDValue Op, SelectionDAG &DAG) const; 11710b57cec5SDimitry Andric SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 11728bcb0991SDimitry Andric SDValue LowerSPLAT_VECTOR(SDValue Op, SelectionDAG &DAG) const; 11735ffd83dbSDimitry Andric SDValue LowerDUPQLane(SDValue Op, SelectionDAG &DAG) const; 117481ad6265SDimitry Andric SDValue LowerToPredicatedOp(SDValue Op, SelectionDAG &DAG, 117581ad6265SDimitry Andric unsigned NewOp) const; 1176e8d8bef9SDimitry Andric SDValue LowerToScalableOp(SDValue Op, SelectionDAG &DAG) const; 1177fe6060f1SDimitry Andric SDValue LowerVECTOR_SPLICE(SDValue Op, SelectionDAG &DAG) const; 11780b57cec5SDimitry Andric SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; 11795ffd83dbSDimitry Andric SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; 118006c3fb27SDimitry Andric SDValue LowerVECTOR_DEINTERLEAVE(SDValue Op, SelectionDAG &DAG) const; 118106c3fb27SDimitry Andric SDValue LowerVECTOR_INTERLEAVE(SDValue Op, SelectionDAG &DAG) const; 11820fca6ea1SDimitry Andric SDValue LowerVECTOR_HISTOGRAM(SDValue Op, SelectionDAG &DAG) const; 1183e8d8bef9SDimitry Andric SDValue LowerDIV(SDValue Op, SelectionDAG &DAG) const; 1184e8d8bef9SDimitry Andric SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const; 11850b57cec5SDimitry Andric SDValue LowerVectorSRA_SRL_SHL(SDValue Op, SelectionDAG &DAG) const; 1186fe6060f1SDimitry Andric SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) const; 11870b57cec5SDimitry Andric SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const; 1188fcaf7f86SDimitry Andric SDValue LowerCTPOP_PARITY(SDValue Op, SelectionDAG &DAG) const; 1189e8d8bef9SDimitry Andric SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) const; 1190fe6060f1SDimitry Andric SDValue LowerBitreverse(SDValue Op, SelectionDAG &DAG) const; 1191349cc55cSDimitry Andric SDValue LowerMinMax(SDValue Op, SelectionDAG &DAG) const; 11920b57cec5SDimitry Andric SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; 11930b57cec5SDimitry Andric SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const; 11940b57cec5SDimitry Andric SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const; 11950b57cec5SDimitry Andric SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) const; 1196349cc55cSDimitry Andric SDValue LowerVectorFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const; 11970b57cec5SDimitry Andric SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const; 1198fe6060f1SDimitry Andric SDValue LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const; 11990fca6ea1SDimitry Andric SDValue LowerVectorXRINT(SDValue Op, SelectionDAG &DAG) const; 12000b57cec5SDimitry Andric SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 1201e8d8bef9SDimitry Andric SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 12020b57cec5SDimitry Andric SDValue LowerVectorOR(SDValue Op, SelectionDAG &DAG) const; 1203e8d8bef9SDimitry Andric SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) const; 12040b57cec5SDimitry Andric SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const; 12050b57cec5SDimitry Andric SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const; 1206fe6060f1SDimitry Andric SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const; 12075ffd83dbSDimitry Andric SDValue LowerVSCALE(SDValue Op, SelectionDAG &DAG) const; 12085ffd83dbSDimitry Andric SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const; 12090b57cec5SDimitry Andric SDValue LowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const; 12100b57cec5SDimitry Andric SDValue LowerATOMIC_LOAD_AND(SDValue Op, SelectionDAG &DAG) const; 12115f757f3fSDimitry Andric SDValue LowerWindowsDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 12125f757f3fSDimitry Andric SDValue LowerInlineDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 12130b57cec5SDimitry Andric SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 12145f757f3fSDimitry Andric 121506c3fb27SDimitry Andric SDValue LowerAVG(SDValue Op, SelectionDAG &DAG, unsigned NewOp) const; 12165ffd83dbSDimitry Andric 1217e8d8bef9SDimitry Andric SDValue LowerFixedLengthVectorIntDivideToSVE(SDValue Op, 1218e8d8bef9SDimitry Andric SelectionDAG &DAG) const; 1219e8d8bef9SDimitry Andric SDValue LowerFixedLengthVectorIntExtendToSVE(SDValue Op, 1220e8d8bef9SDimitry Andric SelectionDAG &DAG) const; 12215ffd83dbSDimitry Andric SDValue LowerFixedLengthVectorLoadToSVE(SDValue Op, SelectionDAG &DAG) const; 1222fe6060f1SDimitry Andric SDValue LowerFixedLengthVectorMLoadToSVE(SDValue Op, SelectionDAG &DAG) const; 1223e8d8bef9SDimitry Andric SDValue LowerVECREDUCE_SEQ_FADD(SDValue ScalarOp, SelectionDAG &DAG) const; 1224e8d8bef9SDimitry Andric SDValue LowerPredReductionToSVE(SDValue ScalarOp, SelectionDAG &DAG) const; 1225e8d8bef9SDimitry Andric SDValue LowerReductionToSVE(unsigned Opcode, SDValue ScalarOp, 1226e8d8bef9SDimitry Andric SelectionDAG &DAG) const; 1227e8d8bef9SDimitry Andric SDValue LowerFixedLengthVectorSelectToSVE(SDValue Op, SelectionDAG &DAG) const; 1228e8d8bef9SDimitry Andric SDValue LowerFixedLengthVectorSetccToSVE(SDValue Op, SelectionDAG &DAG) const; 12295ffd83dbSDimitry Andric SDValue LowerFixedLengthVectorStoreToSVE(SDValue Op, SelectionDAG &DAG) const; 1230fe6060f1SDimitry Andric SDValue LowerFixedLengthVectorMStoreToSVE(SDValue Op, 1231fe6060f1SDimitry Andric SelectionDAG &DAG) const; 12325ffd83dbSDimitry Andric SDValue LowerFixedLengthVectorTruncateToSVE(SDValue Op, 12335ffd83dbSDimitry Andric SelectionDAG &DAG) const; 1234fe6060f1SDimitry Andric SDValue LowerFixedLengthExtractVectorElt(SDValue Op, SelectionDAG &DAG) const; 1235fe6060f1SDimitry Andric SDValue LowerFixedLengthInsertVectorElt(SDValue Op, SelectionDAG &DAG) const; 1236fe6060f1SDimitry Andric SDValue LowerFixedLengthBitcastToSVE(SDValue Op, SelectionDAG &DAG) const; 1237fe6060f1SDimitry Andric SDValue LowerFixedLengthConcatVectorsToSVE(SDValue Op, 1238fe6060f1SDimitry Andric SelectionDAG &DAG) const; 1239fe6060f1SDimitry Andric SDValue LowerFixedLengthFPExtendToSVE(SDValue Op, SelectionDAG &DAG) const; 1240fe6060f1SDimitry Andric SDValue LowerFixedLengthFPRoundToSVE(SDValue Op, SelectionDAG &DAG) const; 1241fe6060f1SDimitry Andric SDValue LowerFixedLengthIntToFPToSVE(SDValue Op, SelectionDAG &DAG) const; 1242fe6060f1SDimitry Andric SDValue LowerFixedLengthFPToIntToSVE(SDValue Op, SelectionDAG &DAG) const; 1243fe6060f1SDimitry Andric SDValue LowerFixedLengthVECTOR_SHUFFLEToSVE(SDValue Op, 1244fe6060f1SDimitry Andric SelectionDAG &DAG) const; 12450b57cec5SDimitry Andric 12460b57cec5SDimitry Andric SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, 12470b57cec5SDimitry Andric SmallVectorImpl<SDNode *> &Created) const override; 124881ad6265SDimitry Andric SDValue BuildSREMPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, 124981ad6265SDimitry Andric SmallVectorImpl<SDNode *> &Created) const override; 12500b57cec5SDimitry Andric SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, 12510b57cec5SDimitry Andric int &ExtraSteps, bool &UseOneConst, 12520b57cec5SDimitry Andric bool Reciprocal) const override; 12530b57cec5SDimitry Andric SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, 12540b57cec5SDimitry Andric int &ExtraSteps) const override; 1255e8d8bef9SDimitry Andric SDValue getSqrtInputTest(SDValue Operand, SelectionDAG &DAG, 1256e8d8bef9SDimitry Andric const DenormalMode &Mode) const override; 1257e8d8bef9SDimitry Andric SDValue getSqrtResultForDenormInput(SDValue Operand, 1258e8d8bef9SDimitry Andric SelectionDAG &DAG) const override; 12590b57cec5SDimitry Andric unsigned combineRepeatedFPDivisors() const override; 12600b57cec5SDimitry Andric 12610b57cec5SDimitry Andric ConstraintType getConstraintType(StringRef Constraint) const override; 1262480093f4SDimitry Andric Register getRegisterByName(const char* RegName, LLT VT, 12638bcb0991SDimitry Andric const MachineFunction &MF) const override; 12640b57cec5SDimitry Andric 12650b57cec5SDimitry Andric /// Examine constraint string and operand type and determine a weight value. 12660b57cec5SDimitry Andric /// The operand object must already have been set up with the operand type. 12670b57cec5SDimitry Andric ConstraintWeight 12680b57cec5SDimitry Andric getSingleConstraintMatchWeight(AsmOperandInfo &info, 12690b57cec5SDimitry Andric const char *constraint) const override; 12700b57cec5SDimitry Andric 12710b57cec5SDimitry Andric std::pair<unsigned, const TargetRegisterClass *> 12720b57cec5SDimitry Andric getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 12730b57cec5SDimitry Andric StringRef Constraint, MVT VT) const override; 12740b57cec5SDimitry Andric 12750b57cec5SDimitry Andric const char *LowerXConstraint(EVT ConstraintVT) const override; 12760b57cec5SDimitry Andric 12775f757f3fSDimitry Andric void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, 12780b57cec5SDimitry Andric std::vector<SDValue> &Ops, 12790b57cec5SDimitry Andric SelectionDAG &DAG) const override; 12800b57cec5SDimitry Andric 12815f757f3fSDimitry Andric InlineAsm::ConstraintCode getInlineAsmMemConstraint(StringRef ConstraintCode)12825f757f3fSDimitry Andric getInlineAsmMemConstraint(StringRef ConstraintCode) const override { 12830b57cec5SDimitry Andric if (ConstraintCode == "Q") 12845f757f3fSDimitry Andric return InlineAsm::ConstraintCode::Q; 12850b57cec5SDimitry Andric // FIXME: clang has code for 'Ump', 'Utf', 'Usa', and 'Ush' but these are 12860b57cec5SDimitry Andric // followed by llvm_unreachable so we'll leave them unimplemented in 12870b57cec5SDimitry Andric // the backend for now. 12880b57cec5SDimitry Andric return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); 12890b57cec5SDimitry Andric } 12900b57cec5SDimitry Andric 129106c3fb27SDimitry Andric /// Handle Lowering flag assembly outputs. 129206c3fb27SDimitry Andric SDValue LowerAsmOutputForConstraint(SDValue &Chain, SDValue &Flag, 129306c3fb27SDimitry Andric const SDLoc &DL, 129406c3fb27SDimitry Andric const AsmOperandInfo &Constraint, 129506c3fb27SDimitry Andric SelectionDAG &DAG) const override; 129606c3fb27SDimitry Andric 1297fe6060f1SDimitry Andric bool shouldExtendGSIndex(EVT VT, EVT &EltTy) const override; 12985f757f3fSDimitry Andric bool shouldRemoveExtendFromGSIndex(SDValue Extend, EVT DataVT) const override; 1299480093f4SDimitry Andric bool isVectorLoadExtDesirable(SDValue ExtVal) const override; 13000b57cec5SDimitry Andric bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override; 13010b57cec5SDimitry Andric bool mayBeEmittedAsTailCall(const CallInst *CI) const override; 1302bdd1243dSDimitry Andric bool getIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, 130306c3fb27SDimitry Andric SDValue &Offset, SelectionDAG &DAG) const; 13040b57cec5SDimitry Andric bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, 13050b57cec5SDimitry Andric ISD::MemIndexedMode &AM, 13060b57cec5SDimitry Andric SelectionDAG &DAG) const override; 13070b57cec5SDimitry Andric bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, 13080b57cec5SDimitry Andric SDValue &Offset, ISD::MemIndexedMode &AM, 13090b57cec5SDimitry Andric SelectionDAG &DAG) const override; 13105f757f3fSDimitry Andric bool isIndexingLegal(MachineInstr &MI, Register Base, Register Offset, 13115f757f3fSDimitry Andric bool IsPre, MachineRegisterInfo &MRI) const override; 13120b57cec5SDimitry Andric 13130b57cec5SDimitry Andric void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, 13140b57cec5SDimitry Andric SelectionDAG &DAG) const override; 1315fe6060f1SDimitry Andric void ReplaceBITCASTResults(SDNode *N, SmallVectorImpl<SDValue> &Results, 1316fe6060f1SDimitry Andric SelectionDAG &DAG) const; 13175ffd83dbSDimitry Andric void ReplaceExtractSubVectorResults(SDNode *N, 13185ffd83dbSDimitry Andric SmallVectorImpl<SDValue> &Results, 13195ffd83dbSDimitry Andric SelectionDAG &DAG) const; 13200b57cec5SDimitry Andric 13210b57cec5SDimitry Andric bool shouldNormalizeToSelectSequence(LLVMContext &, EVT) const override; 13220b57cec5SDimitry Andric 13230b57cec5SDimitry Andric void finalizeLowering(MachineFunction &MF) const override; 13245ffd83dbSDimitry Andric 13255ffd83dbSDimitry Andric bool shouldLocalize(const MachineInstr &MI, 13265ffd83dbSDimitry Andric const TargetTransformInfo *TTI) const override; 13275ffd83dbSDimitry Andric 1328fe6060f1SDimitry Andric bool SimplifyDemandedBitsForTargetNode(SDValue Op, 1329fe6060f1SDimitry Andric const APInt &OriginalDemandedBits, 1330fe6060f1SDimitry Andric const APInt &OriginalDemandedElts, 1331fe6060f1SDimitry Andric KnownBits &Known, 1332fe6060f1SDimitry Andric TargetLoweringOpt &TLO, 1333fe6060f1SDimitry Andric unsigned Depth) const override; 1334fe6060f1SDimitry Andric 133581ad6265SDimitry Andric bool isTargetCanonicalConstantNode(SDValue Op) const override; 133681ad6265SDimitry Andric 1337e8d8bef9SDimitry Andric // With the exception of data-predicate transitions, no instructions are 1338e8d8bef9SDimitry Andric // required to cast between legal scalable vector types. However: 1339e8d8bef9SDimitry Andric // 1. Packed and unpacked types have different bit lengths, meaning BITCAST 1340e8d8bef9SDimitry Andric // is not universally useable. 1341e8d8bef9SDimitry Andric // 2. Most unpacked integer types are not legal and thus integer extends 1342e8d8bef9SDimitry Andric // cannot be used to convert between unpacked and packed types. 1343e8d8bef9SDimitry Andric // These can make "bitcasting" a multiphase process. REINTERPRET_CAST is used 1344e8d8bef9SDimitry Andric // to transition between unpacked and packed types of the same element type, 1345e8d8bef9SDimitry Andric // with BITCAST used otherwise. 1346753f127fSDimitry Andric // This function does not handle predicate bitcasts. 1347e8d8bef9SDimitry Andric SDValue getSVESafeBitCast(EVT VT, SDValue Op, SelectionDAG &DAG) const; 1348fe6060f1SDimitry Andric 13497a6dacacSDimitry Andric // Returns the runtime value for PSTATE.SM by generating a call to 13507a6dacacSDimitry Andric // __arm_sme_state. 13517a6dacacSDimitry Andric SDValue getRuntimePStateSM(SelectionDAG &DAG, SDValue Chain, SDLoc DL, 13527a6dacacSDimitry Andric EVT VT) const; 1353bdd1243dSDimitry Andric 135406c3fb27SDimitry Andric bool preferScalarizeSplat(SDNode *N) const override; 13555f757f3fSDimitry Andric 13565f757f3fSDimitry Andric unsigned getMinimumJumpTableEntries() const override; 13570fca6ea1SDimitry Andric softPromoteHalfType()13580fca6ea1SDimitry Andric bool softPromoteHalfType() const override { return true; } 13590b57cec5SDimitry Andric }; 13600b57cec5SDimitry Andric 13610b57cec5SDimitry Andric namespace AArch64 { 13620b57cec5SDimitry Andric FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 13630b57cec5SDimitry Andric const TargetLibraryInfo *libInfo); 13640b57cec5SDimitry Andric } // end namespace AArch64 13650b57cec5SDimitry Andric 13660b57cec5SDimitry Andric } // end namespace llvm 13670b57cec5SDimitry Andric 13680b57cec5SDimitry Andric #endif 1369