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Searched refs:Rd (Results 1 – 25 of 54) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrThumb2.td445 bits<4> Rd;
448 let Inst{11-8} = Rd;
458 bits<4> Rd;
462 let Inst{11-8} = Rd;
484 bits<4> Rd;
487 let Inst{11-8} = Rd;
497 bits<4> Rd;
500 let Inst{11-8} = Rd;
523 bits<4> Rd;
526 let Inst{11-8} = Rd;
[all …]
H A DARMInstrInfo.td1568 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1575 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1576 iii, opc, "\t$Rd, $Rn, $imm",
1577 [(set GPR:$Rd, (opnode GPR:$Rn, mod_imm:$imm))]>,
1579 bits<4> Rd;
1584 let Inst{15-12} = Rd;
1588 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1589 iir, opc, "\t$Rd, $Rn, $Rm",
1590 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1592 bits<4> Rd;
[all …]
H A DARMInstrThumb.td398 // ADD <Rd>, sp, #<imm8>
909 bits<3> Rd;
911 let Inst{2-0} = Rd;
919 bits<3> Rd;
922 let Inst{2-0} = Rd;
930 bits<3> Rd;
933 let Inst{2-0} = Rd;
939 bits<3> Rd;
942 let Inst{2-0} = Rd;
975 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
[all …]
H A DARMInstrCDE.td82 dag Rd;
116 !strconcat(iname, params.PAsm, "\t$coproc, $Rd, $imm"),
119 bits<4> Rd;
123 let Inst{15-12} = Rd{3-0};
132 !strconcat(iname, params.PAsm, "\t$coproc, $Rd, $Rn, $imm"),
135 bits<4> Rd;
141 let Inst{15-12} = Rd{3-0};
150 !strconcat(iname, params.PAsm, "\t$coproc, $Rd, $Rn, $Rm, $imm"),
153 bits<4> Rd;
163 let Inst{3-0} = Rd{3-0};
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64PBQPRegAlloc.cpp151 bool A57ChainingConstraint::addIntraChainConstraint(PBQPRAGraph &G, unsigned Rd, in addIntraChainConstraint() argument
153 if (Rd == Ra) in addIntraChainConstraint()
158 if (Register::isPhysicalRegister(Rd) || Register::isPhysicalRegister(Ra)) { in addIntraChainConstraint()
160 << Register::isPhysicalRegister(Rd) << '\n'); in addIntraChainConstraint()
166 PBQPRAGraph::NodeId node1 = G.getMetadata().getNodeIdForVReg(Rd); in addIntraChainConstraint()
179 const LiveInterval &ld = LIs.getInterval(Rd); in addIntraChainConstraint()
235 void A57ChainingConstraint::addInterChainConstraint(PBQPRAGraph &G, unsigned Rd, in addInterChainConstraint() argument
241 if (Rd != Ra) { in addInterChainConstraint()
243 << " to " << printReg(Rd, TRI) << '\n'); in addInterChainConstraint()
245 Chains.insert(Rd); in addInterChainConstraint()
[all …]
H A DAArch64InstrFormats.td2373 def : InstAlias<asm # "\t$Rd, $imm, $target",
2374 (!cast<Instruction>(NAME#"W") GPR32as64:$Rd,
2420 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm, "\t$Rd, $Rn", "",
2421 [(set regtype:$Rd, (node regtype:$Rn))]>,
2423 bits<5> Rd;
2433 let Inst{4-0} = Rd;
2452 : I<(outs GPR64:$dst), (ins GPR64:$Rd, GPR64sp:$Rn), asm, "\t$Rd, $Rn",
2453 "$dst = $Rd", [(set GPR64:$dst, (op GPR64:$Rd, opcode, GPR64sp:$Rn))]>,
2455 bits<5> Rd;
2461 let Inst{4-0} = Rd;
[all …]
H A DAArch64PBQPRegAlloc.h32 bool addIntraChainConstraint(PBQPRAGraph &G, unsigned Rd, unsigned Ra);
35 void addInterChainConstraint(PBQPRAGraph &G, unsigned Rd, unsigned Ra);
H A DAArch64SchedPredicates.td284 [// MOV {Rd, SP}, {SP, Rn} =>
285 // ADD {Rd, SP}, {SP, Rn}, #0
298 // MOV Rd, Rm =>
299 // ORR Rd, ZR, Rm, LSL #0
313 [// ORR Rd, ZR, #0
343 def IsRORImmIdiomPred : MCSchedPredicate< // EXTR Rd, Rs, Rs, #Imm
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.td278 def LO : InstRI<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, LoExt:$imm16),
279 !strconcat(AsmStr, "\t$Rs1, $imm16, $Rd"),
282 def HI : InstRI<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, HiExt:$imm16),
283 !strconcat(AsmStr, "\t$Rs1, $imm16, $Rd"),
294 def R : InstRR<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, GPR:$Rs2, pred:$DDDI),
295 !strconcat(AsmStr, "$DDDI\t$Rs1, $Rs2, $Rd"),
296 [(set GPR:$Rd, (OpNode GPR:$Rs1, GPR:$Rs2))]>;
302 [(set GPR:$Rd, (OpNode GPR:$Rs1, LoExt:$imm16))],
303 [(set GPR:$Rd, (OpNode GPR:$Rs1, HiExt:$imm16))]>;
307 def R : InstRR<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, GPR:$Rs2, pred:$DDDI),
[all …]
H A DLanaiInstrFormats.td34 // opcode Rd Rs1 constant (16)
37 // Rd <- Rs1 op constant
83 // A Jump is accomplished by `Rd' being `pc', and it has one shadow.
90 bits<5> Rd;
98 let Inst{27 - 23} = Rd;
112 // opcode Rd Rs1 Rs2 \ operation /
115 // `Rd <- Rs1 op Rs2' iff condition DDDI is true.
131 // instructions in *Note RI::). For the SELECT operation, Rd gets Rs1 if
145 // A Jump is accomplished by `Rd' being `pc', and it has one shadow.
150 bits<5> Rd;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.td62 // Rd - 64-bit registers.
63 class Rd<bits<5> num, string n, list<Register> subregs,
137 def D0 : Rd< 0, "r1:0", [R0, R1]>, DwarfRegNum<[32]>;
138 def D1 : Rd< 2, "r3:2", [R2, R3]>, DwarfRegNum<[34]>;
139 def D2 : Rd< 4, "r5:4", [R4, R5]>, DwarfRegNum<[36]>;
140 def D3 : Rd< 6, "r7:6", [R6, R7]>, DwarfRegNum<[38]>;
141 def D4 : Rd< 8, "r9:8", [R8, R9]>, DwarfRegNum<[40]>;
142 def D5 : Rd<10, "r11:10", [R10, R11]>, DwarfRegNum<[42]>;
143 def D6 : Rd<12, "r13:12", [R12, R13]>, DwarfRegNum<[44]>;
144 def D7 : Rd<14, "r15:14", [R14, R15]>, DwarfRegNum<[46]>;
[all …]
H A DHexagonConstExtenders.cpp312 Register Rd; member
383 OffsetRange getOffsetRange(Register Rd) const;
486 if (ED.Rd.Reg != 0) in operator <<()
487 OS << printReg(ED.Rd.Reg, &HRI, ED.Rd.Sub); in operator <<()
1116 OffsetRange HCE::getOffsetRange(Register Rd) const { in getOffsetRange()
1118 for (const MachineOperand &Op : MRI->use_operands(Rd.Reg)) { in getOffsetRange()
1122 if (Rd != Register(Op)) in getOffsetRange()
1124 Range.intersect(getOffsetRange(Rd, *Op.getParent())); in getOffsetRange()
1151 ED.Rd = MI.getOperand(OpNum-1); in recordExtender()
1171 ED.Rd = MI.getOperand(0); in recordExtender()
[all …]
H A DHexagonPseudo.td65 def CONST32 : CONSTLDInst<(outs IntRegs:$Rd), (ins i32imm:$v),
66 "$Rd = CONST32(#$v)", []>;
67 def CONST64 : CONSTLDInst<(outs DoubleRegs:$Rd), (ins i64imm:$v),
68 "$Rd = CONST64(#$v)", []>;
271 def PS_aligna : Pseudo<(outs IntRegs:$Rd), (ins u32_0Imm:$A), "", []>;
282 def PS_fi : Pseudo<(outs IntRegs:$Rd),
285 def PS_fia : Pseudo<(outs IntRegs:$Rd),
335 def PS_alloca: Pseudo <(outs IntRegs:$Rd),
354 def PS_pselect: InstHexagon<(outs DoubleRegs:$Rd),
535 def PS_vmulw : PseudoM<(outs DoubleRegs:$Rd),
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRInstrInfo.td361 // ADD Rd, Rr
367 // ADDW Rd+1:Rd, Rr+1:Rr
371 // add Rd, Rr
372 // adc Rd+1, Rr+1
377 // ADC Rd, Rr
384 // ADCW Rd+1:Rd, Rr+1:Rr
389 // adc Rd, Rr
390 // adc Rd+1, Rr+1
396 // AIDW Rd, k
397 // Adds an immediate 6-bit value K to Rd, placing the result in Rd.
[all …]
/freebsd/contrib/llvm-project/compiler-rt/lib/xray/
H A Dxray_riscv.cpp46 uint32_t Rs2, uint32_t Rd) { in encodeRTypeInstruction() argument
47 return Rs2 << 20 | Rs1 << 15 | Rd << 7 | Opcode; in encodeRTypeInstruction()
51 uint32_t Rd, uint32_t Imm) { in encodeITypeInstruction() argument
52 return Imm << 20 | Rs1 << 15 | Rd << 7 | Opcode; in encodeITypeInstruction()
62 static inline uint32_t encodeUTypeInstruction(uint32_t Opcode, uint32_t Rd, in encodeUTypeInstruction() argument
64 return Imm << 12 | Rd << 7 | Opcode; in encodeUTypeInstruction()
67 static inline uint32_t encodeJTypeInstruction(uint32_t Opcode, uint32_t Rd, in encodeJTypeInstruction() argument
73 return ImmMSB | ImmLSB | Imm11 | Imm1912 | Rd << 7 | Opcode; in encodeJTypeInstruction()
H A Dxray_loongarch64.cpp31 encodeInstruction2RIx(uint32_t Opcode, uint32_t Rd, uint32_t Rj, in encodeInstruction2RIx() argument
33 return Opcode | (Imm << 10) | (Rj << 5) | Rd; in encodeInstruction2RIx()
38 encodeInstruction1RI20(uint32_t Opcode, uint32_t Rd, in encodeInstruction1RI20() argument
40 return Opcode | (Imm << 5) | Rd; in encodeInstruction1RI20()
H A Dxray_mips.cpp47 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd, in encodeSpecialInstruction() argument
49 return (Rs << 21 | Rt << 16 | Rd << 11 | Imm << 6 | Opcode); in encodeSpecialInstruction()
H A Dxray_mips64.cpp48 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd, in encodeSpecialInstruction() argument
50 return (Rs << 21 | Rt << 16 | Rd << 11 | Imm << 6 | Opcode); in encodeSpecialInstruction()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp550 unsigned Rd = fieldFromInstruction(Insn, 0, 5); in DecodeFMOVLaneInstruction() local
556 Inst, Rd, Address, Decoder); in DecodeFMOVLaneInstruction()
561 Inst, Rd, Address, Decoder); in DecodeFMOVLaneInstruction()
653 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeThreeAddrSRegInstruction() local
681 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rd, Addr, in DecodeThreeAddrSRegInstruction()
705 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd, Addr, in DecodeThreeAddrSRegInstruction()
721 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeMoveImmInstruction() local
733 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rd, Addr, in DecodeMoveImmInstruction()
739 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd, Addr, in DecodeMoveImmInstruction()
1332 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeAddSubERegInstruction() local
[all …]
/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM/
H A DEmulateInstructionARM.cpp1168 uint32_t Rd; // the destination register in EmulateADDRdSPImm() local
1172 Rd = 7; in EmulateADDRdSPImm()
1176 Rd = Bits32(opcode, 15, 12); in EmulateADDRdSPImm()
1186 if (Rd == GetFramePointerRegisterNumber()) in EmulateADDRdSPImm()
1194 if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + Rd, in EmulateADDRdSPImm()
1229 uint32_t Rd; // the destination register in EmulateMOVRdSP() local
1232 Rd = 7; in EmulateMOVRdSP()
1235 Rd = 12; in EmulateMOVRdSP()
1242 if (Rd == GetFramePointerRegisterNumber()) in EmulateMOVRdSP()
1250 if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + Rd, sp)) in EmulateMOVRdSP()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.td49 // Rd - Slots in the FP register file for 64-bit floating-point values.
50 class Rd<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> {
210 def D0 : Rd< 0, "f0", [F0, F1]>, DwarfRegNum<[72]>;
211 def D1 : Rd< 2, "f2", [F2, F3]>, DwarfRegNum<[73]>;
212 def D2 : Rd< 4, "f4", [F4, F5]>, DwarfRegNum<[74]>;
213 def D3 : Rd< 6, "f6", [F6, F7]>, DwarfRegNum<[75]>;
214 def D4 : Rd< 8, "f8", [F8, F9]>, DwarfRegNum<[76]>;
215 def D5 : Rd<10, "f10", [F10, F11]>, DwarfRegNum<[77]>;
216 def D6 : Rd<12, "f12", [F12, F13]>, DwarfRegNum<[78]>;
217 def D7 : Rd<1
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp2438 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeQADDInstruction() local
2446 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) in DecodeQADDInstruction()
2694 unsigned Rd = fieldFromInstruction(Insn, 8, 4); in DecodeT2MOVTWInstruction() local
2703 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) in DecodeT2MOVTWInstruction()
2705 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) in DecodeT2MOVTWInstruction()
2719 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeArmMOVTWInstruction() local
2727 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) in DecodeArmMOVTWInstruction()
2730 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) in DecodeArmMOVTWInstruction()
2747 unsigned Rd = fieldFromInstruction(Insn, 16, 4); in DecodeSMLAInstruction() local
2756 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) in DecodeSMLAInstruction()
[all …]
/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/
H A DRISCVInstructions.h22 struct Rd { struct
45 Rd rd; \ argument
59 Rd rd; \
67 Rd rd; \
74 Rd rd; \
81 Rd rd; \
87 Rd rd; \
H A DRISCVCInstructions.h25 operator Rd() { return Rd{rd + (shift ? 8 : 0)}; } in Rd() function
120 return JAL{Rd{0}, uint32_t(offset)}; in DecodeC_J()
121 return JAL{Rd{0}, uint32_t(int32_t(int16_t(offset | 0xf000)))}; in DecodeC_J()
128 return JALR{Rd{0}, rs1, 0}; in DecodeC_JR()
135 return JALR{Rd{1}, rs1, 0}; in DecodeC_JALR()
183 return ADDI{Rd{gpr_sp_riscv}, Rs{gpr_sp_riscv}, uint32_t(nzimm)}; in DecodeC_LUI_ADDI16SP()
184 return ADDI{Rd{gpr_sp_riscv}, Rs{gpr_sp_riscv}, in DecodeC_LUI_ADDI16SP()
/freebsd/sys/arm64/arm64/
H A Dundefined.c187 int attempts, error, Rn, Rd, Rm; in swp_emulate() local
204 Rd = (insn & 0xf000) >> 12; in swp_emulate()
240 regs[Rd] = val; in swp_emulate()

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