Lines Matching refs:Rd
399 // ADD <Rd>, sp, #<imm8>
910 bits<3> Rd;
912 let Inst{2-0} = Rd;
920 bits<3> Rd;
923 let Inst{2-0} = Rd;
931 bits<3> Rd;
934 let Inst{2-0} = Rd;
940 bits<3> Rd;
943 let Inst{2-0} = Rd;
976 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
978 "add", "\t$Rd, $Rm, $imm3",
979 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]>,
995 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
997 "add", "\t$Rd, $Rn, $Rm",
998 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>,
1015 def tADDSi3 : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
1017 [(set tGPR:$Rd, CPSR, (ARMaddc tGPR:$Rm,
1030 def tADDSrr : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
1032 [(set tGPR:$Rd, CPSR, (ARMaddc tGPR:$Rn,
1079 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
1081 "asr", "\t$Rd, $Rm, $imm5",
1082 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]>,
1164 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_31:$imm5),
1166 "lsl", "\t$Rd, $Rm, $imm5",
1167 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]>,
1182 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
1184 "lsr", "\t$Rd, $Rm, $imm5",
1185 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm_sr:$imm5)))]>,
1200 def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255_expr:$imm8), IIC_iMOVi,
1201 "mov", "\t$Rd, $imm8",
1202 [(set tGPR:$Rd, imm0_255_expr:$imm8)]>,
1205 bits<3> Rd;
1207 let Inst{10-8} = Rd;
1218 def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
1220 "mov", "\t$Rd, $Rm", "", []>,
1223 bits<4> Rd;
1225 let Inst{7} = Rd{3};
1227 let Inst{2-0} = Rd{2-0};
1230 def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1231 "movs\t$Rd, $Rm", []>, Encoding16, Sched<[WriteALU]> {
1233 bits<3> Rd;
1237 let Inst{2-0} = Rd;
1244 Thumb1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), AddrModeNone, 2,
1245 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", "$Rm = $Rd",
1246 [(set tGPR:$Rd, (mul tGPR:$Rn, tGPR:$Rm))]>,
1248 bits<3> Rd;
1251 let Inst{2-0} = Rd;
1260 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr,
1261 "mvn", "\t$Rd, $Rn",
1262 [(set tGPR:$Rd, (not tGPR:$Rn))]>, Sched<[WriteALU]>;
1274 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1276 "rev", "\t$Rd, $Rm",
1277 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>,
1281 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1283 "rev16", "\t$Rd, $Rm",
1284 [(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))]>,
1288 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1290 "revsh", "\t$Rd, $Rm",
1291 [(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))]>,
1304 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn),
1306 "rsb", "\t$Rd, $Rn, #0",
1307 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>, Sched<[WriteALU]>;
1320 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
1322 "sub", "\t$Rd, $Rm, $imm3",
1323 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]>,
1346 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
1348 "sub", "\t$Rd, $Rn, $Rm",
1349 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>,
1369 def tSUBSi3 : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
1371 [(set tGPR:$Rd, CPSR, (ARMsubc tGPR:$Rm,
1383 def tSUBSrr : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
1385 [(set tGPR:$Rd, CPSR, (ARMsubc tGPR:$Rn,
1390 def tRSBS : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rn),
1392 [(set tGPR:$Rd, CPSR, (ARMsubc 0, tGPR:$Rn))]>,
1396 def tLSLSri : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rn, imm0_31:$imm5),
1398 [(set tGPR:$Rd, CPSR, (ARMlsls tGPR:$Rn, imm0_31:$imm5))]>,
1405 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1407 "sxtb", "\t$Rd, $Rm",
1408 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>,
1414 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1416 "sxth", "\t$Rd, $Rm",
1417 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>,
1450 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1452 "uxtb", "\t$Rd, $Rm",
1453 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>,
1459 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1461 "uxth", "\t$Rd, $Rm",
1462 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>,
1476 def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p),
1477 IIC_iALUi, "adr{$p}\t$Rd, $addr", []>,
1479 bits<3> Rd;
1481 let Inst{10-8} = Rd;
1487 def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p),
1491 def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd),
1769 def : tInstAlias<"neg${s}${p} $Rd, $Rm",
1770 (tRSB tGPR:$Rd, s_cc_out:$s, tGPR:$Rm, pred:$p)>;
1793 let Constraints = "@earlyclobber $Rd,@earlyclobber $temp",
1795 def tCMP_SWAP_8 : PseudoInst<(outs GPR:$Rd, tGPR:$temp),
1799 def tCMP_SWAP_16 : PseudoInst<(outs GPR:$Rd, tGPR:$temp),
1803 def tCMP_SWAP_32 : PseudoInst<(outs GPR:$Rd, tGPR:$temp),