Lines Matching refs:Rd
2241 def : InstAlias<asm # "\t$Rd, $imm, $target",
2242 (!cast<Instruction>(NAME#"W") GPR32as64:$Rd,
2288 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm, "\t$Rd, $Rn", "",
2289 [(set regtype:$Rd, (node regtype:$Rn))]>,
2291 bits<5> Rd;
2301 let Inst{4-0} = Rd;
2320 : I<(outs GPR64:$dst), (ins GPR64:$Rd, GPR64sp:$Rn), asm, "\t$Rd, $Rn",
2321 "$dst = $Rd", [(set GPR64:$dst, (op GPR64:$Rd, opcode, GPR64sp:$Rn))]>,
2323 bits<5> Rd;
2329 let Inst{4-0} = Rd;
2334 : I<(outs GPR64:$dst), (ins GPR64:$Rd), asm, "\t$Rd", "$dst = $Rd",
2335 [(set GPR64:$dst, (op GPR64:$Rd, opcode, (i64 0)))]>,
2337 bits<5> Rd;
2342 let Inst{4-0} = Rd;
2347 : I<(outs GPR64:$Rd), (ins GPR64:$Rn, GPR64sp:$Rm),
2348 asm, "\t$Rd, $Rn, $Rm", "",
2349 [(set GPR64:$Rd, (OpNode GPR64:$Rn, GPR64sp:$Rm))]>,
2351 bits<5> Rd;
2359 let Inst{4-0} = Rd;
2363 : I<(outs GPR64:$Rd), (ins GPR64:$Rn), asm, "\t$Rd", "$Rd = $Rn", []>, Sched<[]> {
2364 bits<5> Rd;
2368 let Inst{4-0} = Rd;
2383 let Inst{4-0} = 0b11110; // Rd
2406 let Inst{4-0} = 0b11111; // Rd
2420 let Inst{4-0} = 0b11110; // Rd
2475 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
2476 asm, "\t$Rd, $Rn, $Rm", "", pattern>,
2479 bits<5> Rd;
2487 let Inst{4-0} = Rd;
2493 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV))]>;
2498 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV)),
2531 : I<(outs regtype:$Rd), (ins in1regtype:$Rn, in2regtype:$Rm),
2532 asm, "\t$Rd, $Rn, $Rm", "",
2533 [(set regtype:$Rd, (OpNode in1regtype:$Rn, in2regtype:$Rm))]> {
2534 bits<5> Rd;
2544 let Inst{4-0} = Rd;
2602 : I<(outs addtype:$Rd), (ins multype:$Rn, multype:$Rm, addtype:$Ra),
2603 asm, "\t$Rd, $Rn, $Rm, $Ra", "", pattern> {
2604 bits<5> Rd;
2614 let Inst{4-0} = Rd;
2633 [(set GPR64:$Rd, (AccNode GPR64:$Ra,
2640 : I<(outs GPR64:$Rd), (ins GPR64:$Rn, GPR64:$Rm),
2641 asm, "\t$Rd, $Rn, $Rm", "",
2642 [(set GPR64:$Rd, (OpNode GPR64:$Rn, GPR64:$Rm))]>,
2644 bits<5> Rd;
2652 let Inst{4-0} = Rd;
2671 : I<(outs GPR32:$Rd), (ins GPR32:$Rn, StreamReg:$Rm),
2672 asm, "\t$Rd, $Rn, $Rm", "",
2673 [(set GPR32:$Rd, (OpNode GPR32:$Rn, StreamReg:$Rm))]>,
2675 bits<5> Rd;
2686 let Inst{4-0} = Rd;
2730 : I<(outs regtype:$Rd), (ins movimm32_imm:$imm, shifter:$shift),
2731 asm, "\t$Rd, $imm$shift", "", []>,
2733 bits<5> Rd;
2740 let Inst{4-0} = Rd;
2758 : I<(outs regtype:$Rd),
2760 asm, "\t$Rd, $imm$shift", "$src = $Rd", []>,
2762 bits<5> Rd;
2769 let Inst{4-0} = Rd;
2791 : I<(outs dstRegtype:$Rd), inputs, asm_inst, asm_ops, "", [pattern]>,
2793 bits<5> Rd;
2799 let Inst{4-0} = Rd;
2805 : BaseAddSubImm<isSub, setFlags, dstRegtype, asm_inst, "\t$Rd, $Rn, $imm",
2807 (set dstRegtype:$Rd, (OpNode srcRegtype:$Rn, immtype:$imm))> {
2817 : Pseudo<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
2818 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]>,
2824 : I<(outs regtype:$Rd), (ins regtype:$Rn, (shifted_regtype $Rm, $shift):$Rm_and_shift),
2825 asm, "\t$Rd, $Rn, $Rm_and_shift", "",
2826 [(set regtype:$Rd, (OpNode regtype:$Rn, shifted_regtype:$Rm_and_shift))]>,
2828 bits<5> Rd;
2840 let Inst{4-0} = Rd;
2848 : I<(outs dstRegtype:$Rd),
2850 asm, "\t$Rd, $Rn, $Rm_and_extend", "",
2851 [(set dstRegtype:$Rd, (OpNode src1Regtype:$Rn, src2Regtype:$Rm_and_extend))]>,
2853 bits<5> Rd;
2865 let Inst{4-0} = Rd;
2874 : I<(outs dstRegtype:$Rd),
2876 asm, "\t$Rd, $Rn, $Rm$ext", "", []>,
2878 bits<5> Rd;
2890 let Inst{4-0} = Rd;
2956 // add Rd, Rb, -imm -> sub Rd, Rn, imm
2957 def : InstSubst<alias#"\t$Rd, $Rn, $imm",
2958 (!cast<Instruction>(NAME # "Wri") GPR32sp:$Rd, GPR32sp:$Rn,
2960 def : InstSubst<alias#"\t$Rd, $Rn, $imm",
2961 (!cast<Instruction>(NAME # "Xri") GPR64sp:$Rd, GPR64sp:$Rn,
3031 // Support negative immediates, e.g. adds Rd, Rn, -imm -> subs Rd, Rn, imm
3032 def : InstSubst<alias#"\t$Rd, $Rn, $imm",
3033 (!cast<Instruction>(NAME # "Wri") GPR32:$Rd, GPR32sp:$Rn,
3035 def : InstSubst<alias#"\t$Rd, $Rn, $imm",
3036 (!cast<Instruction>(NAME # "Xri") GPR64:$Rd, GPR64sp:$Rn,
3088 isSub, 0, GPR64sp, asm_inst, "\t$Rd, $Rn, $imm6, $imm4",
3090 (set GPR64sp:$Rd, (OpNode GPR64sp:$Rn, imm0_63:$imm6, imm0_15:$imm4))> {
3114 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, imm_type:$imm),
3115 asm, "\t$Rd, $Rn, $Rm, $imm", "", patterns>,
3117 bits<5> Rd;
3127 let Inst{4-0} = Rd;
3132 [(set GPR32:$Rd,
3140 [(set GPR64:$Rd,
3155 : I<(outs regtype:$Rd), (ins regtype:$Rn, imm_type:$immr, imm_type:$imms),
3156 asm, "\t$Rd, $Rn, $immr, $imms", "", []>,
3158 bits<5> Rd;
3168 let Inst{4-0} = Rd;
3188 : I<(outs regtype:$Rd), (ins regtype:$src, regtype:$Rn, imm_type:$immr,
3190 asm, "\t$Rd, $Rn, $immr, $imms", "$src = $Rd", []>,
3192 bits<5> Rd;
3202 let Inst{4-0} = Rd;
3227 : I<(outs dregtype:$Rd), (ins sregtype:$Rn, imm_type:$imm),
3228 asm, "\t$Rd, $Rn, $imm", "", pattern>,
3230 bits<5> Rd;
3239 let Inst{4-0} = Rd;
3248 : I<(outs regtype:$Rd), (ins regtype:$Rn, (shifted_regtype $Rm, $shift):$Rm_and_shift),
3249 asm, "\t$Rd, $Rn, $Rm_and_shift", "", pattern>,
3251 bits<5> Rd;
3262 let Inst{4-0} = Rd;
3276 [(set GPR32sp:$Rd, (OpNode GPR32:$Rn,
3283 [(set GPR64sp:$Rd, (OpNode GPR64:$Rn,
3288 def : InstSubst<Alias # "\t$Rd, $Rn, $imm",
3289 (!cast<Instruction>(NAME # "Wri") GPR32sp:$Rd, GPR32:$Rn,
3291 def : InstSubst<Alias # "\t$Rd, $Rn, $imm",
3292 (!cast<Instruction>(NAME # "Xri") GPR64sp:$Rd, GPR64:$Rn,
3300 [(set GPR32:$Rd, (OpNode GPR32:$Rn, logical_imm32:$imm))]> {
3305 [(set GPR64:$Rd, (OpNode GPR64:$Rn, logical_imm64:$imm))]> {
3310 def : InstSubst<Alias # "\t$Rd, $Rn, $imm",
3311 (!cast<Instruction>(NAME # "Wri") GPR32:$Rd, GPR32:$Rn,
3313 def : InstSubst<Alias # "\t$Rd, $Rn, $imm",
3314 (!cast<Instruction>(NAME # "Xri") GPR64:$Rd, GPR64:$Rn,
3319 : Pseudo<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
3320 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]>,
3332 [(set GPR32:$Rd, (OpNode GPR32:$Rn,
3337 [(set GPR64:$Rd, (OpNode GPR64:$Rn,
3356 [(set GPR32:$Rd, (OpNode GPR32:$Rn, logical_shifted_reg32:$Rm_and_shift))]> {
3360 [(set GPR64:$Rd, (OpNode GPR64:$Rn, logical_shifted_reg64:$Rm_and_shift))]> {
3449 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, ccode:$cond),
3450 asm, "\t$Rd, $Rn, $Rm, $cond", "",
3451 [(set regtype:$Rd,
3456 bits<5> Rd;
3467 let Inst{4-0} = Rd;
3481 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, ccode:$cond),
3482 asm, "\t$Rd, $Rn, $Rm, $cond", "",
3483 [(set regtype:$Rd,
3489 bits<5> Rd;
3500 let Inst{4-0} = Rd;
4918 : I<(outs dstType:$Rd), (ins srcType:$Rn),
4919 asm, "\t$Rd, $Rn", "", pattern>,
4921 bits<5> Rd;
4931 let Inst{4-0} = Rd;
4938 : I<(outs dstType:$Rd), (ins srcType:$Rn, immType:$scale),
4939 asm, "\t$Rd, $Rn, $scale", "", pattern>,
4941 bits<5> Rd;
4952 let Inst{4-0} = Rd;
4959 [(set GPR32:$Rd, (OpN (f16 FPR16:$Rn)))]> {
4966 [(set GPR64:$Rd, (OpN (f16 FPR16:$Rn)))]> {
4973 [(set GPR32:$Rd, (OpN FPR32:$Rn))]> {
4979 [(set GPR64:$Rd, (OpN FPR32:$Rn))]> {
4985 [(set GPR32:$Rd, (OpN (f64 FPR64:$Rn)))]> {
4991 [(set GPR64:$Rd, (OpN (f64 FPR64:$Rn)))]> {
5001 [(set GPR32:$Rd, (OpN (fmul (f16 FPR16:$Rn),
5011 [(set GPR64:$Rd, (OpN (fmul (f16 FPR16:$Rn),
5020 [(set GPR32:$Rd, (OpN (fmul FPR32:$Rn,
5029 [(set GPR64:$Rd, (OpN (fmul FPR32:$Rn,
5037 [(set GPR32:$Rd, (OpN (fmul FPR64:$Rn,
5046 [(set GPR64:$Rd, (OpN (fmul FPR64:$Rn,
5060 : I<(outs dstType:$Rd), (ins srcType:$Rn, immType:$scale),
5061 asm, "\t$Rd, $Rn, $scale", "", pattern>,
5063 bits<5> Rd;
5071 let Inst{4-0} = Rd;
5078 : I<(outs dstType:$Rd), (ins srcType:$Rn),
5079 asm, "\t$Rd, $Rn", "", [(set (dvt dstType:$Rd), (node srcType:$Rn))]>,
5081 bits<5> Rd;
5089 let Inst{4-0} = Rd;
5128 [(set (f16 FPR16:$Rd),
5138 [(set FPR32:$Rd,
5147 [(set FPR64:$Rd,
5156 [(set (f16 FPR16:$Rd),
5165 [(set FPR32:$Rd,
5173 [(set FPR64:$Rd,
5189 : I<(outs dstType:$Rd), (ins srcType:$Rn), asm, "\t$Rd, $Rn", "",
5195 [/*(set (dvt dstType:$Rd), (bitconvert (svt srcType:$Rn)))*/]>,
5197 bits<5> Rd;
5205 let Inst{4-0} = Rd;
5212 : I<(outs dstType:$Rd), (ins srcType:$Rn, VectorIndex1:$idx), asm,
5213 "{\t$Rd"#kind#"$idx, $Rn|"#kind#"\t$Rd$idx, $Rn}", "", []>,
5215 bits<5> Rd;
5223 let Inst{4-0} = Rd;
5232 : I<(outs dstType:$Rd), (ins srcType:$Rn, VectorIndex1:$idx), asm,
5233 "{\t$Rd, $Rn"#kind#"$idx|"#kind#"\t$Rd, $Rn$idx}", "", []>,
5235 bits<5> Rd;
5243 let Inst{4-0} = Rd;
5314 : I<(outs dstType:$Rd), (ins srcType:$Rn), asm, "\t$Rd, $Rn", "", pattern>,
5316 bits<5> Rd;
5324 let Inst{4-0} = Rd;
5330 [(set (f16 FPR16:$Rd), (any_fpround FPR64:$Rn))]>;
5334 [(set FPR32:$Rd, (any_fpround FPR64:$Rn))]>;
5338 [(set FPR64:$Rd, (any_fpextend (f16 FPR16:$Rn)))]>;
5342 [(set FPR32:$Rd, (any_fpextend (f16 FPR16:$Rn)))]>;
5346 [(set FPR64:$Rd, (any_fpextend FPR32:$Rn))]>;
5350 [(set (f16 FPR16:$Rd), (any_fpround FPR32:$Rn))]>;
5360 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm, "\t$Rd, $Rn", "",
5361 [(set (vt regtype:$Rd), (node (vt regtype:$Rn)))]>,
5363 bits<5> Rd;
5370 let Inst{4-0} = Rd;
5420 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
5421 asm, "\t$Rd, $Rn, $Rm", "", pat>,
5423 bits<5> Rd;
5432 let Inst{4-0} = Rd;
5438 [(set (f16 FPR16:$Rd),
5445 [(set (f32 FPR32:$Rd),
5451 [(set (f64 FPR64:$Rd),
5460 [(set (f16 FPR16:$Rd), (fneg (node (f16 FPR16:$Rn), (f16 FPR16:$Rm))))]> {
5466 [(set FPR32:$Rd, (fneg (node FPR32:$Rn, (f32 FPR32:$Rm))))]> {
5471 [(set FPR64:$Rd, (fneg (node FPR64:$Rn, (f64 FPR64:$Rm))))]> {
5484 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, regtype: $Ra),
5485 asm, "\t$Rd, $Rn, $Rm, $Ra", "", pat>,
5487 bits<5> Rd;
5497 let Inst{4-0} = Rd;
5503 [(set (f16 FPR16:$Rd),
5510 [(set FPR32:$Rd,
5516 [(set FPR64:$Rd,
5691 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, ccode:$cond),
5692 asm, "\t$Rd, $Rn, $Rm, $cond", "",
5693 [(set regtype:$Rd,
5697 bits<5> Rd;
5708 let Inst{4-0} = Rd;
5733 : I<(outs regtype:$Rd), (ins fpimmtype:$imm), asm, "\t$Rd, $imm", "",
5734 [(set regtype:$Rd, fpimmtype:$imm)]>,
5736 bits<5> Rd;
5742 let Inst{4-0} = Rd;
5775 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm), asm,
5776 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind #
5777 "|" # kind # "\t$Rd, $Rn, $Rm|}", "", pattern>,
5779 bits<5> Rd;
5791 let Inst{4-0} = Rd;
5798 : I<(outs regtype:$dst), (ins regtype:$Rd, regtype:$Rn, regtype:$Rm), asm,
5799 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind #
5800 "|" # kind # "\t$Rd, $Rn, $Rm}", "$Rd = $dst", pattern>,
5802 bits<5> Rd;
5814 let Inst{4-0} = Rd;
5819 : Pseudo<(outs regtype:$dst), (ins regtype:$Rd, regtype:$Rn, regtype:$Rm), pattern>,
5825 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
5828 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn),
5863 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
5866 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn), (v16i8 V128:$Rm)))]>;
5869 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
5872 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
5875 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
5878 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
5881 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (v2i64 V128:$Rm)))]>;
5907 [(set V64:$Rd, (v8i8 (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm))))]>;
5910 [(set V128:$Rd, (v16i8 (OpNode (v16i8 V128:$Rn), (v16i8 V128:$Rm))))]>;
5913 [(set V64:$Rd, (v4i16 (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm))))]>;
5916 [(set V128:$Rd, (v8i16 (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm))))]>;
5919 [(set V64:$Rd, (v2i32 (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm))))]>;
5922 [(set V128:$Rd, (v4i32 (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm))))]>;
5930 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
5934 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn), (v16i8 V128:$Rm)))]>;
5938 (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
5942 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
5946 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
5950 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
5958 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
5961 [(set (v16i8 V128:$Rd),
5972 [(set (v4f16 V64:$Rd), (OpNode (v4f16 V64:$Rn), (v4f16 V64:$Rm)))]>;
5975 [(set (v8f16 V128:$Rd), (OpNode (v8f16 V128:$Rn), (v8f16 V128:$Rm)))]>;
5979 [(set (v2f32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
5982 [(set (v4f32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
5985 [(set (v2f64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
5995 [(set (v4i16 V64:$Rd), (OpNode (v4f16 V64:$Rn), (v4f16 V64:$Rm)))]>;
5998 [(set (v8i16 V128:$Rd), (OpNode (v8f16 V128:$Rn), (v8f16 V128:$Rm)))]>;
6002 [(set (v2i32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
6005 [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
6008 [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
6018 (OpNode (v4f16 V64:$Rd), (v4f16 V64:$Rn), (v4f16 V64:$Rm)))]>;
6022 (OpNode (v8f16 V128:$Rd), (v8f16 V128:$Rn), (v8f16 V128:$Rm)))]>;
6027 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
6031 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
6035 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
6044 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
6047 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
6050 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
6053 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
6061 [(set (v8i8 V64:$Rd), (OpNode V64:$Rn, V64:$Rm))]>;
6064 [(set (v16i8 V128:$Rd), (OpNode V128:$Rn, V128:$Rm))]>;
6086 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
6090 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn),
6128 (OpNode (AccumType RegType:$Rd),
6131 let AsmString = !strconcat(asm, "{\t$Rd" # kind1 # ", $Rn" # kind2 # ", $Rm" # kind2 # "}");
6151 (OpNode (AccumType RegType:$Rd),
6154 let AsmString = !strconcat(asm, "{\t$Rd" # kind1 # ", $Rn" # kind2 # ", $Rm" # kind2 # "}");
6185 : I<(outs regtype1:$Rd), (ins regtype2:$Rn, regtype2:$Rm), asm,
6186 "\t$Rd" # kind1 # ", $Rn" # kind2 # ", $Rm" # kind2, "", []>, Sched<[]> {
6187 bits<5> Rd;
6201 let Inst{4-0} = Rd;
6242 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm,
6243 "{\t$Rd" # dstkind # ", $Rn" # srckind #
6244 "|" # dstkind # "\t$Rd, $Rn}", "", pattern>,
6246 bits<5> Rd;
6259 let Inst{4-0} = Rd;
6267 : I<(outs regtype:$dst), (ins regtype:$Rd, regtype:$Rn), asm,
6268 "{\t$Rd" # dstkind # ", $Rn" # srckind #
6269 "|" # dstkind # "\t$Rd, $Rn}", "$Rd = $dst", pattern>,
6271 bits<5> Rd;
6284 let Inst{4-0} = Rd;
6292 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
6295 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
6298 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn)))]>;
6301 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
6304 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
6307 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
6313 : I<(outs V128:$Rd), (ins regtype:$Rn), asm,
6314 "{\t$Rd" # dstkind # ", $Rn" # srckind # ", #" # amount #
6315 "|" # dstkind # "\t$Rd, $Rn, #" # amount # "}", "", []>,
6317 bits<5> Rd;
6325 let Inst{4-0} = Rd;
6350 [(set (v4i16 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
6353 [(set (v8i16 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
6356 [(set (v2i32 V64:$Rd), (OpNode (v4i16 V64:$Rn)))]>;
6359 [(set (v4i32 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
6362 [(set (v1i64 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
6365 [(set (v2i64 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
6372 [(set (v4i16 V64:$dst), (OpNode (v4i16 V64:$Rd),
6376 [(set (v8i16 V128:$dst), (OpNode (v8i16 V128:$Rd),
6380 [(set (v2i32 V64:$dst), (OpNode (v2i32 V64:$Rd),
6384 [(set (v4i32 V128:$dst), (OpNode (v4i32 V128:$Rd),
6388 [(set (v1i64 V64:$dst), (OpNode (v1i64 V64:$Rd),
6392 [(set (v2i64 V128:$dst), (OpNode (v2i64 V128:$Rd),
6401 [(set (v8i8 V64:$dst), (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn)))]>;
6404 [(set (v16i8 V128:$dst), (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn)))]>;
6407 [(set (v4i16 V64:$dst), (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn)))]>;
6410 [(set (v8i16 V128:$dst), (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn)))]>;
6413 [(set (v2i32 V64:$dst), (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn)))]>;
6416 [(set (v4i32 V128:$dst), (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn)))]>;
6419 [(set (v2i64 V128:$dst), (OpNode (v2i64 V128:$Rd), (v2i64 V128:$Rn)))]>;
6426 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
6429 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
6432 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn)))]>;
6435 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
6438 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
6441 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
6444 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn)))]>;
6453 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
6456 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
6465 [(set (v8i8 V64:$Rd), (OpNode V64:$Rn))]>;
6468 [(set (v16i8 V128:$Rd), (OpNode V128:$Rn))]>;
6471 [(set (v4i16 V64:$Rd), (OpNode V64:$Rn))]>;
6474 [(set (v8i16 V128:$Rd), (OpNode V128:$Rn))]>;
6486 [(set (v4f16 V64:$Rd), (OpNode (v4f16 V64:$Rn)))]>;
6489 [(set (v8f16 V128:$Rd), (OpNode (v8f16 V128:$Rn)))]>;
6493 [(set (v2f32 V64:$Rd), (OpNode (v2f32 V64:$Rn)))]>;
6496 [(set (v4f32 V128:$Rd), (OpNode (v4f32 V128:$Rn)))]>;
6499 [(set (v2f64 V128:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
6514 [(set (v2f32 V64:$Rd), (OpNode (v2f32 V64:$Rn)))]>;
6517 [(set (v4f32 V128:$Rd), (OpNode (v4f32 V128:$Rn)))]>;
6520 [(set (v2f64 V128:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
6532 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
6535 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
6544 [(set (v4i16 V64:$Rd), (OpNode (v4f16 V64:$Rn)))]>;
6547 [(set (v8i16 V128:$Rd), (OpNode (v8f16 V128:$Rn)))]>;
6551 [(set (v2i32 V64:$Rd), (OpNode (v2f32 V64:$Rn)))]>;
6554 [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn)))]>;
6557 [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
6566 [(set (v4f16 V64:$Rd), (OpNode (v4i16 V64:$Rn)))]>;
6569 [(set (v8f16 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
6573 [(set (v2f32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
6576 [(set (v4f32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
6579 [(set (v2f64 V128:$Rd), (OpNode (v2i64 V128:$Rn)))]>;
6587 : I<(outs outreg:$Rd), (ins inreg:$Rn), asm,
6588 "{\t$Rd" # outkind # ", $Rn" # inkind #
6589 "|" # outkind # "\t$Rd, $Rn}", "", pattern>,
6591 bits<5> Rd;
6602 let Inst{4-0} = Rd;
6610 : I<(outs outreg:$dst), (ins outreg:$Rd, inreg:$Rn), asm,
6611 "{\t$Rd" # outkind # ", $Rn" # inkind #
6612 "|" # outkind # "\t$Rd, $Rn}", "$Rd = $dst", pattern>,
6614 bits<5> Rd;
6625 let Inst{4-0} = Rd;
6632 [(set (v8i8 V64:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
6637 [(set (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
6642 [(set (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn)))]>;
6646 def : Pat<(concat_vectors (v8i8 V64:$Rd), (OpNode (v8i16 V128:$Rn))),
6648 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
6649 def : Pat<(concat_vectors (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn))),
6651 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
6652 def : Pat<(concat_vectors (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn))),
6654 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
6671 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm,
6672 "{\t$Rd" # kind # ", $Rn" # kind # ", #" # zero #
6673 "|" # kind # "\t$Rd, $Rn, #" # zero # "}", "",
6674 [(set (dty regtype:$Rd), (OpNode (sty regtype:$Rn)))]>,
6676 bits<5> Rd;
6689 let Inst{4-0} = Rd;
6773 : I<(outs outtype:$Rd), (ins intype:$Rn), asm,
6774 !strconcat("\t$Rd", VdTy, ", $Rn", VnTy), "", pattern>,
6776 bits<5> Rd;
6787 let Inst{4-0} = Rd;
6795 : I<(outs outtype:$dst), (ins outtype:$Rd, intype:$Rn), asm,
6796 !strconcat("\t$Rd", VdTy, ", $Rn", VnTy), "$Rd = $dst", pattern>,
6798 bits<5> Rd;
6809 let Inst{4-0} = Rd;
6838 [(set (v2f32 V64:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
6842 def : Pat<(concat_vectors (v2f32 V64:$Rd), (OpNode (v2f64 V128:$Rn))),
6844 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
6857 : I<(outs outtype:$Rd), (ins intype1:$Rn, intype2:$Rm), asm,
6858 "{\t$Rd" # outkind # ", $Rn" # inkind1 # ", $Rm" # inkind2 #
6859 "|" # outkind # "\t$Rd, $Rn, $Rm}", "", pattern>,
6861 bits<5> Rd;
6874 let Inst{4-0} = Rd;
6883 : I<(outs outtype:$dst), (ins outtype:$Rd, intype1:$Rn, intype2:$Rm), asm,
6884 "{\t$Rd" # outkind # ", $Rn" # inkind1 # ", $Rm" # inkind2 #
6885 "|" # outkind # "\t$Rd, $Rn, $Rm}", "$Rd = $dst", pattern>,
6887 bits<5> Rd;
6900 let Inst{4-0} = Rd;
6912 [(set (v8i8 V64:$Rd), (IntOp (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
6920 [(set (v4i16 V64:$Rd), (IntOp (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
6928 [(set (v2i32 V64:$Rd), (IntOp (v2i64 V128:$Rn), (v2i64 V128:$Rm)))]>;
6937 def : Pat<(concat_vectors (v8i8 V64:$Rd), (IntOp (v8i16 V128:$Rn),
6940 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
6942 def : Pat<(concat_vectors (v4i16 V64:$Rd), (IntOp (v4i32 V128:$Rn),
6945 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
6947 def : Pat<(concat_vectors (v2i32 V64:$Rd), (IntOp (v2i64 V128:$Rn),
6950 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
6959 [(set (v8i16 V128:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
6967 [(set (v16i8 V128:$Rd), (OpNode (v1i64 V64:$Rn), (v1i64 V64:$Rm)))]>;
6971 [(set (v16i8 V128:$Rd), (OpNode (extract_high_v2i64 (v2i64 V128:$Rn)),
6985 [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
6989 [(set (v4i32 V128:$Rd), (OpNode (extract_high_v8i16 (v8i16 V128:$Rn)),
6994 [(set (v2i64 V128:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
6998 [(set (v2i64 V128:$Rd), (OpNode (extract_high_v4i32 (v4i32 V128:$Rn)),
7007 [(set (v8i16 V128:$Rd),
7012 [(set (v8i16 V128:$Rd),
7018 [(set (v4i32 V128:$Rd),
7023 [(set (v4i32 V128:$Rd),
7029 [(set (v2i64 V128:$Rd),
7034 [(set (v2i64 V128:$Rd),
7046 (add (v8i16 V128:$Rd),
7052 (add (v8i16 V128:$Rd),
7059 (add (v4i32 V128:$Rd),
7065 (add (v4i32 V128:$Rd),
7072 (add (v2i64 V128:$Rd),
7078 (add (v2i64 V128:$Rd),
7088 [(set (v8i16 V128:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
7092 [(set (v8i16 V128:$Rd), (OpNode (extract_high_v16i8 (v16i8 V128:$Rn)),
7097 [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
7101 [(set (v4i32 V128:$Rd), (OpNode (extract_high_v8i16 (v8i16 V128:$Rn)),
7106 [(set (v2i64 V128:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
7110 [(set (v2i64 V128:$Rd), (OpNode (extract_high_v4i32 (v4i32 V128:$Rn)),
7121 (OpNode (v8i16 V128:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
7126 (OpNode (v8i16 V128:$Rd),
7133 (OpNode (v4i32 V128:$Rd), (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
7138 (OpNode (v4i32 V128:$Rd),
7145 (OpNode (v2i64 V128:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
7150 (OpNode (v2i64 V128:$Rd),
7161 (Accum (v4i32 V128:$Rd),
7168 (Accum (v4i32 V128:$Rd),
7175 (Accum (v2i64 V128:$Rd),
7182 (Accum (v2i64 V128:$Rd),
7192 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i8 V64:$Rm)))]>;
7196 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn),
7201 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i16 V64:$Rm)))]>;
7205 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn),
7210 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (v2i32 V64:$Rm)))]>;
7214 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn),
7224 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, i32imm:$imm), asm,
7225 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind # ", $imm" #
7226 "|" # kind # "\t$Rd, $Rn, $Rm, $imm}", "",
7227 [(set (vty regtype:$Rd),
7230 bits<5> Rd;
7242 let Inst{4-0} = Rd;
7259 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm), asm,
7260 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind #
7261 "|" # kind # "\t$Rd, $Rn, $Rm}", "",
7262 [(set (valty regtype:$Rd), (OpNode regtype:$Rn, regtype:$Rm))]>,
7264 bits<5> Rd;
7277 let Inst{4-0} = Rd;
7321 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm), asm,
7322 "\t$Rd, $Rn, $Rm", "", pattern>,
7324 bits<5> Rd;
7335 let Inst{4-0} = Rd;
7342 : I<oops, iops, asm, "\t$Rd, $Rn, $Rm", "$Rd = $dst", pattern>,
7344 bits<5> Rd;
7356 let Inst{4-0} = Rd;
7362 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm)))]>;
7368 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm)))]>;
7382 [(set FPR32:$Rd, (OpNode FPR32:$Rn, FPR32:$Rm))]>;
7388 (ins FPR32:$Rd, FPR32:$Rn, FPR32:$Rm),
7391 (ins FPR16:$Rd, FPR16:$Rn, FPR16:$Rm),
7401 [(set (f64 FPR64:$Rd), (OpNode (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]>;
7403 [(set FPR32:$Rd, (OpNode FPR32:$Rn, FPR32:$Rm))]>;
7407 [(set (f16 FPR16:$Rd), (OpNode (f16 FPR16:$Rn), (f16 FPR16:$Rm)))]>;
7419 [(set (i64 FPR64:$Rd), (OpNode (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]>;
7421 [(set (i32 FPR32:$Rd), (OpNode (f32 FPR32:$Rn), (f32 FPR32:$Rm)))]>;
7435 "\t$Rd, $Rn, $Rm", cstr, pat>,
7437 bits<5> Rd;
7449 let Inst{4-0} = Rd;
7456 (outs FPR32:$Rd),
7459 (outs FPR64:$Rd),
7461 [(set (i64 FPR64:$Rd), (OpNode (i32 FPR32:$Rn), (i32 FPR32:$Rm)))]>;
7469 (ins FPR32:$Rd, FPR16:$Rn, FPR16:$Rm),
7470 asm, "$Rd = $dst", []>;
7473 (ins FPR64:$Rd, FPR32:$Rn, FPR32:$Rm),
7474 asm, "$Rd = $dst",
7476 (OpNode (i64 FPR64:$Rd), (i32 FPR32:$Rn), (i32 FPR32:$Rm)))]>;
7487 : I<(outs regtype:$Rd), (ins regtype2:$Rn), asm,
7488 "\t$Rd, $Rn", "", pat>,
7490 bits<5> Rd;
7502 let Inst{4-0} = Rd;
7509 : I<(outs regtype:$dst), (ins regtype:$Rd, regtype2:$Rn), asm,
7510 "\t$Rd, $Rn", "$Rd = $dst", pat>,
7512 bits<5> Rd;
7522 let Inst{4-0} = Rd;
7529 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm,
7530 "\t$Rd, $Rn, #" # zero, "", []>,
7532 bits<5> Rd;
7544 let Inst{4-0} = Rd;
7549 : I<(outs FPR32:$Rd), (ins FPR64:$Rn), asm, "\t$Rd, $Rn", "",
7550 [(set (f32 FPR32:$Rd), (AArch64fcvtxnsdr (f64 FPR64:$Rn)))]>,
7552 bits<5> Rd;
7558 let Inst{4-0} = Rd;
7579 def : InstAlias<asm # "\t$Rd, $Rn, #0",
7580 (!cast<Instruction>(NAME # v1i64rz) FPR64:$Rd, FPR64:$Rn), 0>;
7581 def : InstAlias<asm # "\t$Rd, $Rn, #0",
7582 (!cast<Instruction>(NAME # v1i32rz) FPR32:$Rd, FPR32:$Rn), 0>;
7584 def : InstAlias<asm # "\t$Rd, $Rn, #0",
7585 (!cast<Instruction>(NAME # v1i16rz) FPR16:$Rd, FPR16:$Rn), 0>;
7596 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn)))]>;
7620 [(set FPR64:$Rd, (OpNode (f64 FPR64:$Rn)))]>;
7622 [(set FPR32:$Rd, (OpNode (f32 FPR32:$Rn)))]>;
7626 [(set (f16 FPR16:$Rd), (OpNode (f16 FPR16:$Rn)))]>;
7634 [(set (i64 FPR64:$Rd), (OpNode (i64 FPR64:$Rn)))]>;
7636 [(set (i32 FPR32:$Rd), (OpNode (i32 FPR32:$Rn)))]>;
7649 [(set (i64 FPR64:$dst), (OpNode (i64 FPR64:$Rd), (i64 FPR64:$Rn)))]>;
7651 [(set (i32 FPR32:$dst), (OpNode (i32 FPR32:$Rd), (i32 FPR32:$Rn)))]>;
7656 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn))),
7657 (!cast<Instruction>(NAME # v1i64) FPR64:$Rd, FPR64:$Rn)>;
7666 [(set (f32 FPR32:$Rd), (OpNode (f64 FPR64:$Rn)))]>;
7679 : I<(outs regtype:$Rd), (ins vectype:$Rn), asm,
7680 "{\t$Rd, $Rn" # kind # "|" # kind # "\t$Rd, $Rn}", "", []>,
7682 bits<5> Rd;
7692 let Inst{4-0} = Rd;
7720 : I<(outs regtype:$Rd), (ins vectype:$Rn), asm,
7721 "{\t$Rd, $Rn" # kind # "|" # kind # "\t$Rd, $Rn}", "", pattern>,
7723 bits<5> Rd;
7734 let Inst{4-0} = Rd;
7770 [(set (f16 FPR16:$Rd), (intOp (v4f16 V64:$Rn)))]>;
7773 [(set (f16 FPR16:$Rd), (intOp (v8f16 V128:$Rn)))]>;
7777 [(set FPR32:$Rd, (intOp (v4f32 V128:$Rn)))]>;
7790 bits<5> Rd;
7799 let Inst{4-0} = Rd;
7804 : BaseSIMDInsDup<Q, 0, (outs vecreg:$Rd), (ins regtype:$Rn), "dup",
7805 "{\t$Rd" # size # ", $Rn" #
7806 "|" # size # "\t$Rd, $Rn}", "",
7807 [(set (vectype vecreg:$Rd), (AArch64dup regtype:$Rn))]> {
7816 : BaseSIMDInsDup<Q, 0, (outs vecreg:$Rd), (ins V128:$Rn, idxtype:$idx), "dup",
7817 "{\t$Rd" # dstkind # ", $Rn" # srckind # "$idx" #
7818 "|" # dstkind # "\t$Rd, $Rn$idx}", "",
7819 [(set (vectype vecreg:$Rd),
7861 : BaseSIMDInsDup<Q, 0, (outs regtype:$Rd), (ins V128:$Rn, idxtype:$idx), asm,
7862 "{\t$Rd, $Rn" # size # "$idx" #
7863 "|" # size # "\t$Rd, $Rn$idx}", "", pattern> {
7873 [(set regtype:$Rd, (vector_extract (vectype V128:$Rn), idxtype:$idx))]>;
7982 (ins V128:$Rd, idxtype:$idx, regtype:$Rn), "ins",
7983 "{\t$Rd" # size # "$idx, $Rn" #
7984 "|" # size # "\t$Rd$idx, $Rn}",
7985 "$Rd = $dst",
7987 (vector_insert (vectype V128:$Rd), regtype:$Rn, (i64 idxtype:$idx)))]> {
7994 (ins V128:$Rd, idxtype:$idx, V128:$Rn, idxtype:$idx2), "ins",
7995 "{\t$Rd" # size # "$idx, $Rn" # size # "$idx2" #
7996 "|" # size # "\t$Rd$idx, $Rn$idx2}",
7997 "$Rd = $dst",
8000 (vectype V128:$Rd),
8238 : I<(outs vectype:$Rd),
8240 asm, "\t$Rd" # kind # ", $Rn, $Rm$idx", "", []>,
8242 bits<5> Rd;
8255 let Inst{4-0} = Rd;
8355 bits<5> Rd;
8365 let Inst{4-0} = Rd;
8372 : BaseSIMDModifiedImm<Q, op, op2, (outs vectype:$Rd),
8374 "{\t$Rd" # kind # ", $imm8" # opt_shift #
8375 "|" # kind # "\t$Rd, $imm8" # opt_shift # "}",
8385 !con((ins vectype:$Rd, immtype:$imm8), opt_shift_iop),
8386 asm, "{\t$Rd" # kind # ", $imm8" # opt_shift #
8387 "|" # kind # "\t$Rd, $imm8" # opt_shift # "}",
8388 "$Rd = $dst", pattern> {
8461 [(set (v4i16 V64:$dst), (OpNode V64:$Rd,
8466 [(set (v8i16 V128:$dst), (OpNode V128:$Rd,
8472 [(set (v2i32 V64:$dst), (OpNode V64:$Rd,
8477 [(set (v4i32 V128:$dst), (OpNode V128:$Rd,
8504 : BaseSIMDModifiedImm<Q, op, 0, (outs FPR64:$Rd), (ins simdimmtype10:$imm8), asm,
8505 "\t$Rd, $imm8", "", pattern> {
8520 : I<(outs dst_reg:$Rd), (ins lhs_reg:$Rn, rhs_reg:$Rm, vec_idx:$idx),
8522 "{\t$Rd" # dst_kind # ", $Rn" # lhs_kind # ", $Rm" # rhs_kind # "$idx" #
8523 "|" # apple_kind # "\t$Rd, $Rn, $Rm$idx}", "", pattern>,
8525 bits<5> Rd;
8541 let Inst{4-0} = Rd;
8551 (ins dst_reg:$Rd, lhs_reg:$Rn, rhs_reg:$Rm, vec_idx:$idx), asm,
8552 "{\t$Rd" # dst_kind # ", $Rn" # lhs_kind # ", $Rm" # rhs_kind # "$idx" #
8553 "|" # apple_kind # "\t$Rd, $Rn, $Rm$idx}", "$Rd = $dst", pattern>,
8555 bits<5> Rd;
8571 let Inst{4-0} = Rd;
8584 (int_aarch64_neon_bfdot (AccumType RegType:$Rd),
8588 "{\t$Rd" # kind1 # ", $Rn" # kind2 #
8610 (AccumType RegType:$Rd),
8632 [(set (v4f32 V128:$dst), (OpNode (v4f32 V128:$Rd),
8635 let AsmString = !strconcat(asm, "{\t$Rd.4s, $Rn.8h, $Rm.8h}");
8641 (ins V128:$Rd, V128:$Rn, V128_lo:$Rm, VectorIndexH:$idx), asm,
8642 "{\t$Rd.4s, $Rn.8h, $Rm.h$idx}", "$Rd = $dst",
8644 (v4f32 (OpNode (v4f32 V128:$Rd),
8650 bits<5> Rd;
8664 let Inst{4-0} = Rd;
8671 (int_aarch64_neon_bfmmla (v4f32 V128:$Rd),
8674 let AsmString = !strconcat(asm, "{\t$Rd", ".4s", ", $Rn", ".8h",
8682 [(set (v8bf16 V128:$Rd),
8690 (int_aarch64_neon_bfcvtn2 (v8bf16 V128:$Rd), (v4f32 V128:$Rn)))]>;
8694 : I<(outs FPR16:$Rd), (ins FPR32:$Rn), asm, "\t$Rd, $Rn", "",
8695 [(set (bf16 FPR16:$Rd), (int_aarch64_neon_bfcvt (f32 FPR32:$Rn)))]>,
8697 bits<5> Rd;
8701 let Inst{4-0} = Rd;
8736 [(set (v4i32 V128:$dst), (OpNode (v4i32 V128:$Rd),
8739 let AsmString = asm # "{\t$Rd.4s, $Rn.16b, $Rm.16b}";
8752 (AccumType (OpNode (AccumType RegType:$Rd),
8788 (AccumType (OpNode (AccumType RegType:$Rd),
8825 [(set (v4f16 V64:$Rd),
8838 [(set (v8f16 V128:$Rd),
8852 [(set (v2f32 V64:$Rd),
8864 [(set (v4f32 V128:$Rd),
8876 [(set (v2f64 V128:$Rd),
8888 [(set (f16 FPR16Op:$Rd),
8902 [(set (f32 FPR32Op:$Rd),
8914 [(set (f64 FPR64Op:$Rd),
8950 def : Pat<(v8f16 (OpNode (v8f16 V128:$Rd), (v8f16 V128:$Rn),
8954 V128:$Rd, V128:$Rn, V128_lo:$Rm, VectorIndexH:$idx)>;
8955 def : Pat<(v8f16 (OpNode (v8f16 V128:$Rd), (v8f16 V128:$Rn),
8957 (!cast<Instruction>(INST # "v8i16_indexed") V128:$Rd, V128:$Rn,
8960 def : Pat<(v4f16 (OpNode (v4f16 V64:$Rd), (v4f16 V64:$Rn),
8964 V64:$Rd, V64:$Rn, V128_lo:$Rm, VectorIndexH:$idx)>;
8965 def : Pat<(v4f16 (OpNode (v4f16 V64:$Rd), (v4f16 V64:$Rn),
8967 (!cast<Instruction>(INST # "v4i16_indexed") V64:$Rd, V64:$Rn,
8970 def : Pat<(f16 (OpNode (f16 FPR16:$Rd), (f16 FPR16:$Rn),
8972 (!cast<Instruction>(INST # "v1i16_indexed") FPR16:$Rd, FPR16:$Rn,
8977 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
8981 V64:$Rd, V64:$Rn, V128:$Rm, VectorIndexS:$idx)>;
8982 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
8984 (!cast<Instruction>(INST # "v2i32_indexed") V64:$Rd, V64:$Rn,
8989 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
8993 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
8994 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
8996 (!cast<Instruction>(INST # "v4i32_indexed") V128:$Rd, V128:$Rn,
9000 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
9004 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
9005 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
9007 (!cast<Instruction>(INST # "v2i64_indexed") V128:$Rd, V128:$Rn,
9011 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
9013 (!cast<Instruction>(INST # "v1i32_indexed") FPR32:$Rd, FPR32:$Rn,
9017 def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn),
9019 (!cast<Instruction>(INST # "v1i64_indexed") FPR64:$Rd, FPR64:$Rn,
9163 [(set (v4i16 V64:$Rd),
9176 [(set (v8i16 V128:$Rd),
9189 [(set (v2i32 V64:$Rd),
9201 [(set (v4i32 V128:$Rd),
9221 [(set (i32 FPR32Op:$Rd),
9237 [(set (v4i16 V64:$Rd),
9250 [(set (v8i16 V128:$Rd),
9263 [(set (v2i32 V64:$Rd),
9275 [(set (v4i32 V128:$Rd),
9290 (OpNode (v4i16 V64:$Rd),(v4i16 V64:$Rn),
9303 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn),
9316 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn),
9328 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
9342 [(set (v4i32 V128:$Rd),
9355 [(set (v4i32 V128:$Rd),
9369 [(set (v2i64 V128:$Rd),
9381 [(set (v2i64 V128:$Rd),
9414 (Accum (v4i32 V128:$Rd),
9430 (Accum (v4i32 V128:$Rd),
9445 (Accum (v2i64 V128:$Rd),
9459 (Accum (v2i64 V128:$Rd),
9477 def : Pat<(i32 (Accum (i32 FPR32Op:$Rd),
9484 FPR32Op:$Rd,
9489 def : Pat<(i32 (Accum (i32 FPR32Op:$Rd),
9497 FPR32Op:$Rd,
9506 (Accum (i64 FPR64Op:$Rd),
9525 [(set (v4i32 V128:$Rd),
9538 [(set (v4i32 V128:$Rd),
9552 [(set (v2i64 V128:$Rd),
9564 [(set (v2i64 V128:$Rd),
9582 (OpNode (v4i32 V128:$Rd), (v4i16 V64:$Rn),
9595 (OpNode (v4i32 V128:$Rd),
9609 (OpNode (v2i64 V128:$Rd), (v2i32 V64:$Rn),
9621 (OpNode (v2i64 V128:$Rd),
9639 : I<(outs regtype1:$Rd), (ins regtype2:$Rn, immtype:$imm),
9640 asm, "\t$Rd, $Rn, $imm", "", pattern>,
9642 bits<5> Rd;
9652 let Inst{4-0} = Rd;
9659 : I<(outs regtype1:$dst), (ins regtype1:$Rd, regtype2:$Rn, immtype:$imm),
9660 asm, "\t$Rd, $Rn, $imm", "$Rd = $dst", pattern>,
9662 bits<5> Rd;
9672 let Inst{4-0} = Rd;
9697 [(set (i64 FPR64:$Rd),
9710 [(set (i64 FPR64:$dst), (OpNode (i64 FPR64:$Rd), (i64 FPR64:$Rn),
9715 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
9717 (!cast<Instruction>(NAME # "d") FPR64:$Rd, FPR64:$Rn,
9725 [(set (i64 FPR64:$Rd),
9757 [(set (i32 FPR32:$Rd), (OpNode (i64 FPR64:$Rn), vecshiftR32:$imm))]> {
9776 [(set (i32 FPR32:$Rd), (OpNode (i32 FPR32:$Rn), (i32 vecshiftL32:$imm)))]> {
9782 [(set (i64 FPR64:$Rd), (OpNode (i64 FPR64:$Rn), (i32 vecshiftL64:$imm)))]> {
9822 : I<(outs dst_reg:$Rd), (ins src_reg:$Rn, immtype:$imm),
9823 asm, "{\t$Rd" # dst_kind # ", $Rn" # src_kind # ", $imm" #
9824 "|" # dst_kind # "\t$Rd, $Rn, $imm}", "", pattern>,
9826 bits<5> Rd;
9836 let Inst{4-0} = Rd;
9845 : I<(outs vectype1:$dst), (ins vectype1:$Rd, vectype2:$Rn, immtype:$imm),
9846 asm, "{\t$Rd" # dst_kind # ", $Rn" # src_kind # ", $imm" #
9847 "|" # dst_kind # "\t$Rd, $Rn, $imm}", "$Rd = $dst", pattern>,
9849 bits<5> Rd;
9859 let Inst{4-0} = Rd;
9868 [(set (v4i16 V64:$Rd), (OpNode (v4f16 V64:$Rn), (i32 imm:$imm)))]> {
9876 [(set (v8i16 V128:$Rd), (OpNode (v8f16 V128:$Rn), (i32 imm:$imm)))]> {
9884 [(set (v2i32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (i32 imm:$imm)))]> {
9892 [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (i32 imm:$imm)))]> {
9900 [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (i32 imm:$imm)))]> {
9912 [(set (v4f16 V64:$Rd), (OpNode (v4i16 V64:$Rn), (i32 imm:$imm)))]> {
9920 [(set (v8f16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (i32 imm:$imm)))]> {
9929 [(set (v2f32 V64:$Rd), (OpNode (v2i32 V64:$Rn), (i32 imm:$imm)))]> {
9937 [(set (v4f32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (i32 imm:$imm)))]> {
9945 [(set (v2f64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (i32 imm:$imm)))]> {
9956 [(set (v8i8 V64:$Rd), (OpNode (v8i16 V128:$Rn), vecshiftR16Narrow:$imm))]> {
9972 [(set (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn), vecshiftR32Narrow:$imm))]> {
9988 [(set (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn), vecshiftR64Narrow:$imm))]> {
10006 def : Pat<(concat_vectors (v8i8 V64:$Rd),(OpNode (v8i16 V128:$Rn),
10009 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
10011 def : Pat<(concat_vectors (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn),
10014 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
10016 def : Pat<(concat_vectors (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn),
10019 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
10028 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn),
10037 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn),
10046 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn),
10055 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn),
10064 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn),
10073 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn),
10082 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn),
10094 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn),
10103 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn),
10112 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn),
10121 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn),
10130 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn),
10139 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn),
10148 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn),
10161 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn),
10170 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn),
10179 (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn),
10188 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn),
10197 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn),
10206 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
10215 (OpNode (v2i64 V128:$Rd), (v2i64 V128:$Rn),
10228 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn),
10238 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn),
10248 (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn),
10258 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn),
10268 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn),
10278 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
10288 (OpNode (v2i64 V128:$Rd), (v2i64 V128:$Rn),
10299 [(set (v8i16 V128:$Rd), (OpNode (v8i8 V64:$Rn), vecshiftL8:$imm))]> {
10307 [(set (v8i16 V128:$Rd),
10315 [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), vecshiftL16:$imm))]> {
10323 [(set (v4i32 V128:$Rd),
10332 [(set (v2i64 V128:$Rd), (OpNode (v2i32 V64:$Rn), vecshiftL32:$imm))]> {
10340 [(set (v2i64 V128:$Rd),
11213 (v4i16 (op (v4i16 V64:$Rd), (v4i16 V64:$Rn), (v4i16 V64:$Rm))))]>;
11216 (v8i16 (op (v8i16 V128:$Rd), (v8i16 V128:$Rn), (v8i16 V128:$Rm))))]>;
11219 (v2i32 (op (v2i32 V64:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm))))]>;
11222 (v4i32 (op (v4i32 V128:$Rd), (v4i32 V128:$Rn), (v4i32 V128:$Rm))))]>;
11231 (v4i16 (op (v4i16 V64:$Rd), (v4i16 V64:$Rn),
11244 (v8i16 (op (v8i16 V128:$Rd), (v8i16 V128:$Rn),
11257 (v2i32 (op (v2i32 V64:$Rd), (v2i32 V64:$Rn),
11268 (v4i32 (op (v4i32 V128:$Rd), (v4i32 V128:$Rn),
11290 (i32 (op (i32 FPR32Op:$Rd), (i32 FPR32Op:$Rn),
11328 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, rottype:$rot), asm,
11329 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind # ", $rot"
11330 "|" # kind # "\t$Rd, $Rn, $Rm, $rot}", "", pattern>,
11332 bits<5> Rd;
11349 let Inst{4-0} = Rd;
11358 [(set (v4f16 V64:$dst), (OpNode (v4f16 V64:$Rd),
11365 [(set (v8f16 V128:$dst), (OpNode (v8f16 V128:$Rd),
11374 [(set (v2f32 V64:$dst), (OpNode (v2f32 V64:$Rd),
11381 [(set (v4f32 V128:$dst), (OpNode (v4f32 V128:$Rd),
11388 [(set (v2f64 V128:$dst), (OpNode (v2f64 V128:$Rd),
11402 (ins regtype:$Rd, regtype:$Rn, regtype:$Rm, rottype:$rot), asm,
11403 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind # ", $rot"
11404 "|" # kind # "\t$Rd, $Rn, $Rm, $rot}", "$Rd = $dst", pattern>,
11406 bits<5> Rd;
11421 let Inst{4-0} = Rd;
11430 [(set (v4f16 V64:$dst), (OpNode (v4f16 V64:$Rd),
11437 [(set (v8f16 V128:$dst), (OpNode (v8f16 V128:$Rd),
11446 [(set (v2f32 V64:$dst), (OpNode (v2f32 V64:$Rd),
11453 [(set (v4f32 V128:$dst), (OpNode (v4f32 V128:$Rd),
11460 [(set (v2f64 V128:$dst), (OpNode (v2f64 V128:$Rd),
11476 (ins dst_reg:$Rd, lhs_reg:$Rn, rhs_reg:$Rm, vec_idx:$idx, rottype:$rot),
11478 "{\t$Rd" # dst_kind # ", $Rn" # lhs_kind # ", $Rm" # rhs_kind #
11480 "\t$Rd, $Rn, $Rm$idx, $rot}", "$Rd = $dst", pattern>,
11482 bits<5> Rd;
11501 let Inst{4-0} = Rd;
11545 : I<outs, ins, asm, "{\t$Rd.16b, $Rn.16b|.16b\t$Rd, $Rn}", cstr, pat>,
11547 bits<5> Rd;
11553 let Inst{4-0} = Rd;
11557 : AESBase<opc, asm, (outs V128:$Rd), (ins V128:$Rn), "",
11558 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
11561 : AESBase<opc, asm, (outs V128:$dst), (ins V128:$Rd, V128:$Rn),
11562 "$Rd = $dst",
11564 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn)))]>;
11570 "{\t$Rd" # dst_lhs_kind # ", $Rn" # dst_lhs_kind # ", $Rm.4s" #
11571 "|.4s\t$Rd, $Rn, $Rm}", "$Rd = $dst", pat>,
11573 bits<5> Rd;
11582 let Inst{4-0} = Rd;
11587 (ins FPR128:$Rd, FPR32:$Rn, V128:$Rm),
11589 (OpNode (v4i32 FPR128:$Rd), (i32 FPR32:$Rn),
11594 (ins V128:$Rd, V128:$Rn, V128:$Rm),
11596 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
11601 (ins FPR128:$Rd, FPR128:$Rn, V128:$Rm),
11603 (OpNode (v4i32 FPR128:$Rd), (v4i32 FPR128:$Rn),
11610 : I<oops, iops, asm, "{\t$Rd" # kind # ", $Rn" # kind #
11611 "|" # kind # "\t$Rd, $Rn}", cstr, pat>,
11613 bits<5> Rd;
11619 let Inst{4-0} = Rd;
11623 : SHA2OpInst<opc, asm, ".4s", "$Rd = $dst", (outs V128:$dst),
11624 (ins V128:$Rd, V128:$Rn),
11626 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn)))]>;
11629 : SHA2OpInst<opc, asm, "", "", (outs FPR32:$Rd), (ins FPR32:$Rn),
11630 [(set (i32 FPR32:$Rd), (OpNode (i32 FPR32:$Rn)))]>;
12023 (ins GPR64common:$Rd, GPR64common:$Rs, GPR64:$Rn),
12024 asm, "\t[$Rd]!, [$Rs]!, $Rn!",
12025 "$Rd = $Rd_wb,$Rs = $Rs_wb,$Rn = $Rn_wb", []>,
12027 bits<5> Rd;
12040 let Inst{4-0} = Rd;
12056 (ins GPR64common:$Rd, GPR64:$Rn, GPR64:$Rm),
12057 asm, "\t[$Rd]!, $Rn!, $Rm",
12058 "$Rd = $Rd_wb,$Rn = $Rn_wb", []>,
12060 bits<5> Rd;
12072 let Inst{4-0} = Rd;
12148 : I<(outs regtype:$Rd), (ins regtype:$Rn, immtype:$imm),
12149 asm, "\t$Rd, $Rn, $imm", "",
12150 [(set regtype:$Rd, (OpNode regtype:$Rn, immtype:$imm))]> {
12151 bits<5> Rd;
12162 let Inst{4-0} = Rd;
12546 class BaseAddSubCPA<bit isSub, string asm> : I<(outs GPR64sp:$Rd),
12548 asm, "\t$Rd, $Rn, $Rm$shift_imm", "", []>, Sched<[]> {
12549 bits<5> Rd;
12560 let Inst{4-0} = Rd;
12565 : InstAlias<asm#"\t$Rd, $Rn, $Rm",
12566 (inst GPR64sp:$Rd, GPR64sp:$Rn, GPR64:$Rm, 0)>;