Lines Matching refs:Rd
34 // opcode Rd Rs1 constant (16)
37 // Rd <- Rs1 op constant
83 // A Jump is accomplished by `Rd' being `pc', and it has one shadow.
90 bits<5> Rd;
98 let Inst{27 - 23} = Rd;
112 // opcode Rd Rs1 Rs2 \ operation /
115 // `Rd <- Rs1 op Rs2' iff condition DDDI is true.
131 // instructions in *Note RI::). For the SELECT operation, Rd gets Rs1 if
145 // A Jump is accomplished by `Rd' being `pc', and it has one shadow.
150 bits<5> Rd;
158 let Inst{27 - 23} = Rd;
175 // opcode Rd Rs1 constant (16)
178 // Rd <- Memory(ea) (Load) see below for the
179 // Memory(ea) <- Rd (Store) definition of ea.
182 // Loads appear in Rd one cycle after this instruction executes. If the
183 // following instruction reads Rd, that instruction will be delayed by 1
195 // A Jump is accomplished by `Rd' being `pc', and it has *two* delay slots.
198 bits<5> Rd;
209 let Inst{27 - 23} = Rd;
225 // opcode Rd Rs1 Rs2 \ operation /
228 // Rd <- Memory(ea) (Load) see below for the
229 // Memory(ea) <- Rd (Store) definition of ea.
255 // A Jump is accomplished by `Rd' being `pc', and it has *two* delay slots.
259 bits<5> Rd;
271 let Inst{27 - 23} = Rd;
416 // opcode Rd addr 5msb's address 16 lsb's
419 // If S = 0 (LOAD): Rd <- Memory(address);
420 // If S = 1 (STORE): Memory(address) <- Rd
428 bits<5> Rd;
433 let Inst{27 - 23} = Rd;
447 // opcode Rd const 5msb's constant 16 lsb's
450 // Rd <- constant
456 bits<5> Rd;
461 let Inst{27 - 23} = Rd;
475 // opcode Rd Rs1 constant (10)
486 // before being loaded into Rd.
488 // before being loaded into Rd.
501 bits<5> Rd;
512 let Inst{27 - 23} = Rd;
530 // |1.1.0.1| Rd | Rs1 |F.-| . . . . | . . | . . . . | OP |
532 // opcode Rd Rs1
534 // Rd <- Perform action encoded in OP on Rs1
544 bits<5> Rd;
548 let Inst{27 - 23} = Rd;