Lines Matching refs:Rd

501   unsigned Rd = fieldFromInstruction(Insn, 0, 5);  in DecodeFMOVLaneInstruction()  local
507 Inst, Rd, Address, Decoder); in DecodeFMOVLaneInstruction()
512 Inst, Rd, Address, Decoder); in DecodeFMOVLaneInstruction()
604 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeThreeAddrSRegInstruction() local
632 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rd, Addr, in DecodeThreeAddrSRegInstruction()
656 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd, Addr, in DecodeThreeAddrSRegInstruction()
672 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeMoveImmInstruction() local
684 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rd, Addr, in DecodeMoveImmInstruction()
690 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd, Addr, in DecodeMoveImmInstruction()
1256 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeAddSubERegInstruction() local
1270 DecodeSimpleRegisterClass<AArch64::GPR32spRegClassID, 0, 32>(Inst, Rd, Addr, in DecodeAddSubERegInstruction()
1279 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rd, Addr, in DecodeAddSubERegInstruction()
1288 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rd, Addr, in DecodeAddSubERegInstruction()
1297 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd, Addr, in DecodeAddSubERegInstruction()
1306 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rd, Addr, in DecodeAddSubERegInstruction()
1315 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd, Addr, in DecodeAddSubERegInstruction()
1331 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeLogicalImmInstruction() local
1338 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd, Addr, in DecodeLogicalImmInstruction()
1342 Inst, Rd, Addr, Decoder); in DecodeLogicalImmInstruction()
1350 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rd, Addr, in DecodeLogicalImmInstruction()
1354 Inst, Rd, Addr, Decoder); in DecodeLogicalImmInstruction()
1368 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeModImmInstruction() local
1374 DecodeSimpleRegisterClass<AArch64::FPR64RegClassID, 0, 32>(Inst, Rd, Addr, in DecodeModImmInstruction()
1377 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(Inst, Rd, Addr, in DecodeModImmInstruction()
1409 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeModImmTiedInstruction() local
1415 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(Inst, Rd, Addr, in DecodeModImmTiedInstruction()
1417 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(Inst, Rd, Addr, in DecodeModImmTiedInstruction()
1429 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeAdrInstruction() local
1437 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd, Addr, in DecodeAdrInstruction()
1448 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeAddSubImmShift() local
1461 if (Rd == 31 && !S) in DecodeAddSubImmShift()
1463 Inst, Rd, Addr, Decoder); in DecodeAddSubImmShift()
1465 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd, Addr, in DecodeAddSubImmShift()
1470 if (Rd == 31 && !S) in DecodeAddSubImmShift()
1472 Inst, Rd, Addr, Decoder); in DecodeAddSubImmShift()
1474 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rd, Addr, in DecodeAddSubImmShift()
1688 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeCPYMemOpInstruction() local
1694 if (Rd == Rs || Rs == Rn || Rd == Rn) in DecodeCPYMemOpInstruction()
1700 Inst, Rd, Addr, Decoder) || in DecodeCPYMemOpInstruction()
1706 Inst, Rd, Addr, Decoder) || in DecodeCPYMemOpInstruction()
1719 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeSETMemOpInstruction() local
1725 if (Rd == Rm || Rm == Rn || Rd == Rn) in DecodeSETMemOpInstruction()
1731 Inst, Rd, Addr, Decoder) || in DecodeSETMemOpInstruction()
1735 Inst, Rd, Addr, Decoder) || in DecodeSETMemOpInstruction()