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Searched refs:BaseReg (Results 1 – 25 of 98) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FixupLEAs.cpp457 Register BaseReg = LeaI->getOperand(1 + X86::AddrBaseReg).getReg(); in checkRegUsage() local
468 if (TRI->regsOverlap(Reg, BaseReg)) { in checkRegUsage()
506 Register BaseReg = I->getOperand(1 + X86::AddrBaseReg).getReg(); in optLEAALU() local
509 BaseReg = TRI->getSubReg(BaseReg, X86::sub_32bit); in optLEAALU()
513 if (BaseReg == IndexReg) in optLEAALU()
515 std::swap(BaseReg, IndexReg); in optLEAALU()
518 if (BaseReg == IndexReg) in optLEAALU()
527 .addReg(BaseReg, KilledBase ? RegState::Kill : 0); in optLEAALU()
565 Register BaseReg = Base.getReg(); in optTwoAddrLEA() local
574 if (BaseReg) in optTwoAddrLEA()
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H A DX86InsertPrefetch.cpp82 Register BaseReg = MI.getOperand(Op + X86::AddrBaseReg).getReg(); in IsMemOpCompatibleWithPrefetch() local
84 return (BaseReg == 0 || in IsMemOpCompatibleWithPrefetch()
85 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) || in IsMemOpCompatibleWithPrefetch()
86 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg)) && in IsMemOpCompatibleWithPrefetch()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCRegisterInfo.cpp46 unsigned BaseReg = FrameReg; in replaceFrameIndex() local
51 .addReg(BaseReg) in replaceFrameIndex()
60 BaseReg = RS->FindUnusedReg(&ARC::GPR32RegClass); in replaceFrameIndex()
61 if (!BaseReg) { in replaceFrameIndex()
66 BaseReg = in replaceFrameIndex()
68 assert(BaseReg && "Register scavenging failed."); in replaceFrameIndex()
69 LLVM_DEBUG(dbgs() << "Scavenged register " << printReg(BaseReg, TRI) in replaceFrameIndex()
73 RS->setRegUsed(BaseReg); in replaceFrameIndex()
77 .addReg(BaseReg, RegState::Define) in replaceFrameIndex()
95 .addReg(BaseReg, KillState) in replaceFrameIndex()
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H A DARCOptAddrMode.cpp101 MachineOperand &Incr, unsigned BaseReg);
105 void fixPastUses(ArrayRef<MachineInstr *> Uses, unsigned BaseReg,
297 Register BaseReg = Ldst->getOperand(BasePos).getReg(); in canJoinInstructions() local
307 if (Add->getOperand(0).getReg() == StReg || BaseReg == StReg) { in canJoinInstructions()
315 for (MachineInstr &MI : MRI->use_nodbg_instructions(BaseReg)) { in canJoinInstructions()
353 MachineOperand &Incr, unsigned BaseReg) { in canFixPastUses() argument
459 Register BaseReg = Ldst.getOperand(BasePos).getReg(); in changeToAddrMode() local
473 Ldst.addOperand(MachineOperand::CreateReg(BaseReg, false)); in changeToAddrMode()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DLocalStackSlotAllocation.cpp290 static inline bool lookupCandidateBaseReg(Register BaseReg, int64_t BaseOffset, in lookupCandidateBaseReg() argument
298 return TRI->isFrameOffsetLegal(&MI, BaseReg, Offset); in lookupCandidateBaseReg()
362 Register BaseReg; in insertFrameReferenceRegisters() local
405 if (BaseReg.isValid() && in insertFrameReferenceRegisters()
406 lookupCandidateBaseReg(BaseReg, BaseOffset, FrameSizeAdjust, in insertFrameReferenceRegisters()
408 LLVM_DEBUG(dbgs() << " Reusing base register " << printReg(BaseReg) in insertFrameReferenceRegisters()
425 BaseReg, CandBaseOffset, FrameSizeAdjust, in insertFrameReferenceRegisters()
436 BaseReg = TRI->materializeFrameBaseRegister(Entry, FrameIdx, InstrOffset); in insertFrameReferenceRegisters()
440 << " into " << printReg(BaseReg, TRI) << '\n'); in insertFrameReferenceRegisters()
449 assert(BaseReg && "Unable to allocate virtual base register!"); in insertFrameReferenceRegisters()
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H A DImplicitNullChecks.cpp377 const Register BaseReg = AddrMode.BaseReg, ScaledReg = AddrMode.ScaledReg; in isSuitableMemoryOp() local
382 if (BaseReg != PointerReg && ScaledReg != PointerReg) in isSuitableMemoryOp()
388 if ((BaseReg && in isSuitableMemoryOp()
389 TRI->getRegSizeInBits(BaseReg, MRI) != PointerRegSizeInBits) || in isSuitableMemoryOp()
448 if (CalculateDisplacementFromAddrMode(BaseReg, 1)) in isSuitableMemoryOp()
458 if ((BaseReg && BaseReg != PointerReg && !BaseRegIsConstVal) || in isSuitableMemoryOp()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumbRegisterInfo.cpp124 const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, in emitThumbRegPlusImmInReg() argument
131 if (BaseReg == ARM::SP && in emitThumbRegPlusImmInReg()
143 (BaseReg != 0 && !isARMLowRegister(BaseReg)); in emitThumbRegPlusImmInReg()
155 assert(BaseReg == ARM::SP && "Unexpected!"); in emitThumbRegPlusImmInReg()
239 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill); in emitThumbRegPlusImmInReg()
241 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill); in emitThumbRegPlusImmInReg()
252 Register BaseReg, int NumBytes, in emitThumbRegPlusImmediate() argument
283 if (BaseReg == ARM::SP) { in emitThumbRegPlusImmediate()
295 if (BaseReg == ARM::SP) { in emitThumbRegPlusImmediate()
301 } else if (DestReg == BaseReg) { in emitThumbRegPlusImmediate()
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H A DThumb2InstrInfo.cpp314 Register BaseReg, int NumBytes, in emitT2RegPlusImmediate() argument
318 if (NumBytes == 0 && DestReg != BaseReg) { in emitT2RegPlusImmediate()
320 .addReg(BaseReg, RegState::Kill) in emitT2RegPlusImmediate()
330 if (DestReg != ARM::SP && DestReg != BaseReg && in emitT2RegPlusImmediate()
352 .addReg(BaseReg) in emitT2RegPlusImmediate()
364 .addReg(BaseReg) in emitT2RegPlusImmediate()
377 if (DestReg == ARM::SP && BaseReg != ARM::SP) { in emitT2RegPlusImmediate()
380 .addReg(BaseReg) in emitT2RegPlusImmediate()
383 BaseReg = ARM::SP; in emitT2RegPlusImmediate()
387 assert((DestReg != ARM::SP || BaseReg == ARM::SP) && in emitT2RegPlusImmediate()
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H A DARMBaseRegisterInfo.cpp710 Register BaseReg = MRI.createVirtualRegister(&ARM::GPRRegClass); in materializeFrameBaseRegister() local
711 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); in materializeFrameBaseRegister()
713 MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, MCID, BaseReg) in materializeFrameBaseRegister()
719 return BaseReg; in materializeFrameBaseRegister()
722 void ARMBaseRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg, in resolveFrameIndex() argument
741 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII); in resolveFrameIndex()
744 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII, this); in resolveFrameIndex()
751 Register BaseReg, in isFrameOffsetLegal() argument
794 NumBits = (BaseReg == ARM::SP ? 8 : 5); in isFrameOffsetLegal()
H A DThumb2SizeReduction.cpp494 Register BaseReg = MI->getOperand(0).getReg(); in ReduceLoadStore() local
495 assert(isARMLowRegister(BaseReg)); in ReduceLoadStore()
501 if (MO.getReg() == BaseReg) { in ReduceLoadStore()
524 Register BaseReg = MI->getOperand(0).getReg(); in ReduceLoadStore() local
526 if (MO.getReg() == BaseReg) in ReduceLoadStore()
532 Register BaseReg = MI->getOperand(1).getReg(); in ReduceLoadStore() local
533 if (BaseReg != ARM::SP) in ReduceLoadStore()
545 Register BaseReg = MI->getOperand(1).getReg(); in ReduceLoadStore() local
546 if (BaseReg == ARM::SP && in ReduceLoadStore()
551 } else if (!isARMLowRegister(BaseReg) || in ReduceLoadStore()
/freebsd/contrib/llvm-project/llvm/include/llvm/BinaryFormat/
H A DSFrame.h75 enum class BaseReg : uint8_t { enum
134 BaseReg getBaseRegister() const { return static_cast<BaseReg>(Info & 1); }
145 void setBaseRegister(BaseReg Reg) {
148 void setFREInfo(bool RA, FREOffset Sz, uint8_t N, BaseReg Reg) {
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp442 MCRegister BaseReg, IndexReg, TmpReg; member in __anonee973c6c0111::X86AsmParser::IntelExprStateMachine
477 MCRegister getBaseReg() const { return BaseReg; } in getBaseReg()
695 if (!BaseReg) { in onPlus()
696 BaseReg = TmpReg; in onPlus()
754 if (!BaseReg) { in onMinus()
755 BaseReg = TmpReg; in onMinus()
999 if (!BaseReg) { in onRBrac()
1000 BaseReg = TmpReg; in onRBrac()
1064 if (!BaseReg) { in onRParen()
1065 BaseReg = TmpReg; in onRParen()
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H A DX86Operand.h65 MCRegister BaseReg; member
144 if (Mem.BaseReg) in print()
145 OS << ",BaseReg=" << X86IntelInstPrinter::getRegisterName(Mem.BaseReg); in print()
194 return Mem.BaseReg; in getMemBaseReg()
334 return isMem() && Mem.BaseReg != X86::RIP && Mem.BaseReg != X86::EIP; in isSibMem()
752 Res->Mem.BaseReg = MCRegister();
770 MCRegister BaseReg, MCRegister IndexReg, unsigned Scale,
778 assert((SegReg || BaseReg || IndexReg || DefaultBaseReg) &&
787 Res->Mem.BaseReg = BaseReg;
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DLoadStoreOpt.h41 Register BaseReg;
47 Register getBase() { return BaseReg; } in getBase()
48 Register getBase() const { return BaseReg; } in getBase()
51 void setBase(Register NewBase) { BaseReg = NewBase; } in setBase()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelDAGToDAG.cpp67 SDValue BaseReg; member
94 return BaseType == Base::FrameIndexBase || BaseReg.getNode() != nullptr; in hasBase()
100 return BaseType == Base::RegBase && BaseReg.getNode() != nullptr; in hasBaseReg()
138 if (auto *RegNode = dyn_cast_or_null<RegisterSDNode>(BaseReg.getNode())) in isPCRelative()
145 BaseReg = Reg; in setBaseReg()
155 if (BaseReg.getNode()) in dump()
156 BaseReg.getNode()->dump(); in dump()
428 AM.BaseReg = N; in matchAddressBase()
503 AM.BaseReg.getNode() == nullptr && doesDispFitFI(AM)) { in matchAddressRecursively()
559 AM.BaseReg = N.getOperand(0); in matchADD()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64StorePairSuppress.cpp166 Register BaseReg = BaseOp->getReg(); in runOnMachineFunction() local
167 if (PrevBaseReg == BaseReg) { in runOnMachineFunction()
176 PrevBaseReg = BaseReg; in runOnMachineFunction()
H A DAArch64FalkorHWPFFix.cpp208 Register BaseReg; member
637 Register BaseReg = MI.getOperand(BaseRegIdx).getReg(); in getLoadInfo() local
638 if (BaseReg == AArch64::SP || BaseReg == AArch64::WSP) in getLoadInfo()
643 LI.BaseReg = BaseReg; in getLoadInfo()
654 unsigned Base = TRI->getEncodingValue(LI.BaseReg); in getTag()
748 NewLdI.BaseReg = ScratchReg; in runOnLoop()
765 .addReg(LdI.BaseReg) in runOnLoop()
778 TII->get(AArch64::ORRXrs), LdI.BaseReg) in runOnLoop()
H A DAArch64LoadStoreOptimizer.cpp200 unsigned BaseReg, int Offset);
1567 Register BaseReg = AArch64InstrInfo::getLdStBaseOp(LoadMI).getReg(); in findMatchingStore() local
1596 BaseReg == AArch64InstrInfo::getLdStBaseOp(MI).getReg() && in findMatchingStore()
1612 if (!ModifiedRegUnits.available(BaseReg)) in findMatchingStore()
1973 Register BaseReg = AArch64InstrInfo::getLdStBaseOp(FirstMI).getReg(); in findMatchingInsn() local
2044 if (BaseReg == MIBaseReg) { in findMatchingInsn()
2124 if (!ModifiedRegUnits.available(BaseReg)) in findMatchingInsn()
2219 if (!ModifiedRegUnits.available(BaseReg)) { in findMatchingInsn()
2363 Register BaseReg = AArch64InstrInfo::getLdStBaseOp(MemMI).getReg(); in mergeConstOffsetInsn() local
2371 .addUse(BaseReg) in mergeConstOffsetInsn()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLoadStoreOpt.cpp84 Register BaseReg; in getPointerInfo() local
85 if (!mi_match(Ptr, MRI, m_GPtrAdd(m_Reg(BaseReg), m_Reg(PtrAddRHS)))) { in getPointerInfo()
90 Info.setBase(BaseReg); in getPointerInfo()
201 Register BaseReg; in instMayAlias() local
205 m_GPtrAdd(m_Reg(BaseReg), m_ICst(Offset)))) { in instMayAlias()
206 BaseReg = LS->getPointerReg(); in instMayAlias()
211 return {LS->isVolatile(), LS->isAtomic(), BaseReg, in instMayAlias()
739 Register BaseReg; in mergeTruncStore() local
742 m_GPtrAdd(m_Reg(BaseReg), m_ICst(LastOffset)))) { in mergeTruncStore()
743 BaseReg = LastStore.getPointerReg(); in mergeTruncStore()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/AsmParser/
H A DLanaiAsmParser.cpp128 MCRegister BaseReg; member
170 return Mem.BaseReg; in getMemBaseReg()
613 Op->Mem.BaseReg = MCRegister(); in MorphToMemImm()
621 MorphToMemRegReg(MCRegister BaseReg, std::unique_ptr<LanaiOperand> Op, in MorphToMemRegReg()
625 Op->Mem.BaseReg = BaseReg; in MorphToMemRegReg()
633 MorphToMemRegImm(MCRegister BaseReg, std::unique_ptr<LanaiOperand> Op, in MorphToMemRegImm()
637 Op->Mem.BaseReg = BaseReg; in MorphToMemRegImm()
901 MCRegister BaseReg; in parseMemoryOperand() local
955 BaseReg = Op->getReg(); in parseMemoryOperand()
981 if (!BaseReg || Lexer.isNot(AsmToken::RBrac)) in parseMemoryOperand()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonGenMemAbsolute.cpp133 unsigned BaseReg = BaseOp->getReg(); in runOnMachineFunction() local
134 if ((DstReg != BaseReg) || (Offset != 0)) in runOnMachineFunction()
146 if (LoadStoreReg == BaseReg) in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelDAGToDAG.cpp28 bool SelectGlobalValueVariableOffset(SDValue Addr, SDValue &BaseReg,
91 SDValue &BaseReg, in SelectGlobalValueVariableOffset() argument
94 BaseReg = Addr; in SelectGlobalValueVariableOffset()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVLoadStoreOptimizer.cpp229 Register BaseReg = FirstMI.getOperand(1).getReg(); in findMatchingInsn() local
257 if (BaseReg == MIBaseReg) { in findMatchingInsn()
277 if (!ModifiedRegUnits.available(BaseReg)) in findMatchingInsn()
321 if (!ModifiedRegUnits.available(BaseReg)) in findMatchingInsn()
H A DRISCVRegisterInfo.h98 bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
104 void resolveFrameIndex(MachineInstr &MI, Register BaseReg,
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCTargetDesc.h49 auto BaseReg = MI.getOperand(0).getReg(); in isLDMBaseRegInList() local
52 if (Op.isReg() && Op.getReg() == BaseReg) in isLDMBaseRegInList()

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