437     unsigned BaseReg = 0, IndexReg = 0, TmpReg = 0, Scale = 0;  member in __anonee973c6c0111::X86AsmParser::IntelExprStateMachine
471     unsigned getBaseReg() const { return BaseReg; }  in getBaseReg()
689           if (!BaseReg) {  in onPlus()
690             BaseReg = TmpReg;  in onPlus()
748           if (!BaseReg) {  in onMinus()
749             BaseReg = TmpReg;  in onMinus()
993           if (!BaseReg) {  in onRBrac()
994             BaseReg = TmpReg;  in onRBrac()
1155                                unsigned BaseReg, unsigned IndexReg,
1303 static bool CheckBaseRegAndIndexRegAndScale(unsigned BaseReg, unsigned IndexReg,  in CheckBaseRegAndIndexRegAndScale()  argument
1310   if (BaseReg != 0 &&  in CheckBaseRegAndIndexRegAndScale()
1311       !(BaseReg == X86::RIP || BaseReg == X86::EIP ||  in CheckBaseRegAndIndexRegAndScale()
1312         X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) ||  in CheckBaseRegAndIndexRegAndScale()
1313         X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg) ||  in CheckBaseRegAndIndexRegAndScale()
1314         X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg))) {  in CheckBaseRegAndIndexRegAndScale()
1331   if (((BaseReg == X86::RIP || BaseReg == X86::EIP) && IndexReg != 0) ||  in CheckBaseRegAndIndexRegAndScale()
1340   if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) &&  in CheckBaseRegAndIndexRegAndScale()
1341       (Is64BitMode || (BaseReg != X86::BX && BaseReg != X86::BP &&  in CheckBaseRegAndIndexRegAndScale()
1342                        BaseReg != X86::SI && BaseReg != X86::DI))) {  in CheckBaseRegAndIndexRegAndScale()
1347   if (BaseReg == 0 &&  in CheckBaseRegAndIndexRegAndScale()
1353   if (BaseReg != 0 && IndexReg != 0) {  in CheckBaseRegAndIndexRegAndScale()
1354     if (X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) &&  in CheckBaseRegAndIndexRegAndScale()
1361     if (X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg) &&  in CheckBaseRegAndIndexRegAndScale()
1368     if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg)) {  in CheckBaseRegAndIndexRegAndScale()
1374       if ((BaseReg != X86::BX && BaseReg != X86::BP) ||  in CheckBaseRegAndIndexRegAndScale()
1383   if (!Is64BitMode && BaseReg != 0 &&  in CheckBaseRegAndIndexRegAndScale()
1384       (BaseReg == X86::RIP || BaseReg == X86::EIP)) {  in CheckBaseRegAndIndexRegAndScale()
1693         unsigned OrigReg = OrigOp.Mem.BaseReg;  in VerifyAndAdjustOperands()
1694         unsigned FinalReg = FinalOp.Mem.BaseReg;  in VerifyAndAdjustOperands()
1728         FinalOp.Mem.BaseReg = FinalReg;  in VerifyAndAdjustOperands()
1757                                            unsigned BaseReg, unsigned IndexReg,  in CreateMemForMSInlineAsm()  argument
1788     if (BaseReg || IndexReg) {  in CreateMemForMSInlineAsm()
1791                                                BaseReg && IndexReg));  in CreateMemForMSInlineAsm()
1795       BaseReg = 1; // Make isAbsMem() false  in CreateMemForMSInlineAsm()
1798       getPointerWidth(), SegReg, Disp, BaseReg, IndexReg, Scale, Start, End,  in CreateMemForMSInlineAsm()
2654   unsigned BaseReg = SM.getBaseReg();  in parseIntelOperand()  local
2656   if (IndexReg && BaseReg == X86::RIP)  in parseIntelOperand()
2657     BaseReg = 0;  in parseIntelOperand()
2662   if (Scale == 0 && BaseReg != X86::ESP && BaseReg != X86::RSP &&  in parseIntelOperand()
2664     std::swap(BaseReg, IndexReg);  in parseIntelOperand()
2672       (X86MCRegisterClasses[X86::VR128XRegClassID].contains(BaseReg) ||  in parseIntelOperand()
2673        X86MCRegisterClasses[X86::VR256XRegClassID].contains(BaseReg) ||  in parseIntelOperand()
2674        X86MCRegisterClasses[X86::VR512RegClassID].contains(BaseReg)))  in parseIntelOperand()
2675     std::swap(BaseReg, IndexReg);  in parseIntelOperand()
2688   if ((BaseReg == X86::SI || BaseReg == X86::DI) &&  in parseIntelOperand()
2690     std::swap(BaseReg, IndexReg);  in parseIntelOperand()
2692   if ((BaseReg || IndexReg) &&  in parseIntelOperand()
2693       CheckBaseRegAndIndexRegAndScale(BaseReg, IndexReg, Scale, is64BitMode(),  in parseIntelOperand()
2699     return CreateMemForMSInlineAsm(RegNo, Disp, BaseReg, IndexReg, Scale,  in parseIntelOperand()
2719       } else if (!BaseReg && !IndexReg && Disp &&  in parseIntelOperand()
2741   if ((BaseReg || IndexReg || RegNo || DefaultBaseReg != X86::NoRegister))  in parseIntelOperand()
2743         getPointerWidth(), RegNo, Disp, BaseReg, IndexReg, Scale, Start, End,  in parseIntelOperand()
3044   unsigned BaseReg = 0, IndexReg = 0, Scale = 1;  in ParseMemOperand()  local
3056     BaseReg = cast<X86MCExpr>(E)->getRegNo();  in ParseMemOperand()
3057     if (BaseReg == X86::EIZ || BaseReg == X86::RIZ)  in ParseMemOperand()
3085         if (BaseReg == X86::RIP)  in ParseMemOperand()
3103             if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) &&  in ParseMemOperand()
3121   if (BaseReg == X86::DX && IndexReg == 0 && Scale == 1 && SegReg == 0 &&  in ParseMemOperand()
3128   if (CheckBaseRegAndIndexRegAndScale(BaseReg, IndexReg, Scale, is64BitMode(),  in ParseMemOperand()
3137   if (BaseReg || IndexReg) {  in ParseMemOperand()
3140       bool Is64 = X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) ||  in ParseMemOperand()
3142       bool Is16 = X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg);  in ParseMemOperand()
3161   if (SegReg || BaseReg || IndexReg)  in ParseMemOperand()
3163                                              BaseReg, IndexReg, Scale, StartLoc,  in ParseMemOperand()