Lines Matching refs:BaseReg

458   Register BaseReg = LeaI->getOperand(1 + X86::AddrBaseReg).getReg();
469       if (TRI->regsOverlap(Reg, BaseReg)) {
507   Register BaseReg = I->getOperand(1 + X86::AddrBaseReg).getReg();
510     BaseReg = TRI->getSubReg(BaseReg, X86::sub_32bit);
514     if (BaseReg == IndexReg)
516     std::swap(BaseReg, IndexReg);
519   if (BaseReg == IndexReg)
528                .addReg(BaseReg, KilledBase ? RegState::Kill : 0);
566   Register BaseReg = Base.getReg();
575     if (BaseReg != 0)
576       BaseReg = TRI->getSubReg(BaseReg, X86::sub_32bit);
586   if (BaseReg != 0 && IndexReg != 0 && Disp.getImm() == 0 &&
587       (DestReg == BaseReg || DestReg == IndexReg)) {
589     if (DestReg != BaseReg)
590       std::swap(BaseReg, IndexReg);
595         .addReg(BaseReg).addReg(IndexReg)
600         .addReg(BaseReg).addReg(IndexReg);
602   } else if (DestReg == BaseReg && IndexReg == 0) {
617           .addReg(BaseReg).addReg(Base.getReg(), RegState::Implicit);
620           .addReg(BaseReg);
627           .addReg(BaseReg).addImm(Disp.getImm())
631           .addReg(BaseReg).addImm(Disp.getImm());
634   } else if (BaseReg != 0 && IndexReg != 0 && Disp.getImm() == 0) {
759   Register BaseReg = Base.getReg();
763     if (BaseReg != 0)
764       BaseReg = TRI->getSubReg(BaseReg, X86::sub_32bit);
770   bool IsInefficientBase = isInefficientLEAReg(BaseReg);
775   if (IsInefficientBase && DestReg == BaseReg && !IsScale1)
782   bool BaseOrIndexIsDst = DestReg == BaseReg || DestReg == IndexReg;
789   if (IsScale1 && BaseReg == IndexReg &&
811     if (DestReg != BaseReg)
812       std::swap(BaseReg, IndexReg);
817                   .addReg(BaseReg)
823                   .addReg(BaseReg)
869   assert(DestReg != BaseReg && "DestReg == BaseReg should be handled already!");
878     bool BIK = Base.isKill() && BaseReg != IndexReg;
879     TII->copyPhysReg(MBB, MI, MI.getDebugLoc(), DestReg, BaseReg, BIK);