1736                           bool RegDeadKill, bool RegUndef, unsigned BaseReg,  in InsertLDR_STR()  argument
1744       .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));  in InsertLDR_STR()
1753       .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));  in InsertLDR_STR()
1771   Register BaseReg = BaseOp.getReg();  in FixInvalidRegPairOp()  local
1779   bool Errata602117 = EvenReg == BaseReg &&  in FixInvalidRegPairOp()
1812         .addReg(BaseReg, getKillRegState(BaseKill))  in FixInvalidRegPairOp()
1820         .addReg(BaseReg, getKillRegState(BaseKill))  in FixInvalidRegPairOp()
1841     if (isLd && TRI->regsOverlap(EvenReg, BaseReg)) {  in FixInvalidRegPairOp()
1842       assert(!TRI->regsOverlap(OddReg, BaseReg));  in FixInvalidRegPairOp()
1844                     false, BaseReg, false, BaseUndef, Pred, PredReg, TII, MI);  in FixInvalidRegPairOp()
1846                     false, BaseReg, BaseKill, BaseUndef, Pred, PredReg, TII,  in FixInvalidRegPairOp()
1857       if (EvenReg == BaseReg)  in FixInvalidRegPairOp()
1860                     EvenUndef, BaseReg, false, BaseUndef, Pred, PredReg, TII,  in FixInvalidRegPairOp()
1863                     OddUndef, BaseReg, BaseKill, BaseUndef, Pred, PredReg, TII,  in FixInvalidRegPairOp()
2172                           Register &BaseReg, int &Offset, Register &PredReg,
2257     Register &FirstReg, Register &SecondReg, Register &BaseReg, int &Offset,  in CanFormLdStDWord()  argument
2317   BaseReg = Op0->getOperand(1).getReg();  in CanFormLdStDWord()
2417         Register BaseReg, PredReg;  in RescheduleOps()  local
2424                                              FirstReg, SecondReg, BaseReg,  in RescheduleOps()
2439               .addReg(BaseReg);  in RescheduleOps()
2453               .addReg(BaseReg);  in RescheduleOps()