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/freebsd/sys/dev/dpaa2/
H A Ddpaa2_ni_dpkg.h68 #define BIT(x) (1ul << (x)) macro
119 #define NH_FLD_ETH_DA BIT(0)
120 #define NH_FLD_ETH_SA BIT(1)
121 #define NH_FLD_ETH_LENGTH BIT(2)
122 #define NH_FLD_ETH_TYPE BIT(3)
123 #define NH_FLD_ETH_FINAL_CKSUM BIT(4)
124 #define NH_FLD_ETH_PADDING BIT(5)
125 #define NH_FLD_ETH_ALL_FIELDS (BIT(6) - 1)
128 #define NH_FLD_VLAN_VPRI BIT(0)
129 #define NH_FLD_VLAN_CFI BIT(1)
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/freebsd/sys/contrib/dev/rtw89/
H A Dreg.h9 #define B_AX_AUTOLOAD_SUS BIT(5)
13 #define B_AX_PWC_EV2EF_B15 BIT(15)
14 #define B_AX_PWC_EV2EF_B14 BIT(14)
15 #define B_AX_ISO_EB2CORE BIT(8)
18 #define B_AX_FEN_BB_GLB_RSTN BIT(1)
19 #define B_AX_FEN_BBRSTB BIT(0)
22 #define B_AX_SOP_ASWRM BIT(31)
23 #define B_AX_SOP_PWMM_DSWR BIT(29)
24 #define B_AX_XTAL_OFF_A_DIE BIT(22)
25 #define B_AX_DIS_WLBT_PDNSUSEN_SOPC BIT(1
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H A Dpci.h18 #define BAC_OOBS_SEL BIT(4)
20 #define B_BAC_EQ_SEL BIT(5)
22 #define B_PCIE_BIT_PSAVE BIT(15)
24 #define BAC_RX_TEST_EN BIT(6)
27 #define B_PCIE_BIT_PINOUT_DIS BIT(3)
32 #define B_PCIE_BIT_RD_SEL BIT(2)
48 #define B_AX_CLK_CALIB_EN BIT(12)
49 #define B_AX_CALIB_EN BIT(13)
54 #define B_AX_DBI_RFLAG BIT(17)
55 #define B_AX_DBI_WFLAG BIT(1
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/freebsd/sys/contrib/dev/rtw88/
H A Dreg.h9 #define BIT_FEN_EN_25_1 BIT(13)
10 #define BIT_FEN_ELDR BIT(12)
11 #define BIT_FEN_CPUEN BIT(2)
12 #define BIT_FEN_BB_GLB_RST BIT(1)
13 #define BIT_FEN_BB_RSTB BIT(0)
14 #define BIT_R_DIS_PRST BIT(6)
15 #define BIT_WLOCK_1C_B6 BIT(5)
17 #define BIT_PFM_WOWL BIT(3)
19 #define BIT_CPU_CLK_EN BIT(14)
22 #define BIT_ANA8M BIT(
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H A Dpci.h18 #define BIT_RST_TRXDMA_INTF BIT(20)
19 #define BIT_RX_TAG_EN BIT(15)
23 #define BIT_DBI_RFLAG BIT(17)
24 #define BIT_DBI_WFLAG BIT(16)
31 #define BIT_MDIO_WFLAG_V1 BIT(5)
32 #define RTW_PCI_MDIO_PG_SZ BIT(5)
38 #define BIT_CLKREQ_SW_EN BIT(4)
39 #define BIT_L1_SW_EN BIT(3)
40 #define BIT_CLKREQ_N_PAD BIT(0)
43 #define BIT_PCI_BCNQ_FLAG BIT(
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H A Dsdio.h31 #define REG_SDIO_HIMR_RX_REQUEST BIT(0)
32 #define REG_SDIO_HIMR_AVAL BIT(1)
33 #define REG_SDIO_HIMR_TXERR BIT(2)
34 #define REG_SDIO_HIMR_RXERR BIT(3)
35 #define REG_SDIO_HIMR_TXFOVW BIT(4)
36 #define REG_SDIO_HIMR_RXFOVW BIT(5)
37 #define REG_SDIO_HIMR_TXBCNOK BIT(6)
38 #define REG_SDIO_HIMR_TXBCNERR BIT(7)
39 #define REG_SDIO_HIMR_BCNERLY_INT BIT(16)
40 #define REG_SDIO_HIMR_C2HCMD BIT(17)
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/freebsd/sys/contrib/dev/athk/ath12k/
H A Drx_desc.h27 #define RX_MPDU_START_INFO0_FLOW_ID_TOEPLITZ BIT(7)
28 #define RX_MPDU_START_INFO0_PKT_SEL_FP_UCAST_DATA BIT(8)
29 #define RX_MPDU_START_INFO0_PKT_SEL_FP_MCAST_DATA BIT(9)
30 #define RX_MPDU_START_INFO0_PKT_SEL_FP_CTRL_BAR BIT(10)
33 #define RX_MPDU_START_INFO0_MCAST_ECHO_DROP_EN BIT(17)
34 #define RX_MPDU_START_INFO0_WDS_LEARN_DETECT_EN BIT(18)
35 #define RX_MPDU_START_INFO0_INTRA_BSS_CHECK_EN BIT(19)
36 #define RX_MPDU_START_INFO0_USE_PPE BIT(20)
37 #define RX_MPDU_START_INFO0_PPE_ROUTING_EN BIT(21)
41 #define RX_MPDU_START_INFO1_PRE_DELIM_ERR_WARN BIT(24)
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/freebsd/sys/contrib/dev/athk/ath11k/
H A Drx_desc.h88 #define RX_ATTENTION_INFO1_FIRST_MPDU BIT(0)
89 #define RX_ATTENTION_INFO1_RSVD_1A BIT(1)
90 #define RX_ATTENTION_INFO1_MCAST_BCAST BIT(2)
91 #define RX_ATTENTION_INFO1_AST_IDX_NOT_FOUND BIT(3)
92 #define RX_ATTENTION_INFO1_AST_IDX_TIMEDOUT BIT(4)
93 #define RX_ATTENTION_INFO1_POWER_MGMT BIT(5)
94 #define RX_ATTENTION_INFO1_NON_QOS BIT(6)
95 #define RX_ATTENTION_INFO1_NULL_DATA BIT(7)
96 #define RX_ATTENTION_INFO1_MGMT_TYPE BIT(8)
97 #define RX_ATTENTION_INFO1_CTRL_TYPE BIT(9)
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/freebsd/sys/contrib/dev/mediatek/mt76/
H A Dmt76_connac2_mac.h41 #define MT_TX_FREE_PAIR BIT(31)
50 #define MT_TXD1_LONG_FORMAT BIT(31)
51 #define MT_TXD1_TGID BIT(30)
53 #define MT_TXD1_AMSDU BIT(23)
58 #define MT_TXD1_ETH_802_3 BIT(15)
59 #define MT_TXD1_VTA BIT(10)
62 #define MT_TXD2_FIX_RATE BIT(31)
63 #define MT_TXD2_FIXED_RATE BIT(30)
67 #define MT_TXD2_HTC_VLD BIT(13)
68 #define MT_TXD2_DURATION BIT(12)
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H A Dmt76_connac3_mac.h28 #define MT_RXD0_MESH BIT(18)
29 #define MT_RXD0_MHCP BIT(19)
31 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
32 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
40 #define MT_RXD1_NORMAL_GROUP_1 BIT(16)
41 #define MT_RXD1_NORMAL_GROUP_2 BIT(17)
42 #define MT_RXD1_NORMAL_GROUP_3 BIT(18)
43 #define MT_RXD1_NORMAL_GROUP_4 BIT(19)
44 #define MT_RXD1_NORMAL_GROUP_5 BIT(20)
46 #define MT_RXD1_NORMAL_CM BIT(23)
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H A Dmt76x02_regs.h15 #define MT_CMB_CTRL_XTAL_RDY BIT(22)
16 #define MT_CMB_CTRL_PLL_LD BIT(23)
24 #define MT_EFUSE_CTRL_KICK BIT(30)
25 #define MT_EFUSE_CTRL_SEL BIT(31)
31 #define MT_COEXCFG0_COEX_EN BIT(0)
34 #define MT_WLAN_FUN_CTRL_WLAN_EN BIT(0)
35 #define MT_WLAN_FUN_CTRL_WLAN_CLK_EN BIT(1)
36 #define MT_WLAN_FUN_CTRL_WLAN_RESET_RF BIT(2)
43 #define MT_WLAN_FUN_CTRL_WLAN_RESET BIT(3) /* MT76x0 */
44 #define MT_WLAN_FUN_CTRL_CSR_F20M_CKEN BIT(3) /* MT76x2 */
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H A Dmt792x_regs.h12 #define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0)
13 #define MT_MCU_INT_EVENT_DMA_INIT BIT(1)
14 #define MT_MCU_INT_EVENT_SER_TRIGGER BIT(2)
15 #define MT_MCU_INT_EVENT_RESET_DONE BIT(3)
33 #define MT_TMAC_TCR0_TBTT_STOP_CTRL BIT(25)
48 #define MT_TMAC_CTCR0_INS_DDLMT_EN BIT(17)
49 #define MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN BIT(18)
59 #define MT_DMA_DCR0_RXD_G5_EN BIT(23)
78 #define MT_LPON_TCR_SW_WRITE BIT(0)
99 #define MT_MIB_TXDUR_EN BIT(8)
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/freebsd/sys/contrib/dev/mediatek/mt76/mt7603/
H A Dmac.h10 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
11 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
12 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
13 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
14 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
15 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
29 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
30 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)
34 #define MT_RXD1_NORMAL_BEACON_UC BIT(5)
35 #define MT_RXD1_NORMAL_BEACON_MC BIT(4)
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H A Dregs.h28 #define MT_INT_RX_DONE(_n) BIT(_n)
31 #define MT_INT_TX_DONE(_n) BIT((_n) + 4)
33 #define MT_INT_RX_COHERENT BIT(20)
34 #define MT_INT_TX_COHERENT BIT(21)
35 #define MT_INT_MAC_IRQ3 BIT(27)
37 #define MT_INT_MCU_CMD BIT(30)
40 #define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0)
41 #define MT_WPDMA_GLO_CFG_TX_DMA_BUSY BIT(1)
42 #define MT_WPDMA_GLO_CFG_RX_DMA_EN BIT(2)
43 #define MT_WPDMA_GLO_CFG_RX_DMA_BUSY BIT(3)
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/freebsd/sys/dev/qat/qat_hw/qat_dh895xcc/
H A Dadf_dh895xcc_hw_data.h31 #define ADF_DH895XCC_ENABLE_AE_ECC_ERR BIT(28)
32 #define ADF_DH895XCC_ENABLE_AE_ECC_PARITY_CORR (BIT(24) | BIT(12))
35 #define ADF_DH895XCC_ERRSSMSH_EN BIT(3)
39 #define ADF_DH895XCC_PPERR_EN (BIT(2))
50 #define ADF_DH895XCC_ERRMSK0_CERR (BIT(24) | BIT(16) | BIT(8) | BIT(0))
51 #define ADF_DH895XCC_ERRMSK1_CERR (BIT(24) | BIT(16) | BIT(8) | BIT(0))
52 #define ADF_DH895XCC_ERRMSK3_CERR (BIT(7))
53 #define ADF_DH895XCC_ERRMSK4_CERR (BIT(24) | BIT(16) | BIT(8) | BIT(0))
57 #define ADF_DH895XCC_ERRMSK0_UERR (BIT(25) | BIT(17) | BIT(9) | BIT(1))
58 #define ADF_DH895XCC_ERRMSK1_UERR (BIT(25) | BIT(17) | BIT(9) | BIT(1))
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/freebsd/sys/contrib/dev/mediatek/mt76/mt7615/
H A Dmac.h15 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
16 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
17 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
18 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
19 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
20 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
25 #define MT_RXD1_MID_AMSDU_FRAME BIT(1)
26 #define MT_RXD1_LAST_AMSDU_FRAME BIT(0)
27 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
28 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)
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H A Dregs.h40 #define MT_TOP_3NSS BIT(24)
49 #define MT_TOP_MISC2_FW_PWR_ON BIT(1)
71 #define MT_HIF_LOGIC_RST_N BIT(4)
74 #define MT_PDMA_AXI_SLPPROT_ENABLE BIT(0)
75 #define MT_PDMA_AXI_SLPPROT_RDY BIT(16)
78 #define MT_PDMA_TX_IDX_BUSY BIT(2)
79 #define MT_PDMA_BUSY_IDX BIT(31)
93 #define MT_CFG_LPCR_HOST_FW_OWN BIT(0)
94 #define MT_CFG_LPCR_HOST_DRV_OWN BIT(1)
101 #define MT_MCU_INT_EVENT_PDMA_STOPPED BIT(0)
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/freebsd/sys/contrib/dev/athk/ath10k/
H A Drx_desc.h13 RX_ATTENTION_FLAGS_FIRST_MPDU = BIT(0),
14 RX_ATTENTION_FLAGS_LAST_MPDU = BIT(1),
15 RX_ATTENTION_FLAGS_MCAST_BCAST = BIT(2),
16 RX_ATTENTION_FLAGS_PEER_IDX_INVALID = BIT(3),
17 RX_ATTENTION_FLAGS_PEER_IDX_TIMEOUT = BIT(4),
18 RX_ATTENTION_FLAGS_POWER_MGMT = BIT(5),
19 RX_ATTENTION_FLAGS_NON_QOS = BIT(6),
20 RX_ATTENTION_FLAGS_NULL_DATA = BIT(7),
21 RX_ATTENTION_FLAGS_MGMT_TYPE = BIT(8),
22 RX_ATTENTION_FLAGS_CTRL_TYPE = BIT(9),
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/freebsd/sys/dev/qat/qat_hw/qat_c4xxx/
H A Dadf_c4xxx_hw_data.h32 #define ADF_C4XXX_FUSE_PROD_SKU_MASK BIT(31)
34 #define ADF_C4XXX_LEGFUSE_BASE_SKU_MASK (BIT(2) | BIT(3))
36 #define ADF_C4XXX_FUSE_DISABLE_INLINE_INGRESS BIT(12)
37 #define ADF_C4XXX_FUSE_DISABLE_INLINE_EGRESS BIT(13)
61 #define ADF_C4XXX_ENABLE_AE_ECC_ERR BIT(28)
62 #define ADF_C4XXX_ENABLE_AE_ECC_PARITY_CORR (BIT(24) | BIT(12))
64 #define ADF_C4XXX_UERRSSMSH_INTS_CLEAR_MASK (~BIT(0) ^ BIT(16))
66 #define ADF_C4XXX_CERRSSMSH_INTS_CLEAR_MASK (~BIT(0))
67 #define ADF_C4XXX_ERRSSMSH_EN BIT(3)
72 #define ADF_C4XXX_DOORBELL_INT_SRC BIT(10)
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H A Dadf_c4xxx_inline.h19 #define ADF_C4XXX_SADB_SIZE_BIT BIT(24)
39 #define ADF_C4XXX_STATS_REQUEST_ENABLED BIT(16)
40 #define ADF_C4XXX_STATS_REQUEST_DISABLED ~BIT(16)
45 #define ADF_C4XXX_MAC_STATS_READY BIT(0)
48 #define ADF_C4XXX_MAC_ERROR_TX_UNDERRUN BIT(6)
49 #define ADF_C4XXX_MAC_ERROR_TX_FCS BIT(7)
50 #define ADF_C4XXX_MAC_ERROR_TX_DATA_CORRUPT BIT(8)
51 #define ADF_C4XXX_MAC_ERROR_RX_OVERRUN BIT(9)
52 #define ADF_C4XXX_MAC_ERROR_RX_RUNT BIT(10)
53 #define ADF_C4XXX_MAC_ERROR_RX_UNDERSIZE BIT(11)
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/freebsd/contrib/wpa/src/common/
H A Dieee802_11_defs.h39 #define WLAN_GET_SEQ_FRAG(seq) ((seq) & (BIT(3) | BIT(2) | BIT(1) | BIT(0)))
41 (((seq) & (~(BIT(3) | BIT(2) | BIT(1) | BIT(0)))) >> 4)
105 #define WLAN_CAPABILITY_ESS BIT(0)
106 #define WLAN_CAPABILITY_IBSS BIT(1)
107 #define WLAN_CAPABILITY_CF_POLLABLE BIT(2)
108 #define WLAN_CAPABILITY_CF_POLL_REQUEST BIT(3)
109 #define WLAN_CAPABILITY_PRIVACY BIT(4)
110 #define WLAN_CAPABILITY_SHORT_PREAMBLE BIT(5)
111 #define WLAN_CAPABILITY_PBCC BIT(6)
112 #define WLAN_CAPABILITY_CHANNEL_AGILITY BIT(7)
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/freebsd/sys/dev/qat/qat_hw/qat_c62x/
H A Dadf_c62x_hw_data.h23 #define ADF_C62X_POWERGATE_PKE BIT(24)
24 #define ADF_C62X_POWERGATE_DC BIT(23)
29 #define ADF_C62X_ENABLE_AE_ECC_ERR BIT(28)
30 #define ADF_C62X_ENABLE_AE_ECC_PARITY_CORR (BIT(24) | BIT(12))
35 #define ADF_C62X_ERRSSMSH_EN (BIT(3))
37 #define ADF_C62X_PPERR_EN (BIT(2))
45 #define ADF_C62X_ERRMSK0_CERR (BIT(24) | BIT(16) | BIT(8) | BIT(0))
46 #define ADF_C62X_ERRMSK1_CERR (BIT(24) | BIT(16) | BIT(8) | BIT(0))
47 #define ADF_C62X_ERRMSK3_CERR (BIT(7))
48 #define ADF_C62X_ERRMSK4_CERR (BIT(8) | BIT(0))
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/freebsd/sys/dev/qat/qat_hw/qat_200xx/
H A Dadf_200xx_hw_data.h22 #define ADF_200XX_POWERGATE_PKE BIT(24)
23 #define ADF_200XX_POWERGATE_CY BIT(23)
30 #define ADF_200XX_ENABLE_AE_ECC_ERR BIT(28)
31 #define ADF_200XX_ENABLE_AE_ECC_PARITY_CORR (BIT(24) | BIT(12))
34 #define ADF_200XX_ERRSSMSH_EN BIT(3)
39 #define ADF_200XX_PPERR_EN (BIT(2))
47 #define ADF_200XX_ERRMSK0_CERR (BIT(24) | BIT(16) | BIT(8) | BIT(0))
48 #define ADF_200XX_ERRMSK1_CERR (BIT(8) | BIT(0))
52 #define ADF_200XX_ERRMSK0_UERR (BIT(25) | BIT(17) | BIT(9) | BIT(1))
53 #define ADF_200XX_ERRMSK1_UERR (BIT(9) | BIT(1))
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/freebsd/sys/dev/qat/qat_hw/qat_c3xxx/
H A Dadf_c3xxx_hw_data.h22 #define ADF_C3XXX_POWERGATE_PKE BIT(24)
23 #define ADF_C3XXX_POWERGATE_CY BIT(23)
28 #define ADF_C3XXX_ENABLE_AE_ECC_ERR BIT(28)
29 #define ADF_C3XXX_ENABLE_AE_ECC_PARITY_CORR (BIT(24) | BIT(12))
32 #define ADF_C3XXX_ERRSSMSH_EN BIT(3)
37 #define ADF_C3XXX_PPERR_EN (BIT(2))
45 #define ADF_C3XXX_ERRMSK0_CERR (BIT(24) | BIT(16) | BIT(8) | BIT(0))
46 #define ADF_C3XXX_ERRMSK1_CERR (BIT(8) | BIT(0))
50 #define ADF_C3XXX_ERRMSK0_UERR (BIT(25) | BIT(17) | BIT(9) | BIT(1))
51 #define ADF_C3XXX_ERRMSK1_UERR (BIT(9) | BIT(1))
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/freebsd/sys/dev/flash/flexspi/
H A Dflex_spi.h29 #define BIT(x) (1 << (x)) macro
35 #define FSPI_MCR0_LEARN_EN BIT(15)
36 #define FSPI_MCR0_SCRFRUN_EN BIT(14)
37 #define FSPI_MCR0_OCTCOMB_EN BIT(13)
38 #define FSPI_MCR0_DOZE_EN BIT(12)
39 #define FSPI_MCR0_HSEN BIT(11)
40 #define FSPI_MCR0_SERCLKDIV BIT(8)
41 #define FSPI_MCR0_ATDF_EN BIT(7)
42 #define FSPI_MCR0_ARDF_EN BIT(6)
45 #define FSPI_MCR0_MDIS BIT(1)
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