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Searched +full:tx +full:- +full:clk +full:- +full:delay +full:- +full:ps (Results 1 – 25 of 39) sorted by relevance

12

/linux/arch/riscv/boot/dts/starfive/
H A Djh7110-starfive-visionfive-2-v1.3b.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include "jh7110-starfive-visionfive-2.dtsi"
12 compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
16 starfive,tx-use-rgmii-clk;
17 assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
18 assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
22 starfive,tx-use-rgmii-clk;
23 assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>;
24 assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>;
[all …]
H A Djh7110-pine64-star64.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 /dts-v1/;
7 #include "jh7110-common.dtsi"
18 starfive,tx-use-rgmii-clk;
19 assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
20 assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
25 phy-handle = <&phy1>;
26 phy-mode = "rgmii-id";
27 starfive,tx-use-rgmii-clk;
28 assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>;
[all …]
H A Djh7110-milkv-mars.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 /dts-v1/;
7 #include "jh7110-common.dtsi"
10 model = "Milk-V Mars";
15 assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
16 assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
17 starfive,tx-use-rgmii-clk;
34 rx-internal-delay-ps = <1500>;
35 tx-internal-delay-ps = <1500>;
36 motorcomm,rx-clk-drv-microamp = <3970>;
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dmotorcomm,yt8xxx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Sae <frank.sae@motor-comm.com>
13 - $ref: ethernet-phy.yaml#
18 - ethernet-phy-id4f51.e91a
19 - ethernet-phy-id4f51.e91b
21 rx-internal-delay-ps:
23 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
24 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
[all …]
H A Dti,dp83869.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-phy.yaml#
14 - Andrew Davis <afd@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
23 the DP83869HM can run 1000BASE-X-to-1000BASE-T and 100BASE-FX-to-100BASE-TX
[all …]
H A Dmediatek-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/mediatek-dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Biao Huang <biao.huang@mediatek.com>
21 - mediatek,mt2712-gmac
22 - mediatek,mt8188-gmac
23 - mediatek,mt8195-gmac
25 - compatible
28 - $ref: snps,dwmac.yaml#
[all …]
H A Dingenic,mac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
18 - ingenic,jz4775-mac
19 - ingenic,x1000-mac
20 - ingenic,x1600-mac
21 - ingenic,x1830-mac
22 - ingenic,x2000-mac
30 interrupt-names:
[all …]
/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-meson8b.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
35 /* TX clock delay in ns = "8ns / 4 * tx_dly_val" (where 8ns are exactly one
36 * cycle of the 125MHz RGMII TX clock):
57 * the automatically delay and skew automatically (internally).
60 /* An internal counter based on the "timing-adjustment" clock. The counter is
62 * delay (= the counter value) when to start sampling RXEN and RXD[3:0].
66 * large input delay, the bit for that signal (RXEN = bit 0, RXD[3] = bit 1,
67 * ...) can be configured to be 1 to compensate for a delay of about 1ns.
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Dam335x-nano.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Newflow Ltd - https://www.newflow.co.uk/
5 /dts-v1/;
15 cpu0-supply = <&dcdc2_reg>;
25 compatible = "gpio-leds";
30 default-state = "off";
36 pinctrl-names = "default";
37 pinctrl-0 = <&misc_pins>;
39 misc_pins: misc-pins {
40 pinctrl-single,pins = <
[all …]
H A Dam335x-evm.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/irq.h>
12 compatible = "ti,am335x-evm", "ti,am33xx";
16 cpu0-supply = <&vdd1_reg>;
26 stdout-path = &uart0;
30 compatible = "regulator-fixed";
31 regulator-name = "vbat";
32 regulator-min-microvolt = <5000000>;
[all …]
H A Ddra72-evm-common.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
8 #include "dra7-ipu-dsp-common.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/clock/ti-dra7-atl.h>
13 compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
20 stdout-path = &uart1;
23 evm_12v0: fixedregulator-evm12v0 {
25 compatible = "regulator-fixed";
[all …]
/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-h618-orangepi-zero3.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "sun50i-h616-orangepi-zero.dtsi"
9 #include "sun50i-h616-cpu-opp.dtsi"
13 compatible = "xunlong,orangepi-zero3", "allwinner,sun50i-h618";
17 cpu-supply = <&reg_dcdc2>;
21 allwinner,tx-delay-ps = <700>;
22 phy-mode = "rgmii-rxid";
23 phy-supply = <&reg_dldo1>;
27 motorcomm,clk-out-frequency-hz = <125000000>;
[all …]
/linux/arch/arm/boot/dts/st/
H A Dstm32mp15xx-dhcor-avenger96.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
3 * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
9 #include "stm32mp15xx-dhcor-io1v8.dtsi"
22 cec_clock: clk-cec-fixed {
23 #clock-cells = <0>;
24 compatible = "fixed-clock";
25 clock-frequency = <24000000>;
29 stdout-path = "serial0:115200n8";
32 hdmi-out {
33 compatible = "hdmi-connector";
[all …]
/linux/drivers/net/phy/
H A Dmicrel.c1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright (c) 2010-2013 Micrel, Inc.
29 #include <linux/clk.h>
30 #include <linux/delay.h>
129 * The value is calculated as following: (1/1000000)/((2^-32)/4)
135 * The value is calculated as following: (1/1000000)/((2^-32)/8)
365 /* Delay used to get the second part from the LTC */
446 struct clk *clk; member
554 const struct kszphy_type *type = phydev->drv->driver_data; in kszphy_config_intr()
558 if (type && type->interrupt_level_mask) in kszphy_config_intr()
[all …]
/linux/arch/arm64/boot/dts/renesas/
H A Dwhite-hawk-cpu-common.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/leds/common.h>
27 stdout-path = "serial0:921600n8";
30 sn65dsi86_refclk: clk-x6 {
31 compatible = "fixed-clock";
32 #clock-cells = <0>;
33 clock-frequency = <38400000>;
37 compatible = "gpio-keys";
[all …]
H A Dgray-hawk-single.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
6 * Copyright (C) 2024-2025 Glider bv
11 * Because R-Car V4M has only 1 SSI, it cannot handle both Playback/Capture
28 #include <dt-bindings/gpio/gpio.h>
29 #include <dt-bindings/input/input.h>
30 #include <dt-bindings/leds/common.h>
31 #include <dt-bindings/media/video-interfaces.h>
35 compatible = "renesas,gray-hawk-single";
49 can_transceiver0: can-phy0 {
51 #phy-cells = <0>;
[all …]
H A Dulcb.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car Gen3 ULCB board
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/input/input.h>
18 model = "Renesas R-Car Gen3 ULCB board";
37 stdout-path = "serial0:115200n8";
40 audio_clkout: audio-clkout {
43 * but needed to avoid cs2000/rcar_sound probe dead-lock
45 compatible = "fixed-clock";
46 #clock-cells = <0>;
[all …]
H A Ddraak.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2018 Renesas Electronics Corp.
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
21 audio_clkout: audio-clkout {
24 * but needed to avoid cs2000/rcar_sound probe dead-lock
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <12288000>;
32 compatible = "pwm-backlight";
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mm-venice-gw7903.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h>
17 compatible = "gw,imx8mm-gw7903", "fsl,imx8mm";
27 stdout-path = &uart2;
35 gpio-keys {
36 compatible = "gpio-keys";
[all …]
H A Dimx8mp-skov-reva.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 #include "imx8mp-nominal.dtsi"
6 #include <dt-bindings/leds/common.h>
27 compatible = "pwm-backlight";
28 pinctrl-0 = <&pinctrl_backlight>;
30 power-supply = <&reg_24v>;
31 enable-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
32 brightness-levels = <0 255>;
33 num-interpolated-steps = <17>;
34 default-brightness-level = <8>;
[all …]
/linux/drivers/phy/amlogic/
H A Dphy-meson-axg-mipi-dphy.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/clk.h>
14 #include <linux/delay.h>
33 * [11] mipi divider clk selection.
52 /* [31] clk lane tx_hs_en control selection.
53 * 1: from register. 0: use clk lane state machine.
55 * [29] clk lane tx_lp_en contrl selection.
56 * 1: from register. 0: from clk lane state machine.
88 * [4] clk chan power down. this bit is also used as the power down
101 * [20:17] clk lane state. {mbias_ready, tx_stop, tx_ulps, tx_hs_active}
[all …]
/linux/drivers/net/ethernet/renesas/
H A Dravb_main.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2014-2019 Renesas Electronics Corporation
6 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/dma-mapping.h>
58 return -ETIMEDOUT; in ravb_wait()
90 switch (priv->speed) { in ravb_set_rate_gbeth()
107 switch (priv->speed) { in ravb_set_rate_rcar()
148 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0); in ravb_mdio_ctrl()
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8395-genio-1200-evk.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
15 #include <dt-bindings/regulator/mediatek,mt6360-regulator.h>
16 #include <dt-bindings/spmi/spmi.h>
17 #include <dt-bindings/usb/pd.h>
20 model = "MediaTek Genio 1200 EVK-P1V2-EMMC";
[all …]
/linux/drivers/net/ethernet/freescale/
H A Dfec_main.c1 // SPDX-License-Identifier: GPL-2.0+
17 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
20 * Copyright (c) 2004-2006 Macq Electronique SA.
22 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
29 #include <linux/clk.h>
31 #include <linux/delay.h>
194 { .compatible = "fsl,imx25-fec", .data = &fec_imx25_info, },
195 { .compatible = "fsl,imx27-fec", .data = &fec_imx27_info, },
196 { .compatible = "fsl,imx28-fec", .data = &fec_imx28_info, },
197 { .compatible = "fsl,imx6q-fec", .data = &fec_imx6q_info, },
[all …]
/linux/drivers/net/can/
H A Dxilinx_can.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2012 - 2022 Xilinx, Inc.
6 * Copyright (C) 2017 - 2018 Sandvik Mining and Construction Oy
9 * This driver is developed for AXI CAN IP, AXI CANFD IP, CANPS and CANFD PS Controller.
13 #include <linux/clk.h>
52 XCAN_TXFIFO_OFFSET = 0x30, /* TX FIFO base */
61 XCAN_TRR_OFFSET = 0x0090, /* TX Buffer Ready Request */
71 XCAN_TXMSG_BASE_OFFSET = 0x0100, /* TX Message Space */
92 /* the single TX mailbox used by this driver on CAN FD HW */
95 /* CAN register bit masks - XCAN_<REG>_<BIT>_MASK */
[all …]

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