Lines Matching +full:tx +full:- +full:clk +full:- +full:delay +full:- +full:ps
1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-phy.yaml#
14 - Andrew Davis <afd@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
23 the DP83869HM can run 1000BASE-X-to-1000BASE-T and 100BASE-FX-to-100BASE-TX
34 ti,min-output-impedance:
40 ti,max-output-impedance:
46 tx-fifo-depth:
49 Transmitt FIFO depth see dt-bindings/net/ti-dp83869.h for values
51 rx-fifo-depth:
54 Receive FIFO depth see dt-bindings/net/ti-dp83869.h for values
56 ti,clk-output-sel:
59 Muxing option for CLK_OUT pin see dt-bindings/net/ti-dp83869.h for values.
61 ti,op-mode:
65 mode is set by the straps. see dt-bindings/net/ti-dp83869.h for values
67 rx-internal-delay-ps:
68 description: Delay is in pico seconds
73 tx-internal-delay-ps:
74 description: Delay is in pico seconds
80 - reg
85 - |
86 #include <dt-bindings/net/ti-dp83869.h>
88 #address-cells = <1>;
89 #size-cells = <0>;
90 ethphy0: ethernet-phy@0 {
92 tx-fifo-depth = <DP83869_PHYCR_FIFO_DEPTH_4_B_NIB>;
93 rx-fifo-depth = <DP83869_PHYCR_FIFO_DEPTH_4_B_NIB>;
94 ti,op-mode = <DP83869_RGMII_COPPER_ETHERNET>;
95 ti,max-output-impedance;
96 ti,clk-output-sel = <DP83869_CLK_O_SEL_CHN_A_RCLK>;
97 rx-internal-delay-ps = <2000>;
98 tx-internal-delay-ps = <2000>;