xref: /linux/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts (revision a1ff5a7d78a036d6c2178ee5acd6ba4946243800)
1012af553SClément Péron// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2cabbaed7SClément Péron// Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.io>
3494d8367SIcenowy Zheng
4494d8367SIcenowy Zheng/dts-v1/;
5494d8367SIcenowy Zheng
6494d8367SIcenowy Zheng#include "sun50i-h6.dtsi"
7fe79ea57SClément Péron#include "sun50i-h6-cpu-opp.dtsi"
8494d8367SIcenowy Zheng
9494d8367SIcenowy Zheng#include <dt-bindings/gpio/gpio.h>
10494d8367SIcenowy Zheng
11494d8367SIcenowy Zheng/ {
12*523bfa30SDragan Simic	model = "Pine64 PINE H64 Model A";
13494d8367SIcenowy Zheng	compatible = "pine64,pine-h64", "allwinner,sun50i-h6";
14494d8367SIcenowy Zheng
15494d8367SIcenowy Zheng	aliases {
16729e1ffcSIcenowy Zheng		ethernet0 = &emac;
17494d8367SIcenowy Zheng		serial0 = &uart0;
18e757bdd0SAndre Przywara		spi0 = &spi0;
19494d8367SIcenowy Zheng	};
20494d8367SIcenowy Zheng
21494d8367SIcenowy Zheng	chosen {
22494d8367SIcenowy Zheng		stdout-path = "serial0:115200n8";
23494d8367SIcenowy Zheng	};
246677bbdeSChen-Yu Tsai
255dfdedf0SKrzysztof Kozlowski	ext_osc32k: ext-osc32k-clk {
2632507b86SJernej Skrabec		#clock-cells = <0>;
2732507b86SJernej Skrabec		compatible = "fixed-clock";
2832507b86SJernej Skrabec		clock-frequency = <32768>;
2932507b86SJernej Skrabec		clock-output-names = "ext_osc32k";
3032507b86SJernej Skrabec	};
3132507b86SJernej Skrabec
3224e9f61cSCorentin Labbe	hdmi_connector: connector {
337d5bca1cSJernej Skrabec		compatible = "hdmi-connector";
347d5bca1cSJernej Skrabec		type = "a";
3524e9f61cSCorentin Labbe		ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */
367d5bca1cSJernej Skrabec
377d5bca1cSJernej Skrabec		port {
387d5bca1cSJernej Skrabec			hdmi_con_in: endpoint {
397d5bca1cSJernej Skrabec				remote-endpoint = <&hdmi_out_con>;
407d5bca1cSJernej Skrabec			};
417d5bca1cSJernej Skrabec		};
427d5bca1cSJernej Skrabec	};
437d5bca1cSJernej Skrabec
446677bbdeSChen-Yu Tsai	leds {
456677bbdeSChen-Yu Tsai		compatible = "gpio-leds";
466677bbdeSChen-Yu Tsai
47e299e6ddSMaxime Ripard		led-0 {
486677bbdeSChen-Yu Tsai			label = "pine-h64:green:heartbeat";
496677bbdeSChen-Yu Tsai			gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */
506677bbdeSChen-Yu Tsai		};
516677bbdeSChen-Yu Tsai
52e299e6ddSMaxime Ripard		led-1 {
536677bbdeSChen-Yu Tsai			label = "pine-h64:white:link";
546677bbdeSChen-Yu Tsai			gpios = <&r_pio 0 3 GPIO_ACTIVE_HIGH>; /* PL3 */
556677bbdeSChen-Yu Tsai		};
566677bbdeSChen-Yu Tsai
57e299e6ddSMaxime Ripard		led-2 {
586677bbdeSChen-Yu Tsai			label = "pine-h64:blue:status";
596677bbdeSChen-Yu Tsai			gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */
606677bbdeSChen-Yu Tsai		};
616677bbdeSChen-Yu Tsai	};
6244eb589cSIcenowy Zheng
6324e9f61cSCorentin Labbe	reg_gmac_3v3: gmac-3v3 {
6424e9f61cSCorentin Labbe		compatible = "regulator-fixed";
6524e9f61cSCorentin Labbe		regulator-name = "vcc-gmac-3v3";
6624e9f61cSCorentin Labbe		regulator-min-microvolt = <3300000>;
6724e9f61cSCorentin Labbe		regulator-max-microvolt = <3300000>;
6824e9f61cSCorentin Labbe		startup-delay-us = <100000>;
6924e9f61cSCorentin Labbe		gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>;
7024e9f61cSCorentin Labbe		enable-active-high;
7124e9f61cSCorentin Labbe	};
7224e9f61cSCorentin Labbe
7344eb589cSIcenowy Zheng	reg_usb_vbus: vbus {
7444eb589cSIcenowy Zheng		compatible = "regulator-fixed";
7544eb589cSIcenowy Zheng		regulator-name = "usb-vbus";
7644eb589cSIcenowy Zheng		regulator-min-microvolt = <5000000>;
7744eb589cSIcenowy Zheng		regulator-max-microvolt = <5000000>;
7844eb589cSIcenowy Zheng		startup-delay-us = <100000>;
7944eb589cSIcenowy Zheng		gpio = <&r_pio 0 5 GPIO_ACTIVE_HIGH>;
8044eb589cSIcenowy Zheng		enable-active-high;
8144eb589cSIcenowy Zheng	};
82494d8367SIcenowy Zheng};
83494d8367SIcenowy Zheng
84fe79ea57SClément Péron&cpu0 {
85fe79ea57SClément Péron	cpu-supply = <&reg_dcdca>;
86fe79ea57SClément Péron};
87fe79ea57SClément Péron
88d8e2b7e1SClément Péron&de {
89d8e2b7e1SClément Péron	status = "okay";
90d8e2b7e1SClément Péron};
91d8e2b7e1SClément Péron
92d8e2b7e1SClément Péron&ehci0 {
93d8e2b7e1SClément Péron	status = "okay";
94d8e2b7e1SClément Péron};
95d8e2b7e1SClément Péron
96d8e2b7e1SClément Péron&ehci3 {
97d8e2b7e1SClément Péron	status = "okay";
98d8e2b7e1SClément Péron};
99d8e2b7e1SClément Péron
100729e1ffcSIcenowy Zheng&emac {
101729e1ffcSIcenowy Zheng	pinctrl-names = "default";
102729e1ffcSIcenowy Zheng	pinctrl-0 = <&ext_rgmii_pins>;
103419c65f5SCorentin Labbe	phy-mode = "rgmii-id";
104729e1ffcSIcenowy Zheng	phy-handle = <&ext_rgmii_phy>;
10524e9f61cSCorentin Labbe	phy-supply = <&reg_gmac_3v3>;
106729e1ffcSIcenowy Zheng	allwinner,rx-delay-ps = <200>;
107729e1ffcSIcenowy Zheng	allwinner,tx-delay-ps = <200>;
108729e1ffcSIcenowy Zheng	status = "okay";
109729e1ffcSIcenowy Zheng};
110729e1ffcSIcenowy Zheng
1118abc4c4aSClément Péron&gpu {
1128abc4c4aSClément Péron	mali-supply = <&reg_dcdcc>;
1138abc4c4aSClément Péron	status = "okay";
1148abc4c4aSClément Péron};
1158abc4c4aSClément Péron
1167d5bca1cSJernej Skrabec&hdmi {
1177d5bca1cSJernej Skrabec	status = "okay";
1187d5bca1cSJernej Skrabec};
1197d5bca1cSJernej Skrabec
1207d5bca1cSJernej Skrabec&hdmi_out {
1217d5bca1cSJernej Skrabec	hdmi_out_con: endpoint {
1227d5bca1cSJernej Skrabec		remote-endpoint = <&hdmi_con_in>;
1237d5bca1cSJernej Skrabec	};
1247d5bca1cSJernej Skrabec};
1257d5bca1cSJernej Skrabec
126d8e2b7e1SClément Péron&mdio {
127d8e2b7e1SClément Péron	ext_rgmii_phy: ethernet-phy@1 {
128d8e2b7e1SClément Péron		compatible = "ethernet-phy-ieee802.3-c22";
129d8e2b7e1SClément Péron		reg = <1>;
1303bfa011dSIcenowy Zheng	};
1313bfa011dSIcenowy Zheng};
1323bfa011dSIcenowy Zheng
133ecbd6118SIcenowy Zheng&mmc0 {
134ecbd6118SIcenowy Zheng	vmmc-supply = <&reg_cldo1>;
135ecbd6118SIcenowy Zheng	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
136d177c8b6SIcenowy Zheng	bus-width = <4>;
137ecbd6118SIcenowy Zheng	status = "okay";
138ecbd6118SIcenowy Zheng};
139ecbd6118SIcenowy Zheng
140ecbd6118SIcenowy Zheng&mmc2 {
141ecbd6118SIcenowy Zheng	vmmc-supply = <&reg_cldo1>;
142ecbd6118SIcenowy Zheng	vqmmc-supply = <&reg_bldo2>;
143ecbd6118SIcenowy Zheng	non-removable;
144ecbd6118SIcenowy Zheng	cap-mmc-hw-reset;
1458837e845SAndre Przywara	mmc-hs200-1_8v;
146d177c8b6SIcenowy Zheng	bus-width = <8>;
147ecbd6118SIcenowy Zheng	status = "okay";
148ecbd6118SIcenowy Zheng};
149ecbd6118SIcenowy Zheng
1503bfa011dSIcenowy Zheng&ohci0 {
1513bfa011dSIcenowy Zheng	status = "okay";
1523bfa011dSIcenowy Zheng};
1533bfa011dSIcenowy Zheng
1543bfa011dSIcenowy Zheng&ohci3 {
1553bfa011dSIcenowy Zheng	status = "okay";
1563bfa011dSIcenowy Zheng};
1573bfa011dSIcenowy Zheng
15822538576SIcenowy Zheng&pio {
15922538576SIcenowy Zheng	vcc-pc-supply = <&reg_bldo2>;
16022538576SIcenowy Zheng	vcc-pd-supply = <&reg_cldo1>;
16122538576SIcenowy Zheng	vcc-pg-supply = <&reg_aldo1>;
16222538576SIcenowy Zheng};
16322538576SIcenowy Zheng
16417ebc33aSIcenowy Zheng&r_i2c {
16517ebc33aSIcenowy Zheng	status = "okay";
16617ebc33aSIcenowy Zheng
167eb28fb9eSIcenowy Zheng	axp805: pmic@36 {
168eb28fb9eSIcenowy Zheng		compatible = "x-powers,axp805", "x-powers,axp806";
169eb28fb9eSIcenowy Zheng		reg = <0x36>;
170eb28fb9eSIcenowy Zheng		interrupt-parent = <&r_intc>;
17173088dfeSSamuel Holland		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
172eb28fb9eSIcenowy Zheng		interrupt-controller;
173eb28fb9eSIcenowy Zheng		#interrupt-cells = <1>;
174eb28fb9eSIcenowy Zheng		x-powers,self-working-mode;
175eb28fb9eSIcenowy Zheng
176eb28fb9eSIcenowy Zheng		regulators {
177eb28fb9eSIcenowy Zheng			reg_aldo1: aldo1 {
178eb28fb9eSIcenowy Zheng				regulator-always-on;
179eb28fb9eSIcenowy Zheng				regulator-min-microvolt = <3300000>;
180eb28fb9eSIcenowy Zheng				regulator-max-microvolt = <3300000>;
181eb28fb9eSIcenowy Zheng				regulator-name = "vcc-pl";
182eb28fb9eSIcenowy Zheng			};
183eb28fb9eSIcenowy Zheng
184eb28fb9eSIcenowy Zheng			reg_aldo2: aldo2 {
185eb28fb9eSIcenowy Zheng				regulator-min-microvolt = <3300000>;
186eb28fb9eSIcenowy Zheng				regulator-max-microvolt = <3300000>;
187eb28fb9eSIcenowy Zheng				regulator-name = "vcc-ac200";
188729e1ffcSIcenowy Zheng				regulator-enable-ramp-delay = <100000>;
189eb28fb9eSIcenowy Zheng			};
190eb28fb9eSIcenowy Zheng
191eb28fb9eSIcenowy Zheng			reg_aldo3: aldo3 {
192eb28fb9eSIcenowy Zheng				/* This regulator is connected with CLDO1 */
193eb28fb9eSIcenowy Zheng				regulator-always-on;
194eb28fb9eSIcenowy Zheng				regulator-min-microvolt = <3300000>;
195eb28fb9eSIcenowy Zheng				regulator-max-microvolt = <3300000>;
196eb28fb9eSIcenowy Zheng				regulator-name = "vcc-3v3-1";
197eb28fb9eSIcenowy Zheng			};
198eb28fb9eSIcenowy Zheng
199eb28fb9eSIcenowy Zheng			reg_bldo1: bldo1 {
200eb28fb9eSIcenowy Zheng				regulator-always-on;
201eb28fb9eSIcenowy Zheng				regulator-min-microvolt = <1800000>;
202eb28fb9eSIcenowy Zheng				regulator-max-microvolt = <1800000>;
203eb28fb9eSIcenowy Zheng				regulator-name = "vcc-bias-pll";
204eb28fb9eSIcenowy Zheng			};
205eb28fb9eSIcenowy Zheng
206eb28fb9eSIcenowy Zheng			reg_bldo2: bldo2 {
207eb28fb9eSIcenowy Zheng				regulator-always-on;
208eb28fb9eSIcenowy Zheng				regulator-min-microvolt = <1800000>;
209eb28fb9eSIcenowy Zheng				regulator-max-microvolt = <1800000>;
210eb28fb9eSIcenowy Zheng				regulator-name = "vcc-efuse-pcie-hdmi-io";
211eb28fb9eSIcenowy Zheng			};
212eb28fb9eSIcenowy Zheng
213eb28fb9eSIcenowy Zheng			reg_bldo3: bldo3 {
214eb28fb9eSIcenowy Zheng				regulator-always-on;
215eb28fb9eSIcenowy Zheng				regulator-min-microvolt = <1800000>;
216eb28fb9eSIcenowy Zheng				regulator-max-microvolt = <1800000>;
217eb28fb9eSIcenowy Zheng				regulator-name = "vcc-dcxoio";
218eb28fb9eSIcenowy Zheng			};
219eb28fb9eSIcenowy Zheng
220eb28fb9eSIcenowy Zheng			bldo4 {
221eb28fb9eSIcenowy Zheng				/* unused */
222eb28fb9eSIcenowy Zheng			};
223eb28fb9eSIcenowy Zheng
224eb28fb9eSIcenowy Zheng			reg_cldo1: cldo1 {
225eb28fb9eSIcenowy Zheng				/* This regulator is connected with ALDO3 */
226eb28fb9eSIcenowy Zheng				regulator-always-on;
227eb28fb9eSIcenowy Zheng				regulator-min-microvolt = <3300000>;
228eb28fb9eSIcenowy Zheng				regulator-max-microvolt = <3300000>;
229eb28fb9eSIcenowy Zheng				regulator-name = "vcc-3v3-2";
230eb28fb9eSIcenowy Zheng			};
231eb28fb9eSIcenowy Zheng
232eb28fb9eSIcenowy Zheng			reg_cldo2: cldo2 {
233eb28fb9eSIcenowy Zheng				regulator-min-microvolt = <3300000>;
234eb28fb9eSIcenowy Zheng				regulator-max-microvolt = <3300000>;
235eb28fb9eSIcenowy Zheng				regulator-name = "vcc-wifi-1";
236eb28fb9eSIcenowy Zheng			};
237eb28fb9eSIcenowy Zheng
238eb28fb9eSIcenowy Zheng			reg_cldo3: cldo3 {
239eb28fb9eSIcenowy Zheng				regulator-min-microvolt = <3300000>;
240eb28fb9eSIcenowy Zheng				regulator-max-microvolt = <3300000>;
241eb28fb9eSIcenowy Zheng				regulator-name = "vcc-wifi-2";
242eb28fb9eSIcenowy Zheng			};
243eb28fb9eSIcenowy Zheng
244eb28fb9eSIcenowy Zheng			reg_dcdca: dcdca {
245eb28fb9eSIcenowy Zheng				regulator-always-on;
246eb28fb9eSIcenowy Zheng				regulator-min-microvolt = <810000>;
247fe79ea57SClément Péron				regulator-max-microvolt = <1160000>;
248fe79ea57SClément Péron				regulator-ramp-delay = <2500>;
249eb28fb9eSIcenowy Zheng				regulator-name = "vdd-cpu";
250eb28fb9eSIcenowy Zheng			};
251eb28fb9eSIcenowy Zheng
252eb28fb9eSIcenowy Zheng			reg_dcdcc: dcdcc {
2538abc4c4aSClément Péron				regulator-enable-ramp-delay = <32000>;
254eb28fb9eSIcenowy Zheng				regulator-min-microvolt = <810000>;
255eb28fb9eSIcenowy Zheng				regulator-max-microvolt = <1080000>;
256fe79ea57SClément Péron				regulator-ramp-delay = <2500>;
257eb28fb9eSIcenowy Zheng				regulator-name = "vdd-gpu";
258eb28fb9eSIcenowy Zheng			};
259eb28fb9eSIcenowy Zheng
260eb28fb9eSIcenowy Zheng			reg_dcdcd: dcdcd {
261eb28fb9eSIcenowy Zheng				regulator-always-on;
262eb28fb9eSIcenowy Zheng				regulator-min-microvolt = <960000>;
263eb28fb9eSIcenowy Zheng				regulator-max-microvolt = <960000>;
264eb28fb9eSIcenowy Zheng				regulator-name = "vdd-sys";
265eb28fb9eSIcenowy Zheng			};
266eb28fb9eSIcenowy Zheng
267eb28fb9eSIcenowy Zheng			reg_dcdce: dcdce {
268eb28fb9eSIcenowy Zheng				regulator-always-on;
269eb28fb9eSIcenowy Zheng				regulator-min-microvolt = <1200000>;
270eb28fb9eSIcenowy Zheng				regulator-max-microvolt = <1200000>;
271eb28fb9eSIcenowy Zheng				regulator-name = "vcc-dram";
272eb28fb9eSIcenowy Zheng			};
273eb28fb9eSIcenowy Zheng
274eb28fb9eSIcenowy Zheng			sw {
275eb28fb9eSIcenowy Zheng				/* unused */
276eb28fb9eSIcenowy Zheng			};
277eb28fb9eSIcenowy Zheng		};
278eb28fb9eSIcenowy Zheng	};
279eb28fb9eSIcenowy Zheng
28017ebc33aSIcenowy Zheng	pcf8563: rtc@51 {
28117ebc33aSIcenowy Zheng		compatible = "nxp,pcf8563";
28217ebc33aSIcenowy Zheng		reg = <0x51>;
2830bb9d187SChen-Yu Tsai		interrupt-parent = <&r_intc>;
28473088dfeSSamuel Holland		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
28517ebc33aSIcenowy Zheng		#clock-cells = <0>;
28617ebc33aSIcenowy Zheng	};
28717ebc33aSIcenowy Zheng};
28817ebc33aSIcenowy Zheng
28986be7408SClément Péron&r_ir {
29086be7408SClément Péron	status = "okay";
29186be7408SClément Péron};
29286be7408SClément Péron
29322538576SIcenowy Zheng&r_pio {
29422538576SIcenowy Zheng	vcc-pm-supply = <&reg_aldo1>;
29522538576SIcenowy Zheng};
29622538576SIcenowy Zheng
29732507b86SJernej Skrabec&rtc {
29832507b86SJernej Skrabec	clocks = <&ext_osc32k>;
29932507b86SJernej Skrabec};
30032507b86SJernej Skrabec
301e757bdd0SAndre Przywara/*
302e757bdd0SAndre Przywara * The CS pin is shared with the MMC2 CMD pin, so we cannot have the SPI
303e757bdd0SAndre Przywara * flash and eMMC at the same time, as one of them would fail probing.
304e757bdd0SAndre Przywara * Disable SPI0 in here, to prefer the more useful eMMC. U-Boot can
305e757bdd0SAndre Przywara * fix this up in no eMMC is connected.
306e757bdd0SAndre Przywara */
307e757bdd0SAndre Przywara&spi0 {
308e757bdd0SAndre Przywara	pinctrl-0 = <&spi0_pins>, <&spi0_cs_pin>;
309e757bdd0SAndre Przywara	pinctrl-names = "default";
310e757bdd0SAndre Przywara	status = "disabled";
311e757bdd0SAndre Przywara
312e757bdd0SAndre Przywara	flash@0 {
313e757bdd0SAndre Przywara		compatible = "winbond,w25q128", "jedec,spi-nor";
314e757bdd0SAndre Przywara		reg = <0>;
315e757bdd0SAndre Przywara		spi-max-frequency = <4000000>;
316e757bdd0SAndre Przywara	};
317e757bdd0SAndre Przywara};
318e757bdd0SAndre Przywara
319494d8367SIcenowy Zheng&uart0 {
320494d8367SIcenowy Zheng	pinctrl-names = "default";
321494d8367SIcenowy Zheng	pinctrl-0 = <&uart0_ph_pins>;
322494d8367SIcenowy Zheng	status = "okay";
323494d8367SIcenowy Zheng};
3243bfa011dSIcenowy Zheng
3253bfa011dSIcenowy Zheng&usb2otg {
3263bfa011dSIcenowy Zheng	dr_mode = "host";
3273bfa011dSIcenowy Zheng	status = "okay";
3283bfa011dSIcenowy Zheng};
3293bfa011dSIcenowy Zheng
3303bfa011dSIcenowy Zheng&usb2phy {
3313bfa011dSIcenowy Zheng	usb0_vbus-supply = <&reg_usb_vbus>;
3323bfa011dSIcenowy Zheng	usb3_vbus-supply = <&reg_usb_vbus>;
3333bfa011dSIcenowy Zheng	status = "okay";
3343bfa011dSIcenowy Zheng};
335