| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | cortina,gemini-ethernet.txt | 1 Cortina Systems Gemini Ethernet Controller
4 This ethernet controller is found in the Gemini SoC family:
9 - compatible: must be "cortina,gemini-ethernet"
10 - reg: must contain the global registers and the V-bit and A-bit
12 - syscon: a phandle to the system controller
13 - #address-cells: must be specified, must be <1>
14 - #size-cells: must be specified, must be <1>
15 - ranges: should be state like this giving a 1:1 address translation
18 The subnodes represents the two ethernet ports in this device.
23 - port0: contains the resources for ethernet port 0
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| H A D | brcm,unimac-mdio.txt | 4 - compatible: should one from "brcm,genet-mdio-v1", "brcm,genet-mdio-v2",
5 "brcm,genet-mdio-v3", "brcm,genet-mdio-v4", "brcm,genet-mdio-v5" or
6 "brcm,unimac-mdio"
7 - reg: address and length of the register set for the device, first one is the
9 larger than 16-bits MDIO transactions
10 - reg-names: name(s) of the register must be "mdio" and optional "mdio_indir_rw"
11 - #size-cells: must be 1
12 - #address-cells: must be 0
15 - interrupts: must be one if the interrupt is shared with the Ethernet MAC or
16 Ethernet switch this MDIO block is integrated from, or must be two, if there
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| H A D | brcm,bcmgenet.txt | 1 * Broadcom BCM7xxx Ethernet Controller (GENET)
4 - compatible: should contain one of "brcm,genet-v1", "brcm,genet-v2",
5 "brcm,genet-v3", "brcm,genet-v4", "brcm,genet-v5", "brcm,bcm2711-genet-v5" or
6 "brcm,bcm7712-genet-v5".
7 - reg: address and length of the register set for the device
8 - interrupts and/or interrupts-extended: must be two cells, the first cell
11 optional third interrupt cell for Wake-on-LAN can be specified.
12 See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
14 - phy-mode: see ethernet.txt file in the same directory
15 - #address-cells: should be 1
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| H A D | adi,adin1110.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ADI ADIN1110 MAC-PHY
10 - Alexandru Tachici <alexandru.tachici@analog.com>
13 The ADIN1110 is a low power single port 10BASE-T1L MAC-
14 PHY designed for industrial Ethernet applications. It integrates
15 an Ethernet PHY core with a MAC and all the associated analog
18 The ADIN2111 is a low power, low complexity, two-Ethernet ports
19 switch with integrated 10BASE-T1L PHYs and one serial peripheral
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| H A D | ti,k3-am654-cpsw-nuss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ti,k3-am654-cpsw-nuss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: The TI AM654x/J721E/AM642x SoC Gigabit Ethernet MAC (Media Access Controller)
10 - Grygorii Strashko <grygorii.strashko@ti.com>
11 - Sekhar Nori <nsekhar@ti.com>
14 The TI AM654x/J721E SoC Gigabit Ethernet MAC (CPSW2G NUSS) has two ports
15 (one external) and provides Ethernet packet communication for the device.
16 The TI AM642x SoC Gigabit Ethernet MAC (CPSW3G NUSS) has three ports
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| H A D | marvell-orion-net.txt | 1 Marvell Orion/Discovery ethernet controller
4 The Marvell Discovery ethernet controller can be found on Marvell Orion SoCs
8 The Discovery ethernet controller is described with two levels of nodes. The
9 first level describes the ethernet controller itself and the second level
10 describes up to 3 ethernet port nodes within that controller. The reason for
12 set of controller registers. Each port node describes port-specific properties.
16 only one port associated. Multiple ports are implemented as multiple single-port
20 * Ethernet controller node
23 - #address-cells: shall be 1.
24 - #size-cells: shall be 0.
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| H A D | cortina,gemini-ethernet.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/cortina,gemini-ethernet.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cortina Systems Gemini Ethernet Controller
10 - Linus Walleij <linus.walleij@linaro.org>
13 This ethernet controller is found in the Gemini SoC family:
19 const: cortina,gemini-ethernet
23 description: must contain the global registers and the V-bit and A-bit
26 "#address-cells":
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| H A D | keystone-netcp.txt | 5 Ethernet packets. NetCP has a gigabit Ethernet (GbE) subsystem with a ethernet
6 switch sub-module to send and receive packets. NetCP also includes a packet
12 Keystone II SoC's also have a 10 Gigabit Ethernet Subsystem (XGbE) which
13 includes a 3-port Ethernet switch sub-module capable of 10Gb/s and 1Gb/s rates
14 per Ethernet port.
16 Keystone NetCP driver has a plug-in module architecture where each of the NetCP
17 sub-modules exist as a loadable kernel module which plug in to the netcp core.
18 These sub-modules are represented as "netcp-devices" in the dts bindings. It is
19 mandatory to have the ethernet switch sub-module for the ethernet interface to
20 be operational. Any other sub-module like the PA is optional.
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| H A D | fsl-enetc.txt | 1 * ENETC ethernet device tree bindings
4 external) there are two supported link modes specified by
9 - reg : Specifies PCIe Device Number and Function
12 - compatible : Should be "fsl,enetc".
18 In this case, the ENETC node should include a "mdio" sub-node
19 that in turn should contain the "ethernet-phy" node describing the
21 already defined in Documentation/devicetree/bindings/net/ethernet.txt or
26 - phy-handle : Phandle to a PHY on the MDIO bus.
27 Defined in ethernet.txt.
29 - phy-connection-type : Defined in ethernet.txt.
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| H A D | brcm,systemport.txt | 1 * Broadcom BCM7xxx Ethernet Systemport Controller (SYSTEMPORT)
4 - compatible: should be one of:
5 "brcm,systemport-v1.00"
6 "brcm,systemportlite-v1.00" or
8 - reg: address and length of the register set for the device.
9 - interrupts: interrupts for the device, first cell must be for the rx
11 optional third interrupt cell for Wake-on-LAN can be specified
12 - local-mac-address: Ethernet MAC address (48 bits) of this adapter
13 - phy-mode: Should be a string describing the PHY interface to the
14 Ethernet switch/PHY, see Documentation/devicetree/bindings/net/ethernet.txt
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| H A D | apm-xgene-enet.txt | 1 APM X-Gene SoC Ethernet nodes
3 Ethernet nodes are defined to describe on-chip ethernet interfaces in
4 APM X-Gene SoC.
6 Required properties for all the ethernet interfaces:
7 - compatible: Should state binding information from the following list,
8 - "apm,xgene-enet": RGMII based 1G interface
9 - "apm,xgene1-sgenet": SGMII based 1G interface
10 - "apm,xgene1-xgenet": XFI based 10G interface
11 - reg: Address and length of the register set for the device. It contains the
12 information of registers in the same order as described by reg-names
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| H A D | adi,adin.yaml | 1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandru Tachici <alexandru.tachici@analog.com>
13 Bindings for Analog Devices Industrial Ethernet PHYs
16 - $ref: ethernet-phy.yaml#
19 adi,rx-internal-delay-ps:
22 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
26 adi,tx-internal-delay-ps:
29 internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds.
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| H A D | microchip,lan966x-switch.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/microchip,lan966x-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip Lan966x Ethernet switch controller
10 - Horatiu Vultur <horatiu.vultur@microchip.com>
13 The lan966x switch is a multi-port Gigabit AVB/TSN Ethernet Switch with
14 two integrated 10/100/1000Base-T PHYs. In addition to the integrated PHYs,
15 it supports up to 2RGMII/RMII, up to 3BASE-X/SERDES/2.5GBASE-X and up to
16 2 Quad-SGMII/Quad-USGMII interfaces.
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| H A D | cavium-pip.txt | 1 * PIP Ethernet nexus.
3 The PIP Ethernet nexus can control several data packet input/output
4 devices. The devices have a two level grouping scheme. There may be
6 ports might be an individual Ethernet PHY.
10 - compatible: "cavium,octeon-3860-pip"
14 - reg: The base address of the PIP's register bank.
16 - #address-cells: Must be <1>.
18 - #size-cells: Must be <0>.
21 - compatible: "cavium,octeon-3860-pip-interface"
25 - reg: The interface number.
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| H A D | mediatek-net.txt | 1 MediaTek Frame Engine Ethernet controller
4 The frame engine ethernet controller can be found on MediaTek SoCs. These SoCs
7 * Ethernet controller node
10 - compatible: Should be
11 "mediatek,mt2701-eth": for MT2701 SoC
12 "mediatek,mt7623-eth", "mediatek,mt2701-eth": for MT7623 SoC
13 "mediatek,mt7622-eth": for MT7622 SoC
14 "mediatek,mt7629-eth": for MT7629 SoC
15 "ralink,rt5350-eth": for Ralink Rt5350F and MT7628/88 SoC
16 - reg: Address and length of the register set for the device
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| H A D | xilinx_axienet.txt | 1 XILINX AXI ETHERNET Device Tree Bindings
2 --------------------------------------------------------
4 Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core
5 provides connectivity to an external ethernet PHY supporting different
6 interfaces: MII, GMII, RGMII, SGMII, 1000BaseX. It also includes two
18 - compatible : Must be one of "xlnx,axi-ethernet-1.00.a",
19 "xlnx,axi-ethernet-1.01.a", "xlnx,axi-ethernet-2.01.a"
20 - reg : Address and length of the IO space, as well as the address
22 axistream-connected is specified, in which case the reg
24 - interrupts : Should be a list of 2 or 3 interrupts: TX DMA, RX DMA,
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| /freebsd/share/man/man4/ |
| H A D | bnxt.4 | 31 .Nd "Broadcom NetXtreme-C/NetXtreme-E Family Ethernet driver"
36 .Bd -ragged -offset indent
44 .Bd -literal -offset indent
51 BCM57402/4/6, and BCM57502/4/8 Ethernet controller chips.
58 driver provides support for various NICs based on the Broadcom NetXtreme-C and
59 NetXtreme-
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| H A D | lagg.4 | 27 .Bd -ragged -offset indent
34 .Bd -literal -offset indent
42 interface for the purpose of providing fault-tolerance and high-speed links.
66 .Ic laggport Ar child-iface
68 .Ic -laggport Ar child-iface
84 .Bl -ta
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| H A D | bridge.4 | 46 .Bd -ragged -offset indent
53 .Bd -literal -offset indent
60 driver creates a logical link between two or more IEEE 802 networks
64 For example, it is possible to bridge Ethernet and 802.11 networks together,
65 but it is not possible to bridge Ethernet and Token Ring together.
88 Thus you can theoretically have two bridges on different machines with
97 has a non-zero value, the newly created bridge will inherit the MAC
98 address from its first member instead of choosing a random link-level
110 802.11-to-Ethernet bridge for wireless hosts, or traffic isolation.
145 Changing capabilities at run-time may cause NIC reinit and a link flap.
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| H A D | le.4 | 3 .\"-
8 .\" at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
42 .Nd "AMD Am7900 LANCE and Am79C9xx ILACC/PCnet Ethernet interface driver"
47 .Bd -ragged -offset indent
54 .Bd -literal -offset indent
58 For ISA non-PnP adapters, the port address as well as the IRQ and the DRQ
74 driver provides support for Ethernet adapters based on the
78 .Pq CMOS, pin-compatible
79 Local Area Network Controller for Ethernet
85 driver also supports Ethernet adapters based on the
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| /freebsd/sys/contrib/device-tree/Bindings/net/dsa/ |
| H A D | dsa.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
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| /freebsd/sys/dev/irdma/ |
| H A D | ice_devids.h | 1 /*-
2 * SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB
4 * Copyright (c) 2019 - 2020 Intel Corporation
6 * This software is available to you under a choice of one of two
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
41 /* Intel(R) Ethernet Connection E823-L for backplane */
43 /* Intel(R) Ethernet Connection E823-L for SFP */
45 /* Intel(R) Ethernet Connection E823-L/X557-AT 10GBASE-T */
47 /* Intel(R) Ethernet Connection E823-L 1GbE */
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| /freebsd/contrib/ofed/libirdma/ |
| H A D | ice_devids.h | 1 /*-
2 * SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB
4 * Copyright (c) 2019 - 2020 Intel Corporation
6 * This software is available to you under a choice of one of two
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
41 /* Intel(R) Ethernet Connection E823-L for backplane */
43 /* Intel(R) Ethernet Connection E823-L for SFP */
45 /* Intel(R) Ethernet Connection E823-L/X557-AT 10GBASE-T */
47 /* Intel(R) Ethernet Connection E823-L 1GbE */
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| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | armada3700-periph-clock.txt | 6 There are two different blocks associated to north bridge and south
14 -----------------------------------
35 -----------------------------------
36 0 gbe-50 50 MHz parent clock for Gigabit Ethernet
37 1 gbe-core parent clock for Gigabit Ethernet core
38 2 gbe-125 125 MHz parent clock for Gigabit Ethernet
39 3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1
40 4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0
41 5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1
42 6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0
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| /freebsd/sys/contrib/device-tree/Bindings/powerpc/fsl/ |
| H A D | mpc5200.txt | 2 ----------------------------
4 (c) 2006-2009 Secret Lab Technologies Ltd
8 ------------------
9 For mpc5200 on-chip devices, the format for each compatible value is
10 <chip>-<device>[-<mode>]. The OS should be able to match a device driver
11 to the device based solely on the compatible value. If two drivers
21 "fsl,mpc5200-<device>".
28 should have two items in the compatible list:
29 compatible = "fsl,mpc5200b-<device>","fsl,mpc5200-<device>";
34 ie. ethernet on mpc5200: compatible = "fsl,mpc5200-fec";
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