Lines Matching +full:two +full:- +full:ethernet
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ti,k3-am654-cpsw-nuss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: The TI AM654x/J721E/AM642x SoC Gigabit Ethernet MAC (Media Access Controller)
10 - Grygorii Strashko <grygorii.strashko@ti.com>
11 - Sekhar Nori <nsekhar@ti.com>
14 The TI AM654x/J721E SoC Gigabit Ethernet MAC (CPSW2G NUSS) has two ports
15 (one external) and provides Ethernet packet communication for the device.
16 The TI AM642x SoC Gigabit Ethernet MAC (CPSW3G NUSS) has three ports
17 (two external) and provides Ethernet packet communication and switching.
22 Complex (UDMA-P) controller.
52 "#address-cells": true
53 "#size-cells": true
57 - ti,am642-cpsw-nuss
58 - ti,am654-cpsw-nuss
59 - ti,j7200-cpswxg-nuss
60 - ti,j721e-cpsw-nuss
61 - ti,j721e-cpswxg-nuss
62 - ti,j784s4-cpswxg-nuss
69 reg-names:
71 - const: cpsw_nuss
75 dma-coherent: true
81 clock-names:
83 - const: fck
85 assigned-clock-parents: true
87 assigned-clocks: true
89 power-domains:
95 dma-names:
97 - const: tx0
98 - const: tx1
99 - const: tx2
100 - const: tx3
101 - const: tx4
102 - const: tx5
103 - const: tx6
104 - const: tx7
105 - const: rx
107 ethernet-ports:
110 '#address-cells':
112 '#size-cells':
116 "^port@[1-8]$":
120 $ref: ethernet-controller.yaml#
132 - description: CPSW MAC's PHY.
133 - description: Serdes PHY. Serdes PHY is required only if
135 Single-Link configuration.
137 phy-names:
140 - const: mac
141 - const: serdes
146 ti,mac-only:
149 Specifies the port works in mac-only mode.
151 ti,syscon-efuse:
152 $ref: /schemas/types.yaml#/definitions/phandle-array
154 - items:
155 - description: Phandle to the system control device node which
157 - description: offset to efuse registers???
163 - reg
164 - phys
169 "^mdio@[0-9a-f]+$":
171 $ref: ti,davinci-mdio.yaml#
176 "^cpts@[0-9a-f]+":
178 $ref: ti,k3-am654-cpts.yaml#
183 - compatible
184 - reg
185 - reg-names
186 - ranges
187 - clocks
188 - clock-names
189 - power-domains
190 - dmas
191 - dma-names
192 - '#address-cells'
193 - '#size-cells'
196 - if:
202 - ti,j721e-cpswxg-nuss
203 - ti,j784s4-cpswxg-nuss
206 ethernet-ports:
208 "^port@[5-8]$": false
209 "^port@[1-4]$":
215 - if:
221 - ti,j7200-cpswxg-nuss
222 - ti,j721e-cpswxg-nuss
223 - ti,j784s4-cpswxg-nuss
226 ethernet-ports:
228 "^port@[3-8]$": false
229 "^port@[1-2]$":
238 - |
239 #include <dt-bindings/soc/ti,sci_pm_domain.h>
240 #include <dt-bindings/net/ti-dp83867.h>
241 #include <dt-bindings/interrupt-controller/irq.h>
242 #include <dt-bindings/interrupt-controller/arm-gic.h>
245 #address-cells = <2>;
246 #size-cells = <2>;
248 mcu_cpsw: ethernet@46000000 {
249 compatible = "ti,am654-cpsw-nuss";
250 #address-cells = <2>;
251 #size-cells = <2>;
253 reg-names = "cpsw_nuss";
255 dma-coherent;
257 clock-names = "fck";
258 power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>;
259 pinctrl-names = "default";
260 pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
271 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
274 ethernet-ports {
275 #address-cells = <1>;
276 #size-cells = <0>;
280 ti,mac-only;
282 ti,syscon-efuse = <&mcu_conf 0x200>;
285 phy-mode = "rgmii-rxid";
286 phy-handle = <&phy0>;
291 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
293 #address-cells = <1>;
294 #size-cells = <0>;
296 clock-names = "fck";
299 phy0: ethernet-phy@0 {
301 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
302 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
308 compatible = "ti,am65-cpts";
311 clock-names = "cpts";
312 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
313 interrupt-names = "cpts";
314 ti,cpts-ext-ts-inputs = <4>;
315 ti,cpts-periodic-outputs = <2>;