Lines Matching +full:two +full:- +full:ethernet

1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Alexandru Tachici <alexandru.tachici@analog.com>
13   Bindings for Analog Devices Industrial Ethernet PHYs
16   - $ref: ethernet-phy.yaml#
19   adi,rx-internal-delay-ps:
22       internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
26   adi,tx-internal-delay-ps:
29       internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds.
33   adi,fifo-depth-bits:
39   adi,phy-output-clock:
41       Select clock output on GP_CLK pin. Two clocks are available:
42       A 25MHz reference and a free-running 125MHz.
47       - 25mhz-reference
48       - 125mhz-free-running
49       - adaptive-free-running
51   adi,phy-output-reference-clock:
58   - |
59     ethernet {
60         #address-cells = <1>;
61         #size-cells = <0>;
63         phy-mode = "rgmii-id";
65         ethernet-phy@0 {
68             adi,rx-internal-delay-ps = <1800>;
69             adi,tx-internal-delay-ps = <2200>;
72   - |
73     ethernet {
74         #address-cells = <1>;
75         #size-cells = <0>;
77         phy-mode = "rmii";
79         ethernet-phy@1 {
82             adi,fifo-depth-bits = <16>;