| /linux/drivers/pmdomain/renesas/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
7 bool "System Controller support for R-Car" if COMPILE_TEST
10 bool "System Controller support for R-Car Gen4" if COMPILE_TEST
13 bool "System Controller support for R-Mobile" if COMPILE_TEST
17 bool "System Controller support for R8A7742 (RZ/G1H)" if COMPILE_TEST
21 bool "System Controller support for R8A7743 (RZ/G1M)" if COMPILE_TEST
25 bool "System Controller support for R8A7745 (RZ/G1E)" if COMPILE_TEST
29 bool "System Controller support for R8A77470 (RZ/G1C)" if COMPILE_TEST
33 bool "System Controller support for R8A774A1 (RZ/G2M)" if COMPILE_TEST
37 bool "System Controller support for R8A774B1 (RZ/G2N)" if COMPILE_TEST
[all …]
|
| /linux/drivers/eisa/ |
| H A D | eisa.ids | 6 # Marc Zyngier <maz@wild-wind.fr.eu.org>
10 ABP0510 "Advansys ABP-510 ISA SCSI Host Adapter"
11 ABP0540 "Advansys ABP-540/542 ISA SCSI Host Adapter"
12 ABP7401 "AdvanSys ABP-740/742 EISA Single Channel SCSI Host Adapter"
13 ABP7501 "AdvanSys ABP-750/752 EISA Dual Channel SCSI Host Adapter"
14 ACC1200 "ACCTON EtherCombo-32 Ethernet Adapter"
15 ACC120A "ACCTON EtherCombo-32 Ethernet Adapter"
18 ACE1010 "ACME Super Fast System Board"
22 ACE4010 "ACME Tape Controller"
24 ACE6010 "ACME Disk Controller"
[all …]
|
| /linux/Documentation/devicetree/bindings/arm/hisilicon/controller/ |
| H A D | sysctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/hisilicon/controller/sysctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Hisilicon system controller
10 - Wei Xu <xuwei5@hisilicon.com>
13 The Hisilicon system controller is used on many Hisilicon boards, it can be
14 used to assist the slave core startup, reboot the system, etc.
16 There are some variants of the Hisilicon system controller, such as HiP01,
17 Hi3519, Hi6220 system controller, each of them is mostly compatible with the
[all …]
|
| /linux/Documentation/devicetree/bindings/arm/keystone/ |
| H A D | ti,sci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI-SCI controller
10 - Nishanth Menon <nm@ti.com>
15 management of the System on Chip (SoC) system. These include various system
18 An example of such an SoC is K2G, which contains the system control hardware
19 block called Power Management Micro Controller (PMMC). This hardware block is
23 See https://software-dl.ti.com/tisci/esd/latest/index.html for protocol definition.
25 The TI-SCI node describes the Texas Instrument's System Controller entity node.
[all …]
|
| /linux/Documentation/devicetree/bindings/arm/marvell/ |
| H A D | mvebu-system-controller.txt | 1 MVEBU System Controller
2 -----------------------
7 - compatible: one of:
8 - "marvell,orion-system-controller"
9 - "marvell,armada-370-xp-system-controller"
10 - "marvell,armada-375-system-controller"
11 - reg: Should contain system controller registers location and length.
15 system-controller@d0018200 {
16 compatible = "marvell,armada-370-xp-system-controller";
|
| /linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | berlin,pinctrl.txt | 1 * Pin-controller driver for the Marvell Berlin SoCs
3 Pin control registers are part of both chip controller and system
4 controller register sets. Pin controller nodes should be a sub-node of
5 either the chip controller or system controller node. The pins
9 A pin-controller node should contain subnodes representing the pin group
14 is called a 'function' in the pin-controller subsystem.
17 - compatible: should be one of:
18 "marvell,berlin2-soc-pinctrl",
19 "marvell,berlin2-system-pinctrl",
20 "marvell,berlin2cd-soc-pinctrl",
[all …]
|
| H A D | sprd,pinctrl.txt | 1 * Spreadtrum Pin Controller
3 The Spreadtrum pin controller are organized in 3 blocks (types).
8 pad driving level, system control select and so on ("domain pad
11 select 3.0v, then the pin can output 3.0v. "system control" is used
12 to choose one function (like: UART0) for which system, since we
16 of them, so we can not make every Spreadtrum-special configuration
32 Now we have 4 systems for sleep mode on SC9860 SoC: AP system,
33 PUBCP system, TGLDSP system and AGDSP system. And the pin sleep
35 - input-enable
36 - input-disable
[all …]
|
| /linux/Documentation/devicetree/bindings/soc/microchip/ |
| H A D | microchip,mpfs-sys-controller.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/microchip/microchip,mpfs-sys-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) system controller
10 - Conor Dooley <conor.dooley@microchip.com>
13 PolarFire SoC devices include a microcontroller acting as the system controller,
17 https://onlinedocs.microchip.com/pr/GUID-1409CF11-8EF9-4C24-A94E-70979A688632-en-US-1/index.html
19 Communication with the system controller is done via a mailbox, of which the client
27 const: microchip,mpfs-sys-controller
[all …]
|
| /linux/Documentation/ABI/testing/ |
| H A D | sysfs-devices-edac | 1 What: /sys/devices/system/edac/mc/mc*/reset_counters
3 Contact: linux-edac@vger.kernel.org
4 Description: This write-only control file will zero all the statistical
5 counters for UE and CE errors on the given memory controller.
12 What: /sys/devices/system/edac/mc/mc*/seconds_since_reset
14 Contact: linux-edac@vger.kernel.org
19 What: /sys/devices/system/edac/mc/mc*/mc_name
21 Contact: linux-edac@vger.kernel.org
22 Description: This attribute file displays the type of memory controller
25 What: /sys/devices/system/edac/mc/mc*/size_mb
[all …]
|
| /linux/Documentation/devicetree/bindings/reset/ |
| H A D | ti,sci-reset.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/ti,sci-reset.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI-SCI reset controller
10 - Nishanth Menon <nm@ti.com>
13 Some TI SoCs contain a system controller (like the Power Management Micro
14 Controller (PMMC) on Keystone 66AK2G SoC) that are responsible for controlling
16 between the host processor running an OS and the system controller happens
17 through a protocol called TI System Control Interface (TI-SCI protocol).
[all …]
|
| /linux/Documentation/devicetree/bindings/cache/ |
| H A D | socionext,uniphier-system-cache.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/cache/socionext,uniphier-system-cache.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UniPhier outer cache controller
10 UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache
11 controller system. All of them have a level 2 cache controller, and some
12 have a level 3 cache controller as well.
15 - Masahiro Yamada <yamada.masahiro@socionext.com>
19 const: socionext,uniphier-system-cache
[all …]
|
| /linux/Documentation/devicetree/bindings/soc/ti/ |
| H A D | ti,j721e-system-controller.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/soc/ti/ti,j721e-system-controller.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: TI J721e System Controller Registers R/W
12 System controller node represents a register region containing a set
14 represent as any specific type of device. The typical use-case is
15 for some other node's driver, or platform-specific code, to acquire
22 - Kishon Vijay Abraham I <kishon@kernel.org>
[all …]
|
| /linux/drivers/usb/typec/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
4 tristate "USB Type-C Support"
6 USB Type-C Specification defines a cable and connector for USB where
8 be Type-A plug on one end of the cable and Type-B plug on the other.
9 Determination of the host-to-device relationship happens through a
10 specific Configuration Channel (CC) which goes through the USB Type-C
12 Accessory Modes - Analog Audio and Debug - and if USB Power Delivery
22 USB Type-C connector, however it is mostly used together with USB
23 Type-C connectors.
25 USB Type-C and USB Power Delivery Specifications define a set of state
[all …]
|
| /linux/Documentation/arch/x86/ |
| H A D | earlyprintk.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 Mini-HOWTO for using the earlyprintk=dbgp boot option with a
13 [host/target] <-------> [USB debug key] <-------> [client/console]
18 a) Host/target system needs to have USB debug port capability.
21 the lspci -vvv output::
23 # lspci -vvv
25 …00:1d.7 USB Controller: Intel Corporation 82801H (ICH8 Family) USB2 EHCI Controller #1 (rev 03) (p…
27 …Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisIN…
28 …Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- I…
31 Region 0: Memory at fe227000 (32-bit, non-prefetchable) [size=1K]
[all …]
|
| /linux/Documentation/devicetree/bindings/sram/ |
| H A D | allwinner,sun4i-a10-system-control.yaml | 1 # SPDX-License-Identifier: GPL-2.0+
3 ---
4 $id: http://devicetree.org/schemas/sram/allwinner,sun4i-a10-system-control.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 System Control
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 The SRAM controller found on most Allwinner devices is represented
15 by a regular node for the SRAM controller itself, with sub-nodes
16 representing the SRAM handled by the SRAM controller.
[all …]
|
| /linux/Documentation/devicetree/bindings/clock/ |
| H A D | ti,sci-clk.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/ti,sci-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI-SCI clock controller
10 - Nishanth Menon <nm@ti.com>
13 Some TI SoCs contain a system controller (like the Power Management Micro
14 Controller (PMMC) on Keystone 66AK2G SoC) that are responsible for controlling
16 between the host processor running an OS and the system controller happens
17 through a protocol called TI System Control Interface (TI-SCI protocol).
[all …]
|
| H A D | arm,syscon-icst.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/arm,syscon-icst.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM System Controller ICST Clocks
10 - Linus Walleij <linusw@kernel.org>
16 oscillators to their system controllers.
18 The various ARM system controllers contain logic to serialize and initialize
20 into the system controller. Furthermore, to even be able to alter one of
21 these frequencies, the system controller must first be unlocked by
[all …]
|
| /linux/drivers/firmware/imx/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
18 The System Controller Firmware (SCFW) is a low-level system function
19 which runs on a dedicated Cortex-M core to provide power, clock, and
31 The System Controller Management Interface firmware (SCMI FW) is
32 a low-level system function which runs on a dedicated Cortex-M
42 The System Controller Management Interface firmware (SCMI FW) is
43 a low-level system function which runs on a dedicated Cortex-M
53 The System Controller Management Interface firmware (SCMI FW) is
54 a low-level system function which runs on a dedicated Cortex-M
|
| /linux/drivers/clk/starfive/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
12 Say yes here to support the clock controller on the StarFive JH7100
29 Say yes here to support the PLL clock controller on the
33 bool "StarFive JH7110 system clock support"
41 Say yes here to support the system clock controller on the
45 tristate "StarFive JH7110 always-on clock support"
49 Say yes here to support the always-on clock controller on the
53 tristate "StarFive JH7110 System-Top-Group clock support"
57 Say yes here to support the System-Top-Group clock controller
61 tristate "StarFive JH7110 Image-Signal-Process clock support"
[all …]
|
| /linux/drivers/reset/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
6 bool "Reset Controller Support"
9 Generic Reset Controller support.
12 via GPIOs or SoC-internal reset controller modules.
19 tristate "Altera Arria10 System Resource Reset"
23 peripheral PHYs on the Altera Arria10 System Resource Chip.
30 This enables the reset controller driver for AST2700.
36 This enables the ATH79 reset controller driver that supports the
37 AR71xx SoC reset controller.
43 This enables the reset controller driver for AXS10x.
[all …]
|
| /linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | ti,sci-intr.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/ti,sci-intr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lokesh Vutla <lokeshvutla@ti.com>
13 - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
22 +----------------------+
24 +-------+ | +------+ +-----+ |
25 | GPIO |----------->| | irq0 | | 0 | | Host IRQ
26 +-------+ | +------+ +-----+ | controller
[all …]
|
| /linux/Documentation/admin-guide/cgroup-v1/ |
| H A D | cpuacct.rst | 2 CPU Accounting Controller
5 The CPU accounting controller is used to group tasks using cgroups and
8 The CPU accounting controller supports multi-hierarchy groups. An accounting
14 # mount -t cgroup -ocpuacct none /sys/fs/cgroup
18 the system. /sys/fs/cgroup/tasks lists the tasks in this cgroup.
21 in the system.
35 CPU time obtained by the cgroup into user and system times. Currently
39 system: Time spent by tasks of the cgroup in kernel mode.
41 user and system are in USER_HZ unit.
43 cpuacct controller uses percpu_counter interface to collect user and
[all …]
|
| /linux/arch/arm/mach-mvebu/ |
| H A D | system-controller.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * System controller support for Armada 370, 375 and XP platforms.
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 * but rather provide system-level features. This basic
14 * system-controller driver provides a device tree binding for those
19 * soft-reset, but it might be extended in the future.
28 #include "mvebu-soc-id.h"
79 .compatible = "marvell,orion-system-controller",
82 .compatible = "marvell,armada-370-xp-system-controller",
[all …]
|
| /linux/drivers/usb/cdns3/ |
| H A D | Kconfig | 7 Say Y here if your system has a Cadence USBSS or USBSSP
8 dual-role controller.
9 It supports: dual-role switch, Host-only, and Peripheral-only.
17 tristate "Cadence USB3 Dual-Role Controller"
20 Say Y here if your system has a Cadence USB3 dual-role controller.
21 It supports: dual-role switch, Host-only, and Peripheral-only.
30 bool "Cadence USB3 device controller"
33 Say Y here to enable device controller functionality of the
34 Cadence USBSS-DEV driver.
36 This controller supports FF, HS and SS mode. It doesn't support
[all …]
|
| /linux/drivers/platform/surface/aggregator/ |
| H A D | controller.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Main SSAM/SSH controller structure and functionality.
5 * Copyright (C) 2019-2022 Maximilian Luz <luzmaximilian@gmail.com>
22 #include <linux/surface_aggregator/controller.h>
28 /* -- Safe counters. -------------------------------------------------------- */
31 * struct ssh_seq_counter - Safe counter for SSH sequence IDs.
39 * struct ssh_rqid_counter - Safe counter for SSH request IDs.
47 /* -- Event/notification system. -------------------------------------------- */
50 * struct ssam_nf_head - Notifier head for SSAM events.
52 * @head: List-head for notifier blocks registered under this head.
[all …]
|