| /linux/drivers/pmdomain/renesas/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
5 bool "System Controller support for R-Car" if COMPILE_TEST
8 bool "System Controller support for R-Car Gen4" if COMPILE_TEST
11 bool "System Controller support for R-Car D3" if COMPILE_TEST
15 bool "System Controller support for R-Car E2" if COMPILE_TEST
19 bool "System Controller support for R-Car E3" if COMPILE_TEST
23 bool "System Controller support for R-Car H1" if COMPILE_TEST
27 bool "System Controller support for R-Car H2" if COMPILE_TEST
31 bool "System Controller support for R-Car H3" if COMPILE_TEST
35 bool "System Controller support for R-Car M2-W/N" if COMPILE_TEST
[all …]
|
| /linux/drivers/eisa/ |
| H A D | eisa.ids | 6 # Marc Zyngier <maz@wild-wind.fr.eu.org>
10 ABP0510 "Advansys ABP-510 ISA SCSI Host Adapter"
11 ABP0540 "Advansys ABP-540/542 ISA SCSI Host Adapter"
12 ABP7401 "AdvanSys ABP-740/742 EISA Single Channel SCSI Host Adapter"
13 ABP7501 "AdvanSys ABP-750/752 EISA Dual Channel SCSI Host Adapter"
14 ACC1200 "ACCTON EtherCombo-32 Ethernet Adapter"
15 ACC120A "ACCTON EtherCombo-32 Ethernet Adapter"
18 ACE1010 "ACME Super Fast System Board"
22 ACE4010 "ACME Tape Controller"
24 ACE6010 "ACME Disk Controller"
[all …]
|
| /linux/Documentation/devicetree/bindings/arm/hisilicon/controller/ |
| H A D | sysctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/hisilicon/controller/sysctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Hisilicon system controller
10 - Wei Xu <xuwei5@hisilicon.com>
13 The Hisilicon system controller is used on many Hisilicon boards, it can be
14 used to assist the slave core startup, reboot the system, etc.
16 There are some variants of the Hisilicon system controller, such as HiP01,
17 Hi3519, Hi6220 system controller, each of them is mostly compatible with the
[all …]
|
| /linux/Documentation/devicetree/bindings/arm/keystone/ |
| H A D | ti,sci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI-SCI controller
10 - Nishanth Menon <nm@ti.com>
15 management of the System on Chip (SoC) system. These include various system
18 An example of such an SoC is K2G, which contains the system control hardware
19 block called Power Management Micro Controller (PMMC). This hardware block is
23 See https://software-dl.ti.com/tisci/esd/latest/index.html for protocol definition.
25 The TI-SCI node describes the Texas Instrument's System Controller entity node.
[all …]
|
| /linux/Documentation/devicetree/bindings/arm/marvell/ |
| H A D | mvebu-system-controller.txt | 1 MVEBU System Controller
2 -----------------------
7 - compatible: one of:
8 - "marvell,orion-system-controller"
9 - "marvell,armada-370-xp-system-controller"
10 - "marvell,armada-375-system-controller"
11 - reg: Should contain system controller registers location and length.
15 system-controller@d0018200 {
16 compatible = "marvell,armada-370-xp-system-controller";
|
| H A D | ap80x-system-controller.txt | 1 Marvell Armada AP80x System Controller
5 7K/8K/931x SoCs. It contains system controllers, which provide several
6 registers giving access to numerous features: clocks, pin-muxing and
8 these system controllers.
11 - compatible: must be: "syscon", "simple-mfd";
12 - reg: register area of the AP80x system controller
14 SYSTEM CONTROLLER 0
18 -------
21 The Device Tree node representing the AP806/AP807 system controller
24 - 0: reference clock of CPU cluster 0
[all …]
|
| /linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | berlin,pinctrl.txt | 1 * Pin-controller driver for the Marvell Berlin SoCs
3 Pin control registers are part of both chip controller and system
4 controller register sets. Pin controller nodes should be a sub-node of
5 either the chip controller or system controller node. The pins
9 A pin-controller node should contain subnodes representing the pin group
14 is called a 'function' in the pin-controller subsystem.
17 - compatible: should be one of:
18 "marvell,berlin2-soc-pinctrl",
19 "marvell,berlin2-system-pinctrl",
20 "marvell,berlin2cd-soc-pinctrl",
[all …]
|
| H A D | sprd,pinctrl.txt | 1 * Spreadtrum Pin Controller
3 The Spreadtrum pin controller are organized in 3 blocks (types).
8 pad driving level, system control select and so on ("domain pad
11 select 3.0v, then the pin can output 3.0v. "system control" is used
12 to choose one function (like: UART0) for which system, since we
16 of them, so we can not make every Spreadtrum-special configuration
32 Now we have 4 systems for sleep mode on SC9860 SoC: AP system,
33 PUBCP system, TGLDSP system and AGDSP system. And the pin sleep
35 - input-enable
36 - input-disable
[all …]
|
| /linux/Documentation/devicetree/bindings/soc/microchip/ |
| H A D | microchip,mpfs-sys-controller.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/microchip/microchip,mpfs-sys-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) system controller
10 - Conor Dooley <conor.dooley@microchip.com>
13 PolarFire SoC devices include a microcontroller acting as the system controller,
17 https://onlinedocs.microchip.com/pr/GUID-1409CF11-8EF9-4C24-A94E-70979A688632-en-US-1/index.html
19 Communication with the system controller is done via a mailbox, of which the client
27 const: microchip,mpfs-sys-controller
[all …]
|
| /linux/Documentation/ABI/testing/ |
| H A D | sysfs-devices-edac | 1 What: /sys/devices/system/edac/mc/mc*/reset_counters
3 Contact: linux-edac@vger.kernel.org
4 Description: This write-only control file will zero all the statistical
5 counters for UE and CE errors on the given memory controller.
12 What: /sys/devices/system/edac/mc/mc*/seconds_since_reset
14 Contact: linux-edac@vger.kernel.org
19 What: /sys/devices/system/edac/mc/mc*/mc_name
21 Contact: linux-edac@vger.kernel.org
22 Description: This attribute file displays the type of memory controller
25 What: /sys/devices/system/edac/mc/mc*/size_mb
[all …]
|
| /linux/drivers/input/touchscreen/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
20 support for the built-in touchscreen.
25 module will be called 88pm860x-ts.
33 ADS7846/TSC2046/AD7873 or ADS7843/AD7843 controller,
34 and your board-specific setup code includes that in its
51 AD7877 controller, and your board-specific initialization
60 tristate "Analog Devices AD7879-1/AD7889-1 touchscreen interface"
63 the AD7879-1/AD7889-1 controller.
75 Say Y here if you have AD7879-1/AD7889-1 hooked to an I2C bus.
78 module will be called ad7879-i2c.
[all …]
|
| /linux/Documentation/devicetree/bindings/reset/ |
| H A D | ti,sci-reset.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/ti,sci-reset.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI-SCI reset controller
10 - Nishanth Menon <nm@ti.com>
13 Some TI SoCs contain a system controller (like the Power Management Micro
14 Controller (PMMC) on Keystone 66AK2G SoC) that are responsible for controlling
16 between the host processor running an OS and the system controller happens
17 through a protocol called TI System Control Interface (TI-SCI protocol).
[all …]
|
| /linux/Documentation/devicetree/bindings/cache/ |
| H A D | socionext,uniphier-system-cache.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/cache/socionext,uniphier-system-cache.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UniPhier outer cache controller
10 UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache
11 controller system. All of them have a level 2 cache controller, and some
12 have a level 3 cache controller as well.
15 - Masahiro Yamada <yamada.masahiro@socionext.com>
19 const: socionext,uniphier-system-cache
[all …]
|
| /linux/Documentation/devicetree/bindings/soc/ti/ |
| H A D | ti,j721e-system-controller.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/soc/ti/ti,j721e-system-controller.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: TI J721e System Controller Registers R/W
12 System controller node represents a register region containing a set
14 represent as any specific type of device. The typical use-case is
15 for some other node's driver, or platform-specific code, to acquire
22 - Kishon Vijay Abraham I <kishon@kernel.org>
[all …]
|
| /linux/drivers/usb/typec/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
4 tristate "USB Type-C Support"
6 USB Type-C Specification defines a cable and connector for USB where
8 be Type-A plug on one end of the cable and Type-B plug on the other.
9 Determination of the host-to-device relationship happens through a
10 specific Configuration Channel (CC) which goes through the USB Type-C
12 Accessory Modes - Analog Audio and Debug - and if USB Power Delivery
22 USB Type-C connector, however it is mostly used together with USB
23 Type-C connectors.
25 USB Type-C and USB Power Delivery Specifications define a set of state
[all …]
|
| /linux/Documentation/arch/x86/ |
| H A D | earlyprintk.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 Mini-HOWTO for using the earlyprintk=dbgp boot option with a
13 [host/target] <-------> [USB debug key] <-------> [client/console]
18 a) Host/target system needs to have USB debug port capability.
21 the lspci -vvv output::
23 # lspci -vvv
25 …00:1d.7 USB Controller: Intel Corporation 82801H (ICH8 Family) USB2 EHCI Controller #1 (rev 03) (p…
27 …Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisIN…
28 …Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- I…
31 Region 0: Memory at fe227000 (32-bit, non-prefetchable) [size=1K]
[all …]
|
| /linux/Documentation/devicetree/bindings/clock/ |
| H A D | ti,sci-clk.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/ti,sci-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI-SCI clock controller
10 - Nishanth Menon <nm@ti.com>
13 Some TI SoCs contain a system controller (like the Power Management Micro
14 Controller (PMMC) on Keystone 66AK2G SoC) that are responsible for controlling
16 between the host processor running an OS and the system controller happens
17 through a protocol called TI System Control Interface (TI-SCI protocol).
[all …]
|
| H A D | pistachio-clock.txt | 6 from the device-tree.
9 ----------------
12 defined with the following clock-output-names:
13 - "xtal": External 52Mhz oscillator (required)
14 - "audio_clk_in": Alternate audio reference clock (optional)
15 - "enet_clk_in": Alternate ethernet PHY clock (optional)
17 Core clock controller:
18 ----------------------
20 The core clock controller generates clocks for the CPU, RPU (WiFi + BT
21 co-processor), audio, and several peripherals.
[all …]
|
| H A D | arm,syscon-icst.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/arm,syscon-icst.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM System Controller ICST Clocks
10 - Linus Walleij <linusw@kernel.org>
16 oscillators to their system controllers.
18 The various ARM system controllers contain logic to serialize and initialize
20 into the system controller. Furthermore, to even be able to alter one of
21 these frequencies, the system controller must first be unlocked by
[all …]
|
| /linux/drivers/reset/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
6 bool "Reset Controller Support"
9 Generic Reset Controller support.
12 via GPIOs or SoC-internal reset controller modules.
19 tristate "Altera Arria10 System Resource Reset"
23 peripheral PHYs on the Altera Arria10 System Resource Chip.
29 This enables the ATH79 reset controller driver that supports the
30 AR71xx SoC reset controller.
36 This enables the reset controller driver for AXS10x.
39 bool "BCM6345 Reset Controller"
[all …]
|
| /linux/drivers/irqchip/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
69 The maximum number of VICs available in the system, for
88 bool "Amazon's Annapurna Labs Fabric Interrupt Controller"
94 Support Amazon's Annapurna Labs Fabric Interrupt Controller.
119 tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver"
127 tristate "Broadcom STB 7120-style L2 interrupt controller driver"
134 tristate "Broadcom STB generic L2 interrupt controller driver"
176 Enable support for the LAN966x Outbound Interrupt Controller.
177 This controller is present on the Microchip LAN966x PCI device and
181 will be called irq-lan966x-oic.
[all …]
|
| /linux/drivers/clk/starfive/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
12 Say yes here to support the clock controller on the StarFive JH7100
29 Say yes here to support the PLL clock controller on the
33 bool "StarFive JH7110 system clock support"
41 Say yes here to support the system clock controller on the
45 tristate "StarFive JH7110 always-on clock support"
49 Say yes here to support the always-on clock controller on the
53 tristate "StarFive JH7110 System-Top-Group clock support"
57 Say yes here to support the System-Top-Group clock controller
61 tristate "StarFive JH7110 Image-Signal-Process clock support"
[all …]
|
| /linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | ti,sci-intr.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/ti,sci-intr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lokesh Vutla <lokeshvutla@ti.com>
13 - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
22 +----------------------+
24 +-------+ | +------+ +-----+ |
25 | GPIO |----------->| | irq0 | | 0 | | Host IRQ
26 +-------+ | +------+ +-----+ | controller
[all …]
|
| /linux/Documentation/admin-guide/cgroup-v1/ |
| H A D | cpuacct.rst | 2 CPU Accounting Controller
5 The CPU accounting controller is used to group tasks using cgroups and
8 The CPU accounting controller supports multi-hierarchy groups. An accounting
14 # mount -t cgroup -ocpuacct none /sys/fs/cgroup
18 the system. /sys/fs/cgroup/tasks lists the tasks in this cgroup.
21 in the system.
35 CPU time obtained by the cgroup into user and system times. Currently
39 system: Time spent by tasks of the cgroup in kernel mode.
41 user and system are in USER_HZ unit.
43 cpuacct controller uses percpu_counter interface to collect user and
[all …]
|
| /linux/init/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
8 - Re-run Kconfig when the compiler is updated
13 - Ensure full rebuild when the compiler is updated
14 include/linux/compiler-version.h contains this option in the comment
16 auto-generated dependency. When the compiler is updated, syncconfig
20 def_bool $(success,test "$(cc-name)" = GCC)
24 default $(cc-version) if CC_IS_GCC
28 def_bool $(success,test "$(cc-name)" = Clang)
32 default $(cc-version) if CC_IS_CLANG
36 def_bool $(success,test "$(as-name)" = GNU)
[all …]
|