1*b87a1cbbSRoger Quadros# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*b87a1cbbSRoger Quadros# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ 3*b87a1cbbSRoger Quadros%YAML 1.2 4*b87a1cbbSRoger Quadros--- 5*b87a1cbbSRoger Quadros$id: http://devicetree.org/schemas/soc/ti/ti,j721e-system-controller.yaml# 6*b87a1cbbSRoger Quadros$schema: http://devicetree.org/meta-schemas/core.yaml# 7*b87a1cbbSRoger Quadros 8*b87a1cbbSRoger Quadrostitle: TI J721e System Controller Registers R/W 9*b87a1cbbSRoger Quadros 10*b87a1cbbSRoger Quadrosdescription: | 11*b87a1cbbSRoger Quadros This represents the Control Module registers (CTRL_MMR0) on the SoC. 12*b87a1cbbSRoger Quadros System controller node represents a register region containing a set 13*b87a1cbbSRoger Quadros of miscellaneous registers. The registers are not cohesive enough to 14*b87a1cbbSRoger Quadros represent as any specific type of device. The typical use-case is 15*b87a1cbbSRoger Quadros for some other node's driver, or platform-specific code, to acquire 16*b87a1cbbSRoger Quadros a reference to the syscon node (e.g. by phandle, node path, or 17*b87a1cbbSRoger Quadros search using a specific compatible value), interrogate the node (or 18*b87a1cbbSRoger Quadros associated OS driver) to determine the location of the registers, 19*b87a1cbbSRoger Quadros and access the registers directly. 20*b87a1cbbSRoger Quadros 21*b87a1cbbSRoger Quadrosmaintainers: 22*b87a1cbbSRoger Quadros - Kishon Vijay Abraham I <kishon@kernel.org> 23*b87a1cbbSRoger Quadros - Roger Quadros <rogerq@kernel.org> 24*b87a1cbbSRoger Quadros 25*b87a1cbbSRoger Quadrosproperties: 26*b87a1cbbSRoger Quadros compatible: 27*b87a1cbbSRoger Quadros items: 28*b87a1cbbSRoger Quadros - enum: 29*b87a1cbbSRoger Quadros - ti,j7200-system-controller 30*b87a1cbbSRoger Quadros - ti,j721e-system-controller 31*b87a1cbbSRoger Quadros - ti,j721s2-system-controller 32*b87a1cbbSRoger Quadros - const: syscon 33*b87a1cbbSRoger Quadros - const: simple-mfd 34*b87a1cbbSRoger Quadros 35*b87a1cbbSRoger Quadros reg: 36*b87a1cbbSRoger Quadros maxItems: 1 37*b87a1cbbSRoger Quadros 38*b87a1cbbSRoger Quadros "#address-cells": 39*b87a1cbbSRoger Quadros const: 1 40*b87a1cbbSRoger Quadros 41*b87a1cbbSRoger Quadros "#size-cells": 42*b87a1cbbSRoger Quadros const: 1 43*b87a1cbbSRoger Quadros 44*b87a1cbbSRoger Quadros ranges: true 45*b87a1cbbSRoger Quadros 46*b87a1cbbSRoger QuadrospatternProperties: 47*b87a1cbbSRoger Quadros # Optional children 48*b87a1cbbSRoger Quadros "^mux-controller@[0-9a-f]+$": 49*b87a1cbbSRoger Quadros type: object 50*b87a1cbbSRoger Quadros description: 51*b87a1cbbSRoger Quadros This is the SERDES lane control mux. 52*b87a1cbbSRoger Quadros 53*b87a1cbbSRoger Quadros "^clock-controller@[0-9a-f]+$": 54*b87a1cbbSRoger Quadros type: object 55*b87a1cbbSRoger Quadros $ref: /schemas/clock/ti,am654-ehrpwm-tbclk.yaml# 56*b87a1cbbSRoger Quadros description: 57*b87a1cbbSRoger Quadros Clock provider for TI EHRPWM nodes. 58*b87a1cbbSRoger Quadros 59*b87a1cbbSRoger Quadros "phy@[0-9a-f]+$": 60*b87a1cbbSRoger Quadros type: object 61*b87a1cbbSRoger Quadros $ref: /schemas/phy/ti,phy-gmii-sel.yaml# 62*b87a1cbbSRoger Quadros description: 63*b87a1cbbSRoger Quadros The phy node corresponding to the ethernet MAC. 64*b87a1cbbSRoger Quadros 65*b87a1cbbSRoger Quadros "^chipid@[0-9a-f]+$": 66*b87a1cbbSRoger Quadros type: object 67*b87a1cbbSRoger Quadros $ref: /schemas/hwinfo/ti,k3-socinfo.yaml# 68*b87a1cbbSRoger Quadros description: 69*b87a1cbbSRoger Quadros The node corresponding to SoC chip identification. 70*b87a1cbbSRoger Quadros 71*b87a1cbbSRoger Quadrosrequired: 72*b87a1cbbSRoger Quadros - compatible 73*b87a1cbbSRoger Quadros - reg 74*b87a1cbbSRoger Quadros - "#address-cells" 75*b87a1cbbSRoger Quadros - "#size-cells" 76*b87a1cbbSRoger Quadros - ranges 77*b87a1cbbSRoger Quadros 78*b87a1cbbSRoger QuadrosadditionalProperties: false 79*b87a1cbbSRoger Quadros 80*b87a1cbbSRoger Quadrosexamples: 81*b87a1cbbSRoger Quadros - | 82*b87a1cbbSRoger Quadros scm_conf: scm-conf@100000 { 83*b87a1cbbSRoger Quadros compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 84*b87a1cbbSRoger Quadros reg = <0x00100000 0x1c000>; 85*b87a1cbbSRoger Quadros #address-cells = <1>; 86*b87a1cbbSRoger Quadros #size-cells = <1>; 87*b87a1cbbSRoger Quadros ranges; 88*b87a1cbbSRoger Quadros 89*b87a1cbbSRoger Quadros serdes_ln_ctrl: mux-controller@4080 { 90*b87a1cbbSRoger Quadros compatible = "mmio-mux"; 91*b87a1cbbSRoger Quadros reg = <0x00004080 0x50>; 92*b87a1cbbSRoger Quadros 93*b87a1cbbSRoger Quadros #mux-control-cells = <1>; 94*b87a1cbbSRoger Quadros mux-reg-masks = 95*b87a1cbbSRoger Quadros <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ 96*b87a1cbbSRoger Quadros <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ 97*b87a1cbbSRoger Quadros <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ 98*b87a1cbbSRoger Quadros <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */ 99*b87a1cbbSRoger Quadros <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>; 100*b87a1cbbSRoger Quadros /* SERDES4 lane0/1/2/3 select */ 101*b87a1cbbSRoger Quadros }; 102*b87a1cbbSRoger Quadros 103*b87a1cbbSRoger Quadros clock-controller@4140 { 104*b87a1cbbSRoger Quadros compatible = "ti,am654-ehrpwm-tbclk"; 105*b87a1cbbSRoger Quadros reg = <0x4140 0x18>; 106*b87a1cbbSRoger Quadros #clock-cells = <1>; 107*b87a1cbbSRoger Quadros }; 108*b87a1cbbSRoger Quadros 109*b87a1cbbSRoger Quadros chipid@14 { 110*b87a1cbbSRoger Quadros compatible = "ti,am654-chipid"; 111*b87a1cbbSRoger Quadros reg = <0x14 0x4>; 112*b87a1cbbSRoger Quadros }; 113*b87a1cbbSRoger Quadros }; 114*b87a1cbbSRoger Quadros... 115