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/linux/Documentation/devicetree/bindings/pci/
H A Dti,j721e-pci-host.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/pci/ti,j721e-pci-host.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: TI J721E PCI Host (PCIe Wrapper)
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - const: ti,j721e-pcie-host
17 - const: ti,j784s4-pcie-host
18 - description: PCIe controller in AM64
[all …]
H A Dti,j721e-pci-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/pci/ti,j721e-pci-ep.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: TI J721E PCI EP (PCIe Wrapper)
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - const: ti,j721e-pcie-ep
17 - const: ti,j784s4-pcie-ep
18 - description: PCIe EP controller in AM64
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-j784s4-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "ti,j721s2-c71-dsp";
13 reg-names = "l2sram", "l1dram";
15 firmware-name = "j784s4-c71_3-fw";
17 ti,sci-dev-id = <40>;
18 ti,sci-proc-ids = <0x33 0xff>;
22 pcie2_rc: pcie@2920000 {
23 compatible = "ti,j784s4-pcie-host";
30 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
[all …]
H A Dk3-j784s4-evm-pcie0-pcie1-ep.dtso1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
8 * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
11 /dts-v1/;
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/soc/ti,sci_pm_domain.h>
17 #include "k3-pinctrl.h"
32 #address-cells = <2>;
33 #size-cells = <2>;
34 interrupt-parent = <&gic500>;
36 pcie0_ep: pcie-ep@2900000 {
[all …]
H A Dk3-j721s2-evm-pcie1-ep.dtso1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
8 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
11 /dts-v1/;
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/soc/ti,sci_pm_domain.h>
17 #include "k3-pinctrl.h"
28 #address-cells = <2>;
29 #size-cells = <2>;
30 interrupt-parent = <&gic500>;
32 pcie1_ep: pcie-ep@2910000 {
[all …]
H A Dk3-j721e-evm-pcie0-ep.dtso1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
8 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
11 /dts-v1/;
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/soc/ti,sci_pm_domain.h>
17 #include "k3-pinctrl.h"
28 #address-cells = <2>;
29 #size-cells = <2>;
30 interrupt-parent = <&gic500>;
32 pcie0_ep: pcie-ep@2900000 {
[all …]
H A Dk3-j722s-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
12 serdes_refclk: clk-0 {
13 compatible = "fixed-clock";
14 #clock-cells = <0>;
15 clock-frequency = <0>;
21 compatible = "ti,am64-wiz-10g";
23 #address-cells = <1>;
[all …]
H A Dk3-am65-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy-am654-serdes.h>
11 compatible = "mmio-sram";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 atf-sram@0 {
21 sysfw-sram@f0000 {
25 l3cache-sram@100000 {
30 gic500: interrupt-controller@1800000 {
[all …]
/linux/Documentation/devicetree/bindings/soc/imx/
H A Dfsl,imx8mp-hsio-blk-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MP HSIO blk-ctrl
10 - Lucas Stach <l.stach@pengutronix.de>
13 The i.MX8MP HSIO blk-ctrl is a top-level peripheral providing access to
14 the NoC and ensuring proper power sequencing of the high-speed IO
15 (USB an PCIe) peripherals located in the HSIO domain of the SoC.
20 - const: fsl,imx8mp-hsio-blk-ctrl
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dti-phy.txt6 - compatible: Should be one of
7 "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
8 "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register
10 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
12 "ti,control-phy-pcie" - for pcie to support external clock for pcie and to
14 e.g. PCIE PHY in DRA7x
15 "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on
17 "ti,control-phy-usb2-am437" - if it has power down register like USB2 PHY on
19 - reg : register ranges as listed in the reg-names property
20 - reg-names: "otghs_control" for control-phy-otghs
[all …]
/linux/arch/arm/boot/dts/mediatek/
H A Dmt7629.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/mt7629-clk.h>
11 #include <dt-bindings/power/mt7622-power.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/reset/mt7629-resets.h>
18 interrupt-parent = <&sysirq>;
19 #address-cells = <1>;
[all …]
/linux/drivers/pci/controller/mobiveil/
H A Dpcie-layerscape-gen4.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe Gen4 host controller driver for NXP Layerscape SoCs
5 * Copyright 2019-2020 NXP
20 #include <linux/mfd/syscon.h>
23 #include "pcie-mobiveil.h"
37 #define to_ls_g4_pcie(x) platform_get_drvdata((x)->pdev)
45 static inline u32 ls_g4_pcie_pf_readl(struct ls_g4_pcie *pcie, u32 off) in ls_g4_pcie_pf_readl() argument
47 return ioread32(pcie->pci.csr_axi_slave_base + PCIE_PF_OFF + off); in ls_g4_pcie_pf_readl()
50 static inline void ls_g4_pcie_pf_writel(struct ls_g4_pcie *pcie, in ls_g4_pcie_pf_writel() argument
53 iowrite32(val, pcie->pci.csr_axi_slave_base + PCIE_PF_OFF + off); in ls_g4_pcie_pf_writel()
[all …]
/linux/arch/arm64/boot/dts/hisilicon/
H A Dhip06.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip06-d03";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
[all …]
H A Dhip07.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip07-d05";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt7622.dtsi6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/clock/mt7622-clk.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt7622-power.h>
14 #include <dt-bindings/reset/mt7622-reset.h>
15 #include <dt-bindings/thermal/thermal.h>
19 interrupt-parent = <&sysirq>;
20 #address-cells = <2>;
[all …]
/linux/arch/mips/boot/dts/brcm/
H A Dbcm7435.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <175625000>;
42 cpu_intc: interrupt-controller {
43 #address-cells = <0>;
44 compatible = "mti,cpu-interrupt-controller";
46 interrupt-controller;
[all …]
H A Dbcm7425.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <163125000>;
30 cpu_intc: interrupt-controller {
31 #address-cells = <0>;
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mp-clock.h>
7 #include <dt-bindings/power/imx8mp-power.h>
8 #include <dt-bindings/reset/imx8mp-reset.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/interconnect/fsl,imx8mp.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
15 #include "imx8mp-pinfunc.h"
[all …]
/linux/drivers/phy/mscc/
H A Dphy-ocelot-serdes.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
10 #include <linux/mfd/syscon.h>
19 #include <dt-bindings/phy/phy-ocelot-serdes.h>
29 /* Not used when in QSGMII or PCIe mode */
31 struct serdes_ctrl *ctrl; member
406 return -EOPNOTSUPP; in serdes_set_mode()
409 if (macro->idx != ocelot_serdes_muxes[i].idx || in serdes_set_mode()
415 macro->port != ocelot_serdes_muxes[i].port) in serdes_set_mode()
418 ret = regmap_update_bits(macro->ctrl->regs, HSIO_HW_CFG, in serdes_set_mode()
424 if (macro->idx <= SERDES1G_MAX) in serdes_set_mode()
[all …]
/linux/drivers/phy/hisilicon/
H A Dphy-hi3670-pcie.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe phy driver for Kirin 970
25 #include <linux/mfd/syscon.h>
37 /* PCIe CTRL registers */
49 /* PCIe PHY registers */
144 /* peri_crg ctrl */
176 writel(val, phy->bas in hi3670_apb_phy_readl()
[all...]
/linux/arch/arm/boot/dts/marvell/
H A Ddove.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/gpio/gpio.h>
3 #include <dt-bindings/interrupt-controller/irq.h>
8 #address-cells = <1>;
9 #size-cells = <1>;
12 interrupt-parent = <&intc>;
21 #address-cells = <1>;
22 #size-cells = <0>;
25 compatible = "marvell,pj4a", "marvell,sheeva-v7";
27 next-level-cache = <&l2>;
[all …]
/linux/arch/arm/boot/dts/qcom/
H A Dqcom-apq8064.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
5 #include <dt-bindings/clock/qcom,lcc-msm8960.h>
6 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/soc/qcom,gsbi.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
[all …]
/linux/drivers/phy/lantiq/
H A Dphy-lantiq-vrx200-pcie.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * PCIe PHY driver for Lantiq VRX200 and ARX300 SoCs.
8 * Copyright (C) 2009-2015 Lei Chuanhua <chuanhua.lei@lantiq.com>
18 #include <linux/mfd/syscon.h>
27 #include <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>
103 regmap_write(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL1, 0x120e); in ltq_vrx200_pcie_phy_common_setup()
106 regmap_write(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL2, 0x39d7); in ltq_vrx200_pcie_phy_common_setup()
107 regmap_write(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL3, 0x0900); in ltq_vrx200_pcie_phy_common_setup()
110 regmap_write(priv->phy_regmap, PCIE_PHY_RX1_EI, 0x0004); in ltq_vrx200_pcie_phy_common_setup()
111 regmap_write(priv->phy_regmap, PCIE_PHY_RX1_A_CTRL, 0x6803); in ltq_vrx200_pcie_phy_common_setup()
[all …]
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm-nsp.dtsi33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
35 #include <dt-bindings/clock/bcm-nsp.h>
38 #address-cells = <1>;
39 #size-cells = <1>;
42 interrupt-parent = <&gic>;
53 #address-cells = <1>;
54 #size-cells = <0>;
58 compatible = "arm,cortex-a9";
59 next-level-cache = <&L2>;
[all …]
/linux/drivers/phy/st/
H A Dphy-stm32-combophy.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/mfd/syscon.h>
17 #include <dt-bindings/phy/phy.h>
122 u32 min_imp = imp_lookup[imp_size - 1].microohm; in stm32_impedance_tune()
127 if (!of_property_read_u32(combophy->dev->of_node, "st,output-micro-ohms", &val)) { in stm32_impedance_tune()
129 dev_err(combophy->dev, "Invalid value %u for output ohm\n", val); in stm32_impedance_tune()
130 return -EINVAL; in stm32_impedance_tune()
138 return -EINVAL; in stm32_impedance_tune()
140 dev_dbg(combophy->dev, "Set %u micro-ohms output impedance\n", in stm32_impedance_tune()
143 regmap_update_bits(combophy->regmap, SYSCFG_PCIEPRGCR, in stm32_impedance_tune()
[all …]

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