1*f43ec89bSSiddharth Vadapalli// SPDX-License-Identifier: GPL-2.0-only OR MIT 2*f43ec89bSSiddharth Vadapalli/** 3*f43ec89bSSiddharth Vadapalli * DT Overlay for enabling PCIE1 instance in Endpoint Configuration with the 4*f43ec89bSSiddharth Vadapalli * J7 common processor board. 5*f43ec89bSSiddharth Vadapalli * 6*f43ec89bSSiddharth Vadapalli * J7 Common Processor Board Product Link: https://www.ti.com/tool/J721EXCPXEVM 7*f43ec89bSSiddharth Vadapalli * 8*f43ec89bSSiddharth Vadapalli * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ 9*f43ec89bSSiddharth Vadapalli */ 10*f43ec89bSSiddharth Vadapalli 11*f43ec89bSSiddharth Vadapalli/dts-v1/; 12*f43ec89bSSiddharth Vadapalli/plugin/; 13*f43ec89bSSiddharth Vadapalli 14*f43ec89bSSiddharth Vadapalli#include <dt-bindings/interrupt-controller/arm-gic.h> 15*f43ec89bSSiddharth Vadapalli#include <dt-bindings/soc/ti,sci_pm_domain.h> 16*f43ec89bSSiddharth Vadapalli 17*f43ec89bSSiddharth Vadapalli#include "k3-pinctrl.h" 18*f43ec89bSSiddharth Vadapalli 19*f43ec89bSSiddharth Vadapalli/* 20*f43ec89bSSiddharth Vadapalli * Since Root Complex and Endpoint modes are mutually exclusive 21*f43ec89bSSiddharth Vadapalli * disable Root Complex mode. 22*f43ec89bSSiddharth Vadapalli */ 23*f43ec89bSSiddharth Vadapalli&pcie1_rc { 24*f43ec89bSSiddharth Vadapalli status = "disabled"; 25*f43ec89bSSiddharth Vadapalli}; 26*f43ec89bSSiddharth Vadapalli 27*f43ec89bSSiddharth Vadapalli&cbass_main { 28*f43ec89bSSiddharth Vadapalli #address-cells = <2>; 29*f43ec89bSSiddharth Vadapalli #size-cells = <2>; 30*f43ec89bSSiddharth Vadapalli interrupt-parent = <&gic500>; 31*f43ec89bSSiddharth Vadapalli 32*f43ec89bSSiddharth Vadapalli pcie1_ep: pcie-ep@2910000 { 33*f43ec89bSSiddharth Vadapalli compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep"; 34*f43ec89bSSiddharth Vadapalli reg = <0x00 0x02910000 0x00 0x1000>, 35*f43ec89bSSiddharth Vadapalli <0x00 0x02917000 0x00 0x400>, 36*f43ec89bSSiddharth Vadapalli <0x00 0x0d800000 0x00 0x00800000>, 37*f43ec89bSSiddharth Vadapalli <0x00 0x18000000 0x00 0x08000000>; 38*f43ec89bSSiddharth Vadapalli reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 39*f43ec89bSSiddharth Vadapalli interrupt-names = "link_state"; 40*f43ec89bSSiddharth Vadapalli interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 41*f43ec89bSSiddharth Vadapalli max-link-speed = <3>; 42*f43ec89bSSiddharth Vadapalli num-lanes = <2>; 43*f43ec89bSSiddharth Vadapalli power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 44*f43ec89bSSiddharth Vadapalli clocks = <&k3_clks 240 6>; 45*f43ec89bSSiddharth Vadapalli clock-names = "fck"; 46*f43ec89bSSiddharth Vadapalli max-functions = /bits/ 8 <6>; 47*f43ec89bSSiddharth Vadapalli max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; 48*f43ec89bSSiddharth Vadapalli dma-coherent; 49*f43ec89bSSiddharth Vadapalli phys = <&serdes0_pcie_link>; 50*f43ec89bSSiddharth Vadapalli phy-names = "pcie-phy"; 51*f43ec89bSSiddharth Vadapalli ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; 52*f43ec89bSSiddharth Vadapalli }; 53*f43ec89bSSiddharth Vadapalli}; 54