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/linux/arch/powerpc/platforms/powermac/
H A Dcache.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * This file contains low-level cache management functions
5 * (In fact the only thing that is Apple-specific is that we assume
15 #include <asm/feature-fixups.h>
45 sync
52 sync
58 sync
60 sync
62 /* Disp-flush L1. We have a weird problem here that I never
64 * results in a non-working flush. We use that workaround for
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H A Dsleep.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * This file contains sleep low-level functions for PowerBook G3.
14 #include <asm/asm-offsets.h>
16 #include <asm/feature-fixups.h>
57 /* This gets called by via-pmu.c late during the sleep process.
96 mfsprg r4,2
110 mfdbatu r4,2
112 mfdbatl r4,2
126 mfibatu r4,2
128 mfibatl r4,2
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/linux/tools/testing/selftests/kvm/
H A Dmemslot_perf_test.c1 // SPDX-License-Identifier: GPL-2.0
3 * A memslot-related performance benchmark.
37 #define MEM_TEST_SIZE (MEM_SIZE - MEM_EXTRA_SIZE)
46 #define MEM_TEST_MAP_SIZE (MEM_SIZE_MAP - MEM_EXTRA_SIZE)
52 * 2 MiB chunk size like a typical huge page
69 * architecture slots memory-per-slot memory-o
291 struct sync_area *sync; prepare_vm() local
385 let_guest_run(struct sync_area * sync) let_guest_run() argument
392 struct sync_area *sync = (typeof(sync))MEM_SYNC_GPA; guest_spin_until_start() local
398 make_guest_exit(struct sync_area * sync) make_guest_exit() argument
405 struct sync_area *sync = (typeof(sync))MEM_SYNC_GPA; _guest_should_exit() local
418 host_perform_sync(struct sync_area * sync) host_perform_sync() argument
431 struct sync_area *sync = (typeof(sync))MEM_SYNC_GPA; guest_perform_sync() local
449 struct sync_area *sync = (typeof(sync))MEM_SYNC_GPA; guest_code_test_memslot_move() local
478 struct sync_area *sync = (typeof(sync))MEM_SYNC_GPA; guest_code_test_memslot_map() local
510 struct sync_area *sync = (typeof(sync))MEM_SYNC_GPA; guest_code_test_memslot_unmap() local
545 struct sync_area *sync = (typeof(sync))MEM_SYNC_GPA; guest_code_test_memslot_rw() local
578 test_memslot_move_prepare(struct vm_data * data,struct sync_area * sync,uint64_t * maxslots,bool isactive) test_memslot_move_prepare() argument
614 test_memslot_move_prepare_active(struct vm_data * data,struct sync_area * sync,uint64_t * maxslots) test_memslot_move_prepare_active() argument
621 test_memslot_move_prepare_inactive(struct vm_data * data,struct sync_area * sync,uint64_t * maxslots) test_memslot_move_prepare_inactive() argument
627 test_memslot_move_loop(struct vm_data * data,struct sync_area * sync) test_memslot_move_loop() argument
680 test_memslot_map_loop(struct vm_data * data,struct sync_area * sync) test_memslot_map_loop() argument
719 test_memslot_unmap_loop_common(struct vm_data * data,struct sync_area * sync,uint64_t chunk) test_memslot_unmap_loop_common() argument
746 test_memslot_unmap_loop(struct vm_data * data,struct sync_area * sync) test_memslot_unmap_loop() argument
757 test_memslot_unmap_loop_chunked(struct vm_data * data,struct sync_area * sync) test_memslot_unmap_loop_chunked() argument
765 test_memslot_rw_loop(struct vm_data * data,struct sync_area * sync) test_memslot_rw_loop() argument
808 struct sync_area *sync; test_execute() local
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/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
H A Dfsl,qe-tsa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-tsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC QE Time-slot assigner (TSA) controller
10 - Herve Codina <herve.codina@bootlin.com>
13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
14 Its purpose is to route some TDM time-slots to other internal serial
20 - enum:
21 - fsl,mpc8321-tsa
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H A Dfsl,cpm1-tsa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC CPM Time-slot assigner (TSA) controller
10 - Herve Codina <herve.codina@bootlin.com>
13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
14 Its purpose is to route some TDM time-slots to other internal serial
20 - enum:
21 - fsl,mpc885-tsa
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/linux/arch/parisc/kernel/
H A Dperf_asm.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 /* low-level asm for "intrigue" (PA8500-8700 CPU perf counters)
5 * Copyright (C) 2001 Randolph Chung <tausq at parisc-linux.org>
6 * Copyright (C) 2001 Hewlett-Packard (Grant Grundler)
46 sync ; follow ERS
100 ;* %r24 - original DR2 value
101 ;* %r1 - scratch
102 ;* %r29 - scratch
117 ; NOTE: The PCX-W ERS states that DR2_SLOW_RET must be set before any
132 ; Cacheline start (32-byte cacheline)
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/linux/drivers/video/fbdev/
H A Dcontrolfb.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
42 /* Vertical parameters are in units of 1/2 scan line */
47 struct preg vesync; /* vert end sync */
48 struct preg vssync; /* vert start sync */
51 /* Horizontal params are in units of 2 pixels */
52 struct preg hperiod; /* horiz period - 2 */
55 struct preg hesync; /* horiz end sync */
56 struct preg hssync; /* horiz start sync */
57 struct preg heq; /* half horiz sync len */
59 struct preg hserr; /* horiz period - horiz sync len */
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H A Dfm2fb.c2 * linux/drivers/video/fm2fb.c -- BSC FrameMaster II/Rainbow II frame buffer
5 * Copyright (C) 1998 Steffen A. Mork (linux-dev@morknet.de)
35 * - PAL/NTSC
36 * - interlaced/non interlaced
37 * - composite sync/sync/sync over green
40 * - 768x576 (PAL)
41 * - 768x480 (NTSC)
46 * is near to 2 MByte (the allocated address space of Zorro2).
59 * 1 2 0=video out disabled/1=video out enabled
60 * 2 4 0=normal mode as jumpered via JP8/1=complement mode
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/linux/Documentation/devicetree/bindings/sound/
H A Dqcom,q6dsp-lpass-ports.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/qcom,q6dsp-lpass-ports.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
18 - qcom,q6afe-dais
20 '#sound-dai-cells':
23 '#address-cells':
26 '#size-cells':
31 '^dai@[0-9]+$':
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/linux/arch/powerpc/kernel/
H A Dl2cr_6xx.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 Copyright © 1997-1998 by PowerLogix R & D, Inc.
9 - First public release, contributed by PowerLogix.
12 - Terry: Made sure code disabled interrupts before running. (Previously
14 - Terry: Updated for tentative G4 support. 4MB of memory is now flushed
15 instead of 2MB. (Prob. only 3 is necessary).
16 - Terry: Updated for workaround to HID0[DPM] processor bug
20 - Terry: Added isync to correct for an errata.
23 - DanM: Finally added the 7450 patch I've had for the past
29 Please e-mail updates to this file to me, thanks!
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H A Dcpu_setup_6xx.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
13 #include <asm/asm-offsets.h>
16 #include <asm/feature-fixups.h>
100 bne 1f /* don't invalidate the D-cache */
102 1: sync
104 sync
106 sync
118 sync
120 sync /* on 604e/604r */
122 sync
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/linux/drivers/gpu/drm/i915/selftests/
H A Di915_syncmap.c41 for (d = 0; d < depth - 1; d++) { in __sync_print()
42 if (last & BIT(depth - d - 1)) in __sync_print()
47 *sz -= len; in __sync_print()
49 len = scnprintf(buf, *sz, "%x-> ", idx); in __sync_print()
51 *sz -= len; in __sync_print()
55 len = scnprintf(buf, *sz, "0x%016llx", p->prefix << p->height << SHIFT); in __sync_print()
57 *sz -= len; in __sync_print()
58 X = (p->height + SHIFT) / 4; in __sync_print()
59 scnprintf(buf - X, *sz + X, "%*s", X, "XXXXXXXXXXXXXXXXX"); in __sync_print()
61 if (!p->height) { in __sync_print()
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/linux/arch/mips/alchemy/common/
H A Dsleeper.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
26 sw $2, PT_R2(sp)
74 sync
76 sync
103 sync
105 sync
107 sync
129 sync
131 sync
133 /* wait for sdram to enter self-refresh mode */
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/linux/arch/powerpc/platforms/52xx/
H A Dlite5200_sleep.S1 /* SPDX-License-Identifier: GPL-2.0 */
32 sync; \
41 /* ---------------------------------------------------------------------- */
42 /* low-power mode with help of M68HLC908QT1 */
50 /* setup wakeup address for u-boot at physical location 0x0 */
60 * 0xf0 (0xe0->0x100 gets overwritten when BDI connected;
62 * WARNING: self-refresh doesn't seem to work when BDI2000 is connected,
80 li r3, (sram_code_end - sram_code)/4
99 sync; isync;
101 sync; isync;
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/linux/arch/mips/include/asm/
H A Dsync.h1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * sync types are defined by the MIPS64 Instruction Set documentation in Volume
7 * II-A of the MIPS Architecture Reference Manual, which can be found here:
9 * https://www.mips.com/?do-download=the-mips64-instruction-set-v6-06
16 * 2) Ordering barriers, which only ensure that affected memory operations
27 * actually need to complete - they just need to get far enough that all
43 * No sync instruction at all; used to allow code to nullify the effect of the
46 #define __SYNC_none -1
49 * A full completion barrier; all memory accesses appearing prior to this sync
51 * appearing after this sync instruction in program order.
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/linux/Documentation/fb/
H A Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
15 # Sync Width 3.813 us 0.064 ms
16 # 12 chars 2 lines
18 # 2 chars 10 lines
28 mode "640x480-60"
31 timings 39722 48 16 33 10 96 2 endmode mode "480x640-60"
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
40 # Sync Width 2.032 us 0.080 ms
43 # 2 chars 1 lines
52 mode "640x480-75"
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/linux/net/caif/
H A Dcfserl.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) ST-Ericsson AB 2010
25 spinlock_t sync; member
45 this->layer.receive = cfserl_receive; in cfserl_create()
46 this->layer.transmit = cfserl_transmit; in cfserl_create()
47 this->layer.ctrlcmd = cfserl_ctrlcmd; in cfserl_create()
48 this->usestx = use_stx; in cfserl_create()
49 spin_lock_init(&this->sync); in cfserl_create()
50 snprintf(this->layer.name, CAIF_LAYER_NAME_SZ, "ser1"); in cfserl_create()
51 return &this->layer; in cfserl_create()
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/linux/drivers/tty/serial/
H A Dip22zilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
31 #define BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2))
32 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
41 #define R2 2
85 /* Write Register #2 (Interrupt Vector) */
90 #define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
106 #define SYNC_ENAB 0 /* Sync Modes Enable */
109 #define SB2 0xc /* 2 stop bits/char */
111 #define MONSYNC 0 /* 8 Bit Sync character */
112 #define BISYNC 0x10 /* 16 bit sync character */
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H A Dsunzilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
23 #define BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2))
24 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
33 #define R2 2
77 /* Write Register #2 (Interrupt Vector) */
82 #define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
98 #define SYNC_ENAB 0 /* Sync Modes Enable */
101 #define SB2 0xc /* 2 stop bits/char */
103 #define MONSYNC 0 /* 8 Bit Sync character */
104 #define BISYNC 0x10 /* 16 bit sync character */
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/linux/drivers/gpu/drm/xe/
H A Dxe_sync.h1 /* SPDX-License-Identifier: MIT */
20 #define SYNC_PARSE_FLAG_DISALLOW_USER_FENCE BIT(2)
23 struct xe_sync_entry *sync,
28 int xe_sync_entry_add_deps(struct xe_sync_entry *sync,
30 void xe_sync_entry_signal(struct xe_sync_entry *sync,
32 void xe_sync_entry_cleanup(struct xe_sync_entry *sync);
34 xe_sync_in_fence_get(struct xe_sync_entry *sync, int num_sync,
37 static inline bool xe_sync_is_ufence(struct xe_sync_entry *sync) in xe_sync_is_ufence() argument
39 return !!sync->ufence; in xe_sync_is_ufence()
43 struct xe_user_fence *xe_sync_ufence_get(struct xe_sync_entry *sync);
/linux/arch/sparc/kernel/
H A Dcherrs.S1 /* SPDX-License-Identifier: GPL-2.0 */
8 membar #Sync
12 membar #Sync
16 .size cheetah_fecc_trap_vector,.-cheetah_fecc_trap_vector
21 membar #Sync
25 membar #Sync
29 .size cheetah_fecc_trap_vector_tl1,.-cheetah_fecc_trap_vector_tl1
34 membar #Sync
38 membar #Sync
42 .size cheetah_cee_trap_vector,.-cheetah_cee_trap_vector
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/linux/include/linux/spi/
H A Dsh_msiof.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 #define SITMDR2 0x04 /* Transmit Mode Register 2 */
12 #define SIRMDR2 0x14 /* Receive Mode Register 2 */
21 #define SITDR2 0x4c /* Transmit Control Data Register 2 (SH, A1) */
24 #define SIRDR2 0x5c /* Receive Control Data Register 2 (SH, A1) */
29 #define SIMDR1_SYNCMD GENMASK(29, 28) /* SYNC Mode */
30 #define SIMDR1_SYNCMD_PULSE 0U /* Frame start sync pulse */
31 #define SIMDR1_SYNCMD_SPI 2U /* Level mode/SPI */
33 #define SIMDR1_SYNCAC BIT(25) /* Sync Polarity (1 = Active-low) */
36 #define SIMDR1_SYNCDL GENMASK(18, 16) /* Frame Sync Signal Timing Delay */
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/linux/Documentation/devicetree/bindings/iio/imu/
H A Dadi,adis16475.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nuno Sá <nuno.sa@analog.com>
14 https://www.analog.com/media/en/technical-documentation/data-sheets/ADIS16475.pdf
19 - adi,adis16475-1
20 - adi,adis16475-2
21 - adi,adis16475-3
22 - adi,adis16477-1
23 - adi,adis16477-2
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/linux/drivers/net/ethernet/xscale/
H A Dixp46x_ts.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
26 u32 control; /* 0x00 Time Sync Control Register */
27 u32 event; /* 0x04 Time Sync Event Register */
28 u32 addend; /* 0x08 Time Sync Addend Register */
29 u32 accum; /* 0x0C Time Sync Accumulator Register */
30 u32 test; /* 0x10 Time Sync Test Register */
46 /* 0x00 Time Sync Control Register Bits */
48 #define TSCR_ASM (1<<2)
52 /* 0x04 Time Sync Event Register Bits */
54 #define TSER_SNS (1<<2)
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/linux/Documentation/input/devices/
H A Dwalkera0701.rst2 Walkera WK-0701 transmitter
5 Walkera WK-0701 transmitter is supplied with a ready to fly Walkera
10 http://zub.fei.tuke.sk/walkera-wk0701/
13 cg-clone http://zub.fei.tuke.sk/GIT/walkera0701-joystick
19 At back side of transmitter S-video connector can be found. Modulation
20 pulses from processor to HF part can be found at pin 2 of this connector,
26 Walkera WK-0701 TX S-VIDEO connector::
29 __ __ S-video: canon25
30 / |_| \ pin 2 (signal) NPN parport
32 ( O 2 1 O ) | C
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