Lines Matching +full:sync +full:- +full:2
1 /* SPDX-License-Identifier: GPL-2.0 */
31 #define BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2))
32 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
41 #define R2 2
85 /* Write Register #2 (Interrupt Vector) */
90 #define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
106 #define SYNC_ENAB 0 /* Sync Modes Enable */
109 #define SB2 0xc /* 2 stop bits/char */
111 #define MONSYNC 0 /* 8 Bit Sync character */
112 #define BISYNC 0x10 /* 16 bit sync character */
113 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
114 #define EXTSYNC 0x30 /* External Sync Mode */
126 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
136 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
138 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
144 #define NV 2 /* No Vector */
154 #define BIT6 1 /* 6 bit/8bit sync */
155 #define LOOPMODE 2 /* SDLC Loop mode */
168 #define TRxCBR 2 /* TRxC = BR Generator Output */
187 #define BRSRC 2 /* Baud rate generator source */
200 #define ZCIE 2 /* Zero count IE */
202 #define SYNCIE 0x10 /* Sync/hunt IE */
213 #define SYNC 0x10 /* Sync/hunt */ macro
228 #define RES28 0x0 /* 2/8 */
235 /* Read Register 2 (channel b only) - Interrupt vector */
257 #define ONLOOP 2 /* On loop */
269 #define ZS_CLEARERR(channel) do { writeb(ERR_RES, &channel->control); \
272 #define ZS_CLEARSTAT(channel) do { writeb(RES_EXT_INT, &channel->control); \
275 #define ZS_CLEARFIFO(channel) do { readb(&channel->data); \
276 udelay(2); \
277 readb(&channel->data); \
278 udelay(2); \
279 readb(&channel->data); \
280 udelay(2); } while(0)