1 /* SPDX-License-Identifier: GPL-2.0 */
24 #define TSB_EXTENSION_P		0x0000000000000048 /* Ultra-III and later		*/
25 #define TSB_EXTENSION_S		0x0000000000000050 /* Ultra-III and later, D-TLB only	*/
26 #define TSB_EXTENSION_N		0x0000000000000058 /* Ultra-III and later		*/
27 #define TLB_TAG_ACCESS_EXT	0x0000000000000060 /* Ultra-III+ and later		*/
38 #define SPITFIRE_HIGHEST_LOCKED_TLBENT	(64 - 1)
39 #define CHEETAH_HIGHEST_LOCKED_TLBENT	(16 - 1)
62 #define CPU_ID_NIAGARA2		('2')
76 	cheetah_plus = 2,
99 	__asm__ __volatile__("stxa	%0, [%1] %2\n\t"  in spitfire_put_dcache_tag()
100 			     "membar	#Sync"  in spitfire_put_dcache_tag()
113 	__asm__ __volatile__("stxa	%0, [%1] %2\n\t"  in spitfire_put_icache_tag()
114 			     "membar	#Sync"  in spitfire_put_icache_tag()
123 	__asm__ __volatile__("ldxa	[%1] %2, %0"  in spitfire_get_dtlb_data()
137 	__asm__ __volatile__("ldxa	[%1] %2, %0"  in spitfire_get_dtlb_tag()
145 	__asm__ __volatile__("stxa	%0, [%1] %2\n\t"  in spitfire_put_dtlb_data()
146 			     "membar	#Sync"  in spitfire_put_dtlb_data()
156 	__asm__ __volatile__("ldxa	[%1] %2, %0"  in spitfire_get_itlb_data()
170 	__asm__ __volatile__("ldxa	[%1] %2, %0"  in spitfire_get_itlb_tag()
178 	__asm__ __volatile__("stxa	%0, [%1] %2\n\t"  in spitfire_put_itlb_data()
179 			     "membar	#Sync"  in spitfire_put_itlb_data()
188 			     "membar	#Sync"  in spitfire_flush_dtlb_nucleus_page()
196 			     "membar	#Sync"  in spitfire_flush_itlb_nucleus_page()
201 /* Cheetah has "all non-locked" tlb flushes. */
205 			     "membar	#Sync"  in cheetah_flush_dtlb_all()
213 			     "membar	#Sync"  in cheetah_flush_itlb_all()
218 /* Cheetah has a 4-tlb layout so direct access is a bit different.
223  * The third TLB is for data accesses to 8K non-locked translations, is
224  * 2 way assosciative, and holds 512 entries.  The fourth TLB is for
225  * instruction accesses to 8K non-locked translations, is 2 way
230  * the problem for me. -DaveM
236 	__asm__ __volatile__("ldxa	[%1] %2, %%g0\n\t"  in cheetah_get_ldtlb_data()
237 			     "ldxa	[%1] %2, %0"  in cheetah_get_ldtlb_data()
249 	__asm__ __volatile__("ldxa	[%1] %2, %%g0\n\t"  in cheetah_get_litlb_data()
250 			     "ldxa	[%1] %2, %0"  in cheetah_get_litlb_data()
262 	__asm__ __volatile__("ldxa	[%1] %2, %0"  in cheetah_get_ldtlb_tag()
274 	__asm__ __volatile__("ldxa	[%1] %2, %0"  in cheetah_get_litlb_tag()
284 	__asm__ __volatile__("stxa	%0, [%1] %2\n\t"  in cheetah_put_ldtlb_data()
285 			     "membar	#Sync"  in cheetah_put_ldtlb_data()
294 	__asm__ __volatile__("stxa	%0, [%1] %2\n\t"  in cheetah_put_litlb_data()
295 			     "membar	#Sync"  in cheetah_put_litlb_data()
306 	__asm__ __volatile__("ldxa	[%1] %2, %%g0\n\t"  in cheetah_get_dtlb_data()
307 			     "ldxa	[%1] %2, %0"  in cheetah_get_dtlb_data()
318 	__asm__ __volatile__("ldxa	[%1] %2, %0"  in cheetah_get_dtlb_tag()
326 	__asm__ __volatile__("stxa	%0, [%1] %2\n\t"  in cheetah_put_dtlb_data()
327 			     "membar	#Sync"  in cheetah_put_dtlb_data()
338 	__asm__ __volatile__("ldxa	[%1] %2, %%g0\n\t"  in cheetah_get_itlb_data()
339 			     "ldxa	[%1] %2, %0"  in cheetah_get_itlb_data()
341 			     : "r" ((2 << 16) | (entry << 3)),  in cheetah_get_itlb_data()
351 	__asm__ __volatile__("ldxa	[%1] %2, %0"  in cheetah_get_itlb_tag()
353 			     : "r" ((2 << 16) | (entry << 3)), "i" (ASI_ITLB_TAG_READ));  in cheetah_get_itlb_tag()
359 	__asm__ __volatile__("stxa	%0, [%1] %2\n\t"  in cheetah_put_itlb_data()
360 			     "membar	#Sync"  in cheetah_put_itlb_data()
362 			     : "r" (data), "r" ((2 << 16) | (entry << 3)),  in cheetah_put_itlb_data()