Lines Matching +full:sync +full:- +full:2
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 Copyright © 1997-1998 by PowerLogix R & D, Inc.
9 - First public release, contributed by PowerLogix.
12 - Terry: Made sure code disabled interrupts before running. (Previously
14 - Terry: Updated for tentative G4 support. 4MB of memory is now flushed
15 instead of 2MB. (Prob. only 3 is necessary).
16 - Terry: Updated for workaround to HID0[DPM] processor bug
20 - Terry: Added isync to correct for an errata.
23 - DanM: Finally added the 7450 patch I've had for the past
29 Please e-mail updates to this file to me, thanks!
36 #include <asm/feature-fixups.h>
54 _setL2CR(0) - disables the cache
55 _setL2CR(0xB3A04000) - enables my G3 upgrade card:
56 - L2E set to turn on the cache
57 - L2SIZ set to 1MB
58 - L2CLK set to 1:1
59 - L2RAM set to pipelined synchronous late-write
60 - L2I set to perform a global invalidation
61 - L2OH set to 0.5 nS
62 - L2DF set because this upgrade card
76 The size is read-only for these processors with internal L2
78 -- Dan
86 * -- paulus.
91 li r3,-1
100 sync
107 sync
118 sync
120 sync
132 beq 2f
140 /**** Might be a good idea to set L2DO here - to prevent instructions
156 sync
158 sync
182 sync
188 2:
196 sync
198 sync
202 21: sync
209 sync
211 sync
229 sync
231 sync
240 sync
246 sync
248 sync
254 sync
256 sync
282 li r3,-1
290 sync
296 sync
304 rlwinm r3,r3,0,2,31 /* Turn off the enable & PE bits */
308 beq 2f
324 2:
326 sync
328 sync
332 sync
335 sync
344 sync
346 sync
357 sync
371 sync
392 /* --- End of PowerLogix code ---
396 /* flush_disable_L1() - Flush and disable L1 cache
406 sync
419 sync
429 sync
435 sync
439 /* inval_enable_L1 - Invalidate and enable L1 cache
449 sync
454 sync