Lines Matching +full:sync +full:- +full:2
1 /* SPDX-License-Identifier: GPL-2.0 */
23 #define BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2))
24 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
33 #define R2 2
77 /* Write Register #2 (Interrupt Vector) */
82 #define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
98 #define SYNC_ENAB 0 /* Sync Modes Enable */
101 #define SB2 0xc /* 2 stop bits/char */
103 #define MONSYNC 0 /* 8 Bit Sync character */
104 #define BISYNC 0x10 /* 16 bit sync character */
105 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
106 #define EXTSYNC 0x30 /* External Sync Mode */
118 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
128 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
130 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
134 #define AUTO_EOM_RST 2 /* Automatic EOM Reset */
145 #define NV 2 /* No Vector */
156 #define BIT6 1 /* 6 bit/8bit sync */
157 #define LOOPMODE 2 /* SDLC Loop mode */
170 #define TRxCBR 2 /* TRxC = BR Generator Output */
189 #define BRSRC 2 /* Baud rate generator source */
203 #define ZCIE 2 /* Zero count IE */
206 #define SYNCIE 0x10 /* Sync/hunt IE */
217 #define SYNC 0x10 /* Sync/hunt */ macro
232 #define RES28 0x0 /* 2/8 */
239 /* Read Register 2 (channel b only) - Interrupt vector */
265 #define ONLOOP 2 /* On loop */
277 #define ZS_CLEARERR(channel) do { sbus_writeb(ERR_RES, &channel->control); \
280 #define ZS_CLEARSTAT(channel) do { sbus_writeb(RES_EXT_INT, &channel->control); \
283 #define ZS_CLEARFIFO(channel) do { sbus_readb(&channel->data); \
284 udelay(2); \
285 sbus_readb(&channel->data); \
286 udelay(2); \
287 sbus_readb(&channel->data); \
288 udelay(2); } while(0)