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/linux/Documentation/devicetree/bindings/dma/
H A Dmv-xor.txt1 * Marvell XOR engines
4 - compatible: Should be one of the following:
5 - "marvell,orion-xor"
6 - "marvell,armada-380-xor"
7 - "marvell,armada-3700-xor".
8 - reg: Should contain registers location and length (two sets)
11 - clocks: pointer to the reference clock
13 The DT node must also contains sub-nodes for each XOR channel that the
14 XOR engine has. Those sub-nodes have the following required
16 - interrupts: interrupt of the XOR channel
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/linux/include/uapi/drm/
H A Dxe_drm.h1 /* SPDX-License-Identifier: MIT */
17 * subject to backwards-compatibility constraints.
28 * The diagram below represents a high-level simplification of a discrete
56 * │ │ │ └─DSS─┘ └─DSS─┘ └─DSS─┘ └─────Engines─────┘ │ │ │ │ │ │ │
72 * - &DRM_IOCTL_XE_DEVICE_QUERY
73 * - &DRM_IOCTL_XE_GEM_CREATE
74 * - &DRM_IOCTL_XE_GEM_MMAP_OFFSET
75 * - &DRM_IOCTL_XE_VM_CREATE
76 * - &DRM_IOCTL_XE_VM_DESTROY
77 * - &DRM_IOCTL_XE_VM_BIND
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H A Di915_drm.h9 * distribute, sub license, and/or sell copies of the Software, and to
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
37 * subject to backwards-compatibility constraints.
43 * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch
46 * track of these events, and if a specific cache-line seems to have a
48 * intel-gpu-tools. The value supplied with the event is always 1.
50 * I915_ERROR_UEVENT - Generated upon error detection, currently only via
57 * I915_RESET_UEVENT - Event is generated just before an attempt to reset the
66 * struct i915_user_extension - Base class for defining a chain of extensions
82 * .. code-block:: C
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H A Dhabanalabs_accel.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
3 * Copyright 2016-2023 HabanaLabs, Ltd.
14 * Defines that are asic-specific but constitutes as ABI between kernel driver
195 * stream id is a running number from 0 up to (N-1), where N is the number
656 * enum hl_goya_dma_direction - Direction of DMA operation inside a LIN_DMA packet that is
683 * enum hl_device_status - Device status information.
715 * Notifier event values - for the notification mechanism and the HL_INFO_GET_EVENTS command
717 * HL_NOTIFIER_EVENT_TPC_ASSERT - Indicates TPC assert event
718 * HL_NOTIFIER_EVENT_UNDEFINED_OPCODE - Indicates undefined operation code
719 * HL_NOTIFIER_EVENT_DEVICE_RESET - Indicates device requires a reset
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/linux/Documentation/devicetree/bindings/arm/tegra/
H A Dnvidia,tegra194-cbb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-cbb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sumit Gupta <sumitg@nvidia.com>
15 multiple hierarchical sub-NOCs (Network-on-Chip) and connects various
20 "AON-NOC, SCE-NOC, RCE-NOC, BPMP-NOC, CV-NOC" and "CBB Central NOC"
28 - For CCPLEX (CPU Complex) initiator, the driver sets ERD bit. So, the
31 - For other initiators, the ERD is disabled. So, the access issuing
34 include all engines using Cortex-R5 (which is ARMv7 CPU cluster) and
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/linux/drivers/gpu/drm/sun4i/
H A Dsun8i_mixer.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
16 #define SUN8I_MIXER_SIZE(w, h) (((h) - 1) << 16 | ((w) - 1))
111 /* format 12 is semi-planar YUV411 UVUV */
112 /* format 13 is semi-planar YUV411 VUVU */
119 /* format 20 is packed YVU444 10-bit */
120 /* format 21 is packed YUV444 10-bit */
123 * Sub-engines listed bellow are unused for now. The EN registers are here only
124 * to be used to disable these sub-engines.
155 * struct sun8i_mixer_cfg - mixer HW configuration
217 return mixer->cfg->is_de3 ? DE3_BLD_BASE : DE2_BLD_BASE; in sun8i_blender_base()
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H A Dsun8i_mixer.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <linux/dma-mapping.h>
250 return -EINVAL; in sun8i_mixer_drm_format_to_hw()
255 u32 ch_base = sun8i_channel_base(layer->mixer, layer->channel); in sun8i_layer_enable()
258 if (layer->type == SUN8I_LAYER_TYPE_UI) { in sun8i_layer_enable()
261 reg = SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch_base, layer->overlay); in sun8i_layer_enable()
265 reg = SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, layer->overlay); in sun8i_layer_enable()
268 regmap_update_bits(layer->mixer->engine.regs, reg, mask, val); in sun8i_layer_enable()
283 drm_for_each_plane(plane, state->dev) { in sun8i_mixer_commit()
288 if (!(plane->possible_crtcs & drm_crtc_mask(crtc)) || layer->mixer != mixer) in sun8i_mixer_commit()
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/linux/drivers/dma/idxd/
H A Dinit.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/dma-mapping.h>
13 #include <linux/io-64-nonatomic-lo-hi.h>
25 MODULE_DESCRIPTION("Intel Data Streaming Accelerator and In-Memory Analytics Accelerator common dri…
51 .user_submission_safe = false, /* See INTEL-SA-01084 security advisory */
62 .user_submission_safe = false, /* See INTEL-SA-01084 security advisory */
72 /* DSA on GNR-D platforms */
89 struct pci_dev *pdev = idxd->pdev; in idxd_setup_interrupts()
90 struct device *dev = &pdev->dev; in idxd_setup_interrupts()
97 dev_err(dev, "Not MSI-X interrupt capable.\n"); in idxd_setup_interrupts()
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/linux/tools/include/uapi/drm/
H A Di915_drm.h9 * distribute, sub license, and/or sell copies of the Software, and to
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
37 * subject to backwards-compatibility constraints.
43 * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch
46 * track of these events, and if a specific cache-line seems to have a
48 * intel-gpu-tools. The value supplied with the event is always 1.
50 * I915_ERROR_UEVENT - Generated upon error detection, currently only via
57 * I915_RESET_UEVENT - Event is generated just before an attempt to reset the
66 * struct i915_user_extension - Base class for defining a chain of extensions
82 * .. code-block:: C
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/linux/Documentation/devicetree/bindings/net/
H A Dfsl,fman.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
13 Due to the fact that the FMan is an aggregation of sub-engines (ports, MACs,
19 - fsl,fman
26 cell-index:
31 The cell-index value may be used by the SoC, to identify the
33 there's a description of the cell-index use in each SoC:
35 - P1023:
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/linux/drivers/gpu/drm/i915/gt/
H A Dintel_context_types.h1 /* SPDX-License-Identifier: MIT */
71 struct intel_context *(*create_parallel)(struct intel_engine_cs **engines,
95 __intel_context_inflight(READ_ONCE((ce)->inflight))
97 __intel_context_inflight_count(READ_ONCE((ce)->inflight))
166 unsigned int active_count; /* protected by timeline->mutex */
169 struct mutex pin_mutex; /* guards pinning and associated on-gpuing */
184 * This is only used if this is a perma-pinned kernel context and
229 * with the GuC, protected by guc->submission_state.lock
235 * guc->submission_state.lock
239 * @link: in guc->guc_id_list when the guc_id has no refs but is
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/linux/drivers/gpu/drm/xe/
H A Dxe_vm_types.h1 /* SPDX-License-Identifier: MIT */
12 #include <linux/dma-resv.h>
49 /** struct xe_userptr - User pointer */
65 /** @unmap_mutex: Mutex protecting dma-unmapping */
69 * write: vm->userptr.notifier_lock in read mode and vm->resv held.
70 * read: vm->userptr.notifier_lock in write mode or vm->resv held.
73 /** @mapped: Whether the @sgt sg-table is dma-mapped. Protected by @unmap_mutex. */
111 * protected by vm->lock, vm->resv and for userptrs,
112 * vm->userptr.notifier_lock for writing. Needs either for reading,
113 * but if reading is done under the vm->lock only, it needs to be held
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/linux/drivers/ata/
H A Dlibahci_platform.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2004-2005 Red Hat, Inc.
37 * ahci_platform_enable_phys - Enable PHYs
40 * This function enables all the PHYs found in hpriv->phys, if any.
51 for (i = 0; i < hpriv->nports; i++) { in ahci_platform_enable_phys()
55 rc = phy_init(hpriv->phys[i]); in ahci_platform_enable_phys()
59 rc = phy_set_mode(hpriv->phys[i], PHY_MODE_SATA); in ahci_platform_enable_phys()
61 phy_exit(hpriv->phys[i]); in ahci_platform_enable_phys()
65 rc = phy_power_on(hpriv->phys[i]); in ahci_platform_enable_phys()
67 phy_exit(hpriv->phys[i]); in ahci_platform_enable_phys()
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/linux/drivers/accel/habanalabs/common/
H A Dhabanalabs.h1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright 2016-2023 HabanaLabs, Ltd.
19 #include <linux/dma-direction.h>
28 #include <linux/io-64-nonatomic-lo-hi.h>
30 #include <linux/dma-buf.h>
45 * bits[63:59] - Encode mmap type
46 * bits[45:0] - mmap offset value
51 #define HL_MMAP_TYPE_SHIFT (59 - PAGE_SHIFT)
110 * enum hl_mmu_page_table_location - mmu page table location
111 * @MMU_DR_PGT: page-table is located on device DRAM.
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/linux/drivers/base/
H A Dcomponent.c1 // SPDX-License-Identifier: GPL-2.0
16 * The component helper allows drivers to collect a pile of sub-devices,
20 * subsystem-specific way to find a device is not available: The component
24 * the SoC on various components (scanout engines, blending blocks, transcoders
85 struct aggregate_device *m = s->private; in component_devices_show()
86 struct component_match *match = m->match; in component_devices_show()
90 seq_printf(s, "%-50s %20s\n", "aggregate_device name", "status"); in component_devices_show()
91 seq_puts(s, "-----------------------------------------------------------------------\n"); in component_devices_show()
92 seq_printf(s, "%-50s %20s\n\n", in component_devices_show()
93 dev_name(m->parent), m->bound ? "bound" : "not bound"); in component_devices_show()
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/linux/include/linux/mtd/
H A Drawnand.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
75 #define NAND_CMD_NONE -1
84 #define NAND_DATA_IFACE_CHECK_ONLY -1
98 * ecc.correct() returns -EBADMSG.
124 * Chip requires ready check on read (for auto-incremented sequential read).
142 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
174 * In case your controller is implementing ->legacy.cmd_ctrl() and is relying
175 * on the default ->cmdfunc() implementation, you may want to let the core
208 * Some controllers with pipelined ECC engines override the BBM marker with
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/linux/drivers/gpu/drm/amd/display/dc/resource/dcn314/
H A Ddcn314_resource.c1 // SPDX-License-Identifier: MIT
122 dc->ctx->logger
893 .dwb_fi_phase = -1, // -1 = disable,
960 return &dpp->base; in dcn31_dpp_create()
980 return &opp->base; in dcn31_opp_create()
998 ctx->dc->caps.extended_aux_timeout_support); in dcn31_aux_engine_create()
1000 return &aux_engine->base; in dcn31_aux_engine_create()
1075 return &mpc30->base; in dcn31_mpc_create()
1098 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; in dcn31_hubbub_create()
1100 vmid->ctx = ctx; in dcn31_hubbub_create()
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/linux/drivers/gpu/drm/amd/display/dc/resource/dcn316/
H A Ddcn316_resource.c868 .dwb_fi_phase = -1, // -1 = disable,
918 return &dpp->base; in dcn31_dpp_create()
938 return &opp->base; in dcn31_opp_create()
956 ctx->dc->caps.extended_aux_timeout_support); in dcn31_aux_engine_create()
958 return &aux_engine->base; in dcn31_aux_engine_create()
1011 return &mpc30->base; in dcn31_mpc_create()
1034 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; in dcn31_hubbub_create()
1036 vmid->ctx = ctx; in dcn31_hubbub_create()
1038 vmid->regs = &vmid_regs[i]; in dcn31_hubbub_create()
1039 vmid->shifts = &vmid_shifts; in dcn31_hubbub_create()
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/linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/
H A Ddcn31_resource.c107 dc->ctx->logger
356 /* Some encoders won't be initialized here - but they're logical, not physical. */
873 .dwb_fi_phase = -1, // -1 = disable,
926 return &dpp->base; in dcn31_dpp_create()
946 return &opp->base; in dcn31_opp_create()
964 ctx->dc->caps.extended_aux_timeout_support); in dcn31_aux_engine_create()
966 return &aux_engine->base; in dcn31_aux_engine_create()
1019 return &mpc30->base; in dcn31_mpc_create()
1042 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; in dcn31_hubbub_create()
1044 vmid->ctx = ctx; in dcn31_hubbub_create()
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/linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/
H A Ddcn35_resource.c1 /* SPDX-License-Identifier: MIT */
127 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
150 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
153 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
200 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg]
733 .dwb_fi_phase = -1, // -1 = disable,
828 ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp); in dcn35_dpp_create()
829 return &dpp->base; in dcn35_dpp_create()
858 dcn35_opp_set_fgcg(opp, ctx->dc->debug.enable_fine_grain_clock_gating.bits.opp); in dcn35_opp_create()
860 return &opp->base; in dcn35_opp_create()
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/linux/drivers/gpu/drm/amd/display/dc/resource/dcn36/
H A Ddcn36_resource.c1 /* SPDX-License-Identifier: MIT */
112 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
135 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
138 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
185 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg]
714 .dwb_fi_phase = -1, // -1 = disable,
809 ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp); in dcn35_dpp_create()
810 return &dpp->base; in dcn35_dpp_create()
839 dcn35_opp_set_fgcg(opp, ctx->dc->debug.enable_fine_grain_clock_gating.bits.opp); in dcn35_opp_create()
841 return &opp->base; in dcn35_opp_create()
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/linux/drivers/gpu/drm/amd/display/dc/resource/dcn351/
H A Ddcn351_resource.c1 /* SPDX-License-Identifier: MIT */
107 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
130 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
133 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
180 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg]
713 .dwb_fi_phase = -1, // -1 = disable,
808 ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp); in dcn35_dpp_create()
809 return &dpp->base; in dcn35_dpp_create()
838 dcn35_opp_set_fgcg(opp, ctx->dc->debug.enable_fine_grain_clock_gating.bits.opp); in dcn35_opp_create()
840 return &opp->base; in dcn35_opp_create()
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/linux/drivers/gpu/drm/i915/
H A Di915_drv.h1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
12 * distribute, sub license, and/or sell copies of the Software, and to
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
208 * Chaining user engines happens in multiple stages, starting with a
209 * simple lock-less linked list created by intel_engine_add_user(),
215 * in question runs before or after intel_engines_driver_register() --
250 * wq - Driver workqueue for GEM.
259 * unordered_wq - internal workqueue for unordered work
374 return i915->gt[0]; in to_gt()
381 for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\
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/linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/
H A Ddcn401_resource.c1 // SPDX-License-Identifier: MIT
95 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
123 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
126 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
172 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg]
186 (ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
697 .dwb_fi_phase = -1, // -1 = disable,
762 ctx->dc->caps.extended_aux_timeout_support); in dcn401_aux_engine_create()
764 return &aux_engine->base; in dcn401_aux_engine_create()
817 clk_src->base.dp_clk_src = dp_clk_src; in dcn401_clock_source_create()
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/linux/drivers/net/can/peak_canfd/
H A Dpeak_pciefd_main.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Stephane Grosjean <s.grosjean@peak-system.com>
7 * Copyright (C) 2001-2006 PEAK System-Technik GmbH
22 MODULE_AUTHOR("Stephane Grosjean <s.grosjean@peak-system.com>");
23 MODULE_DESCRIPTION("Socket-CAN driver for PEAK PCAN PCIe/M.2 FD family cards");
30 #define PCAN_CPCIEFD_ID 0x0014 /* for Compact-PCI Serial slot cards */
31 #define PCAN_PCIE104FD_ID 0x0017 /* for PCIe-104 Express slot cards */
32 #define PCAN_MINIPCIEFD_ID 0x0018 /* for mini-PCIe slot cards */
59 /* CAN-FD channel addresses */
64 /* CAN-FD channel registers */
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