| /linux/include/uapi/drm/ |
| H A D | xe_drm.h | 1 /* SPDX-License-Identifier: MIT */
17 * subject to backwards-compatibility constraints.
28 * The diagram below represents a high-level simplification of a discrete
56 * │ │ │ └─DSS─┘ └─DSS─┘ └─DSS─┘ └─────Engines─────┘ │ │ │ │ │ │ │
72 * - &DRM_IOCTL_XE_DEVICE_QUERY
73 * - &DRM_IOCTL_XE_GEM_CREATE
74 * - &DRM_IOCTL_XE_GEM_MMAP_OFFSET
75 * - &DRM_IOCTL_XE_VM_CREATE
76 * -
272 struct drm_xe_engine engines[]; global() member
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| H A D | i915_drm.h | 9 * distribute, sub license, and/or sell copies of the Software, and to
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
37 * subject to backwards-compatibility constraints.
43 * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch
46 * track of these events, and if a specific cache-line seems to have a
48 * intel-gpu-tools. The value supplied with the event is always 1.
50 * I915_ERROR_UEVENT - Generated upon error detection, currently only via
57 * I915_RESET_UEVENT - Event is generated just before an attempt to reset the
66 * struct i915_user_extension - Base class for defining a chain of extensions
82 * .. code-block:: C
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| H A D | habanalabs_accel.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
3 * Copyright 2016-2023 HabanaLabs, Ltd.
14 * Defines that are asic-specific but constitutes as ABI between kernel driver
195 * stream id is a running number from 0 up to (N-1), where N is the number
656 * enum hl_goya_dma_direction - Direction of DMA operation inside a LIN_DMA packet that is
683 * enum hl_device_status - Device status information.
715 * Notifier event values - for the notification mechanism and the HL_INFO_GET_EVENTS command
717 * HL_NOTIFIER_EVENT_TPC_ASSERT - Indicates TPC assert event
718 * HL_NOTIFIER_EVENT_UNDEFINED_OPCODE - Indicates undefined operation code
719 * HL_NOTIFIER_EVENT_DEVICE_RESET - Indicates device requires a reset
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| /linux/Documentation/devicetree/bindings/arm/tegra/ |
| H A D | nvidia,tegra194-cbb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-cbb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sumit Gupta <sumitg@nvidia.com>
15 multiple hierarchical sub-NOCs (Network-on-Chip) and connects various
20 "AON-NOC, SCE-NOC, RCE-NOC, BPMP-NOC, CV-NOC" and "CBB Central NOC"
28 - For CCPLEX (CPU Complex) initiator, the driver sets ERD bit. So, the
31 - For other initiators, the ERD is disabled. So, the access issuing
34 include all engines using Cortex-R5 (which is ARMv7 CPU cluster) and
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| /linux/drivers/dma/idxd/ |
| H A D | init.c | 1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/dma-mapping.h>
13 #include <linux/io-64-nonatomic-lo-hi.h>
25 MODULE_DESCRIPTION("Intel Data Streaming Accelerator and In-Memory Analytics Accelerator common dri…
51 .user_submission_safe = false, /* See INTEL-SA-01084 security advisory */
62 .user_submission_safe = false, /* See INTEL-SA-01084 security advisory */
72 /* DSA on GNR-D platforms */
91 struct pci_dev *pdev = idxd->pdev; in idxd_setup_interrupts()
92 struct device *dev = &pdev->dev; in idxd_setup_interrupts()
99 dev_err(dev, "Not MSI-X interrupt capable.\n"); in idxd_setup_interrupts()
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| H A D | registers.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
364 u64 engines; member
370 /* bytes 0-3 */
374 /* bytes 4-7 */
378 /* bytes 8-11 */
389 /* bytes 12-15 */
394 /* bytes 16-19 */
399 /* bytes 20-23 */
404 /* bytes 24-27 */
411 /* bytes 28-31 */
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| /linux/tools/include/uapi/drm/ |
| H A D | i915_drm.h | 9 * distribute, sub license, and/or sell copies of the Software, and to
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
37 * subject to backwards-compatibility constraints.
43 * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch
46 * track of these events, and if a specific cache-line seems to have a
48 * intel-gpu-tools. The value supplied with the event is always 1.
50 * I915_ERROR_UEVENT - Generated upon error detection, currently only via
57 * I915_RESET_UEVENT - Event is generated just before an attempt to reset the
66 * struct i915_user_extension - Base class for defining a chain of extensions
82 * .. code-block:: C
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| /linux/Documentation/devicetree/bindings/net/ |
| H A D | fsl,fman.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
13 Due to the fact that the FMan is an aggregation of sub-engines (ports, MACs,
19 - fsl,fman
26 cell-index:
31 The cell-index value may be used by the SoC, to identify the
33 there's a description of the cell-index use in each SoC:
35 - P1023:
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| /linux/drivers/net/wireless/ath/ath10k/ |
| H A D | hw.h | 1 /* SPDX-License-Identifier: ISC */
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
131 #define ATH10K_FW_API2_FILE "firmware-2.bin"
132 #define ATH10K_FW_API3_FILE "firmware-3.bin"
135 #define ATH10K_FW_API4_FILE "firmware-4.bin"
138 #define ATH10K_FW_API5_FILE "firmware-5.bin"
140 /* the firmware-6.bin blob */
141 #define ATH10K_FW_API6_FILE "firmware-6.bin"
144 #define ATH10K_FW_UTF_API2_FILE "utf-2.bin"
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| /linux/drivers/gpu/drm/xe/ |
| H A D | xe_vm_types.h | 1 /* SPDX-License-Identifier: MIT */
12 #include <linux/dma-resv.h>
52 * struct xe_vma_mem_attr - memory attributes associated with vma
114 * protected by BO's resv and for userptrs, vm->svm.gpusvm.notifier_lock in
115 * write mode for writing or vm->svm.gpusvm.notifier_lock in read mode and
116 * the vm->resv. For stable reading, BO's resv or userptr
117 * vm->svm.gpusvm.notifier_lock in read mode is required. Can be
127 * protected by vm->lock, vm->resv and for userptrs,
128 * vm->svm.gpusvm.notifier_lock for writing. Needs either for reading,
129 * but if reading is done under the vm->lock only, it needs to be held
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| H A D | xe_guc_capture.c | 1 // SPDX-License-Identifier: MIT
3 * Copyright © 2021-2024 Intel Corporation
45 * Book-keeping structure used to track read and write pointers
46 * as we extract error capture data from the GuC-log-buffer's
47 * error-capture region as a stream of dwords.
57 * struct __guc_capture_parsed_output - extracted error capture node
59 * A single unit of extracted error-capture output data grouped together
60 * at an engine-instance level. We keep these nodes in a linked list.
65 * A single set of 3 capture lists: a global-list
66 * an engine-class-list and an engine-instance list.
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| H A D | xe_guc.c | 1 // SPDX-License-Identifier: MIT
59 addr = __xe_bo_ggtt_addr(bo, gt_to_tile(guc_to_gt(guc))->id); in guc_bo_ggtt_addr()
64 xe_assert(xe, xe_bo_size(bo) <= GUC_GGTT_TOP - addr); in guc_bo_ggtt_addr()
71 u32 level = xe_guc_log_get_level(&guc->log); in guc_ctl_debug_flags()
87 if (!xe->info.skip_guc_pc) in guc_ctl_feature_flags()
90 if (xe_configfs_get_psmi_enabled(to_pci_dev(xe->drm.dev))) in guc_ctl_feature_flags()
98 u32 offset = guc_bo_ggtt_addr(guc, guc->log.bo) >> PAGE_SHIFT; in guc_ctl_log_params_flags()
128 FIELD_PREP(GUC_LOG_CRASH, CRASH_BUFFER_SIZE / LOG_UNIT - 1) | in guc_ctl_log_params_flags()
129 FIELD_PREP(GUC_LOG_DEBUG, DEBUG_BUFFER_SIZE / LOG_UNIT - 1) | in guc_ctl_log_params_flags()
130 FIELD_PREP(GUC_LOG_CAPTURE, CAPTURE_BUFFER_SIZE / CAPTURE_UNIT - 1) | in guc_ctl_log_params_flags()
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| /linux/drivers/ata/ |
| H A D | libahci_platform.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2004-2005 Red Hat, Inc.
37 * ahci_platform_enable_phys - Enable PHYs
40 * This function enables all the PHYs found in hpriv->phys, if any.
51 for (i = 0; i < hpriv->nports; i++) { in ahci_platform_enable_phys()
55 rc = phy_init(hpriv->phys[i]); in ahci_platform_enable_phys()
59 rc = phy_set_mode(hpriv->phys[i], PHY_MODE_SATA); in ahci_platform_enable_phys()
61 phy_exit(hpriv->phys[i]); in ahci_platform_enable_phys()
65 rc = phy_power_on(hpriv->phys[i]); in ahci_platform_enable_phys()
67 phy_exit(hpriv->phys[i]); in ahci_platform_enable_phys()
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| /linux/Documentation/edac/ |
| H A D | scrub.rst | 1 .. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.2-no-invariants-or-later
7 Copyright (c) 2024-2025 HiSilicon Limited.
11 Invariant Sections, Front-Cover Texts nor Back-Cover Texts.
14 - Written for: 6.15
17 ------------
24 Memory scrubbing is a feature where an ECC (Error-Correcting Code) engine
49 2. On-demand scrubbing for a specific address range or region of memory.
65 -----------------------------------------
70 and software-based memory scrubbers.
74 on-demand scrubbing (e.g., ACPI RAS2, ACPI ARS). However, the scrub control
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| /linux/drivers/base/ |
| H A D | component.c | 1 // SPDX-License-Identifier: GPL-2.0
16 * The component helper allows drivers to collect a pile of sub-devices,
20 * subsystem-specific way to find a device is not available: The component
24 * the SoC on various components (scanout engines, blending blocks, transcoders
85 struct aggregate_device *m = s->private; in component_devices_show()
86 struct component_match *match = m->match; in component_devices_show()
90 seq_printf(s, "%-50s %20s\n", "aggregate_device name", "status"); in component_devices_show()
91 seq_puts(s, "-----------------------------------------------------------------------\n"); in component_devices_show()
92 seq_printf(s, "%-50s %20s\n\n", in component_devices_show()
93 dev_name(m->parent), m->bound ? "bound" : "not bound"); in component_devices_show()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn316/ |
| H A D | dcn316_resource.c | 868 .dwb_fi_phase = -1, // -1 = disable,
918 return &dpp->base; in dcn31_dpp_create()
938 return &opp->base; in dcn31_opp_create()
956 ctx->dc->caps.extended_aux_timeout_support); in dcn31_aux_engine_create()
958 return &aux_engine->base; in dcn31_aux_engine_create()
1011 return &mpc30->base; in dcn31_mpc_create()
1034 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; in dcn31_hubbub_create()
1036 vmid->ctx = ctx; in dcn31_hubbub_create()
1038 vmid->regs = &vmid_regs[i]; in dcn31_hubbub_create()
1039 vmid->shifts = &vmid_shifts; in dcn31_hubbub_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
| H A D | dcn31_resource.c | 107 dc->ctx->logger
356 /* Some encoders won't be initialized here - but they're logical, not physical. */
873 .dwb_fi_phase = -1, // -1 = disable,
926 return &dpp->base; in dcn31_dpp_create()
946 return &opp->base; in dcn31_opp_create()
964 ctx->dc->caps.extended_aux_timeout_support); in dcn31_aux_engine_create()
966 return &aux_engine->base; in dcn31_aux_engine_create()
1019 return &mpc30->base; in dcn31_mpc_create()
1042 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; in dcn31_hubbub_create()
1044 vmid->ctx = ctx; in dcn31_hubbub_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn315/ |
| H A D | dcn315_resource.c | 873 .dwb_fi_phase = -1, // -1 = disable,
924 return &dpp->base; in dcn31_dpp_create()
944 return &opp->base; in dcn31_opp_create()
962 ctx->dc->caps.extended_aux_timeout_support); in dcn31_aux_engine_create()
964 return &aux_engine->base; in dcn31_aux_engine_create()
1017 return &mpc30->base; in dcn31_mpc_create()
1040 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; in dcn31_hubbub_create()
1042 vmid->ctx = ctx; in dcn31_hubbub_create()
1044 vmid->regs = &vmid_regs[i]; in dcn31_hubbub_create()
1045 vmid->shifts = &vmid_shifts; in dcn31_hubbub_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| H A D | dcn35_resource.c | 1 /* SPDX-License-Identifier: MIT */
127 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
150 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
153 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
200 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg]
733 .dwb_fi_phase = -1, // -1 = disable,
828 ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp); in dcn35_dpp_create()
829 return &dpp->base; in dcn35_dpp_create()
858 dcn35_opp_set_fgcg(opp, ctx->dc->debug.enable_fine_grain_clock_gating.bits.opp); in dcn35_opp_create()
860 return &opp->base; in dcn35_opp_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn36/ |
| H A D | dcn36_resource.c | 1 /* SPDX-License-Identifier: MIT */
112 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
135 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
138 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
185 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg]
714 .dwb_fi_phase = -1, // -1 = disable,
809 ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp); in dcn35_dpp_create()
810 return &dpp->base; in dcn35_dpp_create()
839 dcn35_opp_set_fgcg(opp, ctx->dc->debug.enable_fine_grain_clock_gating.bits.opp); in dcn35_opp_create()
841 return &opp->base; in dcn35_opp_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn351/ |
| H A D | dcn351_resource.c | 1 /* SPDX-License-Identifier: MIT */
107 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
130 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
133 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
180 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg]
713 .dwb_fi_phase = -1, // -1 = disable,
808 ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp); in dcn35_dpp_create()
809 return &dpp->base; in dcn35_dpp_create()
838 dcn35_opp_set_fgcg(opp, ctx->dc->debug.enable_fine_grain_clock_gating.bits.opp); in dcn35_opp_create()
840 return &opp->base; in dcn35_opp_create()
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| /linux/drivers/gpu/drm/amd/amdkfd/ |
| H A D | kfd_device.c | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright 2014-2022 Advanced Micro Devices, Inc.
44 * create process (open) will return -EAGAIN.
69 uint32_t sdma_version = amdgpu_ip_version(kfd->adev, SDMA0_HWIP, 0); in kfd_device_info_set_sdma_info()
81 kfd->device_info.num_sdma_queues_per_engine = 2; in kfd_device_info_set_sdma_info()
107 kfd->device_info.num_sdma_queues_per_engine = 8; in kfd_device_info_set_sdma_info()
113 kfd->device_info.num_sdma_queues_per_engine = 8; in kfd_device_info_set_sdma_info()
116 bitmap_zero(kfd->device_info.reserved_sdma_queues_bitmap, KFD_MAX_SDMA_QUEUES); in kfd_device_info_set_sdma_info()
130 kfd->device_info.num_reserved_sdma_queues_per_engine = 2; in kfd_device_info_set_sdma_info()
131 /* BIT(0)=engine-0 queue-0; BIT(1)=engine-1 queue-0; BIT(2)=engine-0 queue-1; ... */ in kfd_device_info_set_sdma_info()
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| /linux/drivers/accel/ivpu/ |
| H A D | vpu_jsm_api.h | 1 /* SPDX-License-Identifier: MIT */
3 * Copyright (c) 2020-2024, Intel Corporation.
74 /* Job status returned when the job was preempted mid-inference */
79 * Host <-> VPU IPC channels.
80 * ASYNC commands use a high priority channel, other messages use low-priority ones.
132 * does not need per-job fence signalling. Other inline commands objects can be
160 * same process with a relative in-process priority. Valid values for relative
161 * priority are given below - max and min.
164 #define VPU_HWS_COMMAND_QUEUE_MIN_IN_PROCESS_PRIORITY -7
207 * present in the queue prior to them, and in-order relative to each other in the queue.
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_fence.c | 9 * distribute, sub license, and/or sell copies of the Software, and to
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
53 if (__f->base.ops == &amdgpu_fence_ops || in to_amdgpu_fence()
54 __f->base.ops == &amdgpu_job_fence_ops) in to_amdgpu_fence()
61 * amdgpu_fence_write - write a fence value
70 struct amdgpu_fence_driver *drv = &ring->fence_drv; in amdgpu_fence_write()
72 if (drv->cpu_addr) in amdgpu_fence_write()
73 *drv->cpu_addr = cpu_to_le32(seq); in amdgpu_fence_write()
77 * amdgpu_fence_read - read a fence value
86 struct amdgpu_fence_driver *drv = &ring->fence_drv; in amdgpu_fence_read()
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| /linux/include/linux/qed/ |
| H A D | common_hsi.h | 1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
3 * Copyright (c) 2015-2016 QLogic Corporation
4 * Copyright (c) 2019-2021 Marvell International Ltd.
111 #define MAX_NUM_OF_PFS_IN_CHIP (16) /* On both engines */
132 /* Traffic classes in network-facing blocks (PBF, BTB, NIG, BRB, PRS and QM) */
334 (DQ_PWM_OFFSET_TCM32_BASE + DQ_TCM_AGG_VAL_SEL_REG9 - 4)
382 #define QM_LINE_CRD_REG_SIGN_BIT BIT((QM_LINE_CRD_REG_WIDTH - 1))
384 #define QM_BYTE_CRD_REG_SIGN_BIT BIT((QM_BYTE_CRD_REG_WIDTH - 1))
386 #define QM_WFQ_CRD_REG_SIGN_BIT BIT((QM_WFQ_CRD_REG_WIDTH - 1))
388 #define QM_RL_CRD_REG_SIGN_BIT BIT((QM_RL_CRD_REG_WIDTH - 1))
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