Lines Matching +full:sub +full:- +full:engines
1 /* SPDX-License-Identifier: MIT */
17 * subject to backwards-compatibility constraints.
28 * The diagram below represents a high-level simplification of a discrete
56 * │ │ │ └─DSS─┘ └─DSS─┘ └─DSS─┘ └─────Engines─────┘ │ │ │ │ │ │ │
72 * - &DRM_IOCTL_XE_DEVICE_QUERY
73 * - &DRM_IOCTL_XE_GEM_CREATE
74 * - &DRM_IOCTL_XE_GEM_MMAP_OFFSET
75 * - &DRM_IOCTL_XE_VM_CREATE
76 * - &DRM_IOCTL_XE_VM_DESTROY
77 * - &DRM_IOCTL_XE_VM_BIND
78 * - &DRM_IOCTL_XE_EXEC_QUEUE_CREATE
79 * - &DRM_IOCTL_XE_EXEC_QUEUE_DESTROY
80 * - &DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY
81 * - &DRM_IOCTL_XE_EXEC
82 * - &DRM_IOCTL_XE_WAIT_USER_FENCE
83 * - &DRM_IOCTL_XE_OBSERVATION
106 /* Must be kept compact -- no holes */
141 * .. code-block:: C
162 * struct drm_xe_user_extension - Base class for defining a chain of extensions
192 * struct drm_xe_ext_set_property - Generic set property extension
215 * struct drm_xe_engine_class_instance - instance of an engine class
222 * - %DRM_XE_ENGINE_CLASS_RENDER
223 * - %DRM_XE_ENGINE_CLASS_COPY
224 * - %DRM_XE_ENGINE_CLASS_VIDEO_DECODE
225 * - %DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE
226 * - %DRM_XE_ENGINE_CLASS_COMPUTE
227 * - %DRM_XE_ENGINE_CLASS_VM_BIND - Kernel only classes (not actual
249 * struct drm_xe_engine - describe hardware engine
260 * struct drm_xe_query_engines - describe engines
267 /** @num_engines: number of engines returned in @engines */
271 /** @engines: The returned engines for this device */
272 struct drm_xe_engine engines[]; member
276 * enum drm_xe_memory_class - Supported memory classes.
290 * struct drm_xe_mem_region - Describes some region as known to
307 * @min_page_size: Min page-size in bytes for this region.
316 * Affected IOCTLS will return %-EINVAL if alignment restrictions are
366 * struct drm_xe_query_mem_regions - describe memory regions
382 * struct drm_xe_query_config - describe the device configuration
389 * - %DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID - Device ID (lower 16 bits)
391 * - %DRM_XE_QUERY_CONFIG_FLAGS - Flags describing the device
394 * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM - Flag is set if the device
396 * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_LOW_LATENCY - Flag is set if the device
398 * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR - Flag is set if the
400 * - %DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT - Minimal memory alignment
402 * - %DRM_XE_QUERY_CONFIG_VA_BITS - Maximum bits of a virtual address
403 * - %DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY - Value of the highest
426 * struct drm_xe_gt - describe an individual GT.
434 * - %DRM_XE_QUERY_GT_TYPE_MAIN
435 * - %DRM_XE_QUERY_GT_TYPE_MEDIA
452 * drm_xe_query_mem_regions that are nearest to the current engines
462 * drm_xe_query_mem_regions that are far from the engines of this GT.
485 * struct drm_xe_query_gt_list - A list with GT description items.
501 * struct drm_xe_query_topology_mask - describe the topology mask of a GT
511 * - %DRM_XE_TOPO_DSS_GEOMETRY - To query the mask of Dual Sub Slices
516 * - %DRM_XE_TOPO_DSS_COMPUTE - To query the mask of Dual Sub Slices
521 * - %DRM_XE_TOPO_L3_BANK - To query the mask of enabled L3 banks. This type
524 * - %DRM_XE_TOPO_EU_PER_DSS - To query the mask of Execution Units (EU)
525 * available per Dual Sub Slices (DSS). For example a query response
530 * - %DRM_XE_TOPO_SIMD16_EU_PER_DSS - To query the mask of SIMD16 Execution
531 * Units (EU) available per Dual Sub Slices (DSS). For example a query
552 /** @mask: little-endian mask of @num_bytes */
557 * struct drm_xe_query_engine_cycles - correlate CPU and GPU timestamps
608 * struct drm_xe_query_uc_fw_version - query a micro-controller firmware version
611 * of the micro-controller firmware.
614 /** @uc_type: The micro-controller type to query firmware version */
639 * struct drm_xe_query_pxp_status - query if PXP is ready
648 * -ENODEV: PXP not supported or disabled;
649 * -EIO: fatal error occurred during init, so PXP will never be enabled;
650 * -EINVAL: incorrect value provided as part of the query;
651 * -EFAULT: error copying the memory between kernel and userspace.
672 * struct drm_xe_device_query - Input of &DRM_IOCTL_XE_DEVICE_QUERY - main
680 * - %DRM_XE_DEVICE_QUERY_ENGINES
681 * - %DRM_XE_DEVICE_QUERY_MEM_REGIONS
682 * - %DRM_XE_DEVICE_QUERY_CONFIG
683 * - %DRM_XE_DEVICE_QUERY_GT_LIST
684 * - %DRM_XE_DEVICE_QUERY_HWCONFIG - Query type to retrieve the hardware
688 * - %DRM_XE_DEVICE_QUERY_GT_TOPOLOGY
689 * - %DRM_XE_DEVICE_QUERY_ENGINE_CYCLES
690 * - %DRM_XE_DEVICE_QUERY_PXP_STATUS
696 * IOCTL call returns -EINVAL.
699 * information about the device engines with DRM_XE_DEVICE_QUERY_ENGINES:
701 * .. code-block:: C
703 * struct drm_xe_query_engines *engines;
711 * engines = malloc(query.size);
712 * query.data = (uintptr_t)engines;
714 * for (int i = 0; i < engines->num_engines; i++) {
716 * engines->engines[i].instance.engine_class ==
718 * engines->engines[i].instance.engine_class ==
720 * engines->engines[i].instance.engine_class ==
722 * engines->engines[i].instance.engine_class ==
724 * engines->engines[i].instance.engine_class ==
728 * free(engines);
759 * struct drm_xe_gem_create - Input of &DRM_IOCTL_XE_GEM_CREATE - A structure for
763 * - %DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING
764 * - %DRM_XE_GEM_CREATE_FLAG_SCANOUT
765 * - %DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM - When using VRAM as a
768 * for small-bar systems (on full-bar systems this gets turned into a
775 * Note2: For clear-color CCS surfaces the kernel needs to read the
776 * clear-color value stored in the buffer, and on discrete platforms we
779 * small-bar systems.
782 * - %DRM_XE_GEM_CPU_CACHING_WB - Allocate the pages with write-back
785 * - %DRM_XE_GEM_CPU_CACHING_WC - Allocate the pages as write-combined. This
793 * - %DRM_XE_GEM_CREATE_SET_PROPERTY_PXP_TYPE - set the type of PXP session
857 * between GPU- and CPU is guaranteed. The caching mode of
858 * existing CPU-mappings will be updated transparently to
859 * user-space clients.
870 * struct drm_xe_gem_mmap_offset - Input of &DRM_IOCTL_XE_GEM_MMAP_OFFSET
873 * - %DRM_XE_MMAP_OFFSET_FLAG_PCI_BARRIER - For user to query special offset
887 * .. code-block:: C
917 * struct drm_xe_vm_create - Input of &DRM_IOCTL_XE_VM_CREATE
920 * - %DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE - Map the whole virtual address
925 * - %DRM_XE_VM_CREATE_FLAG_LR_MODE - An LR, or Long Running VM accepts
930 * used as out-syncobjs, that is, together with DRM_XE_SYNC_FLAG_SIGNAL.
931 * LR VMs can be created in recoverable page-fault mode using
934 * different per-VM overcommit semantics that are enabled by
937 * - %DRM_XE_VM_CREATE_FLAG_FAULT_MODE - Requires also
939 * demand when accessed, and also allows per-VM overcommit of memory.
961 * struct drm_xe_vm_destroy - Input of &DRM_IOCTL_XE_VM_DESTROY
975 * struct drm_xe_vm_bind_op - run bind operations
978 * - %DRM_XE_VM_BIND_OP_MAP
979 * - %DRM_XE_VM_BIND_OP_UNMAP
980 * - %DRM_XE_VM_BIND_OP_MAP_USERPTR
981 * - %DRM_XE_VM_BIND_OP_UNMAP_ALL
982 * - %DRM_XE_VM_BIND_OP_PREFETCH
985 * - %DRM_XE_VM_BIND_FLAG_READONLY - Setup the page tables as read-only
987 * - %DRM_XE_VM_BIND_FLAG_IMMEDIATE - On a faulting VM, do the
989 * fault handler. This is implied on a non-faulting VM as there is no
991 * - %DRM_XE_VM_BIND_FLAG_NULL - When the NULL flag is set, the page
997 * - %DRM_XE_VM_BIND_FLAG_CHECK_PXP - If the object is encrypted via PXP,
1000 * - %DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR - When the CPU address mirror flag is
1027 * there is a mismatch (see note below for pre-MTL platforms).
1029 * Note: On pre-MTL platforms there is only a caching mode and no
1031 * shared-LLC (or is dgpu) so all GT memory accesses are coherent with
1036 * levels into the following coherency buckets on all pre-MTL platforms:
1038 * ppGTT UC -> COH_NONE
1039 * ppGTT WC -> COH_NONE
1040 * ppGTT WT -> COH_NONE
1041 * ppGTT WB -> COH_AT_LEAST_1WAY
1044 * such platforms (or perhaps in general for dma-buf if shared with
1047 * have a shared-LLC. On MTL+ this completely changes and the HW
1051 * Note: For userptr and externally imported dma-buf the kernel expects
1126 * struct drm_xe_vm_bind - Input of &DRM_IOCTL_XE_VM_BIND
1133 * .. code-block:: C
1197 * struct drm_xe_exec_queue_create - Input of &DRM_IOCTL_XE_EXEC_QUEUE_CREATE
1203 * - %DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY - set the queue priority.
1205 * - %DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE - set the queue timeslice
1207 * - %DRM_XE_EXEC_QUEUE_SET_PROPERTY_PXP_TYPE - set the type of PXP session
1216 * before PXP is ready, the ioctl will return -EBUSY if init is still in
1217 * progress or -EIO if init failed.
1218 * Given that going into a power-saving state kills PXP HWDRM sessions,
1226 * .. code-block:: C
1281 * @instances: user pointer to a 2-d array of struct
1294 * struct drm_xe_exec_queue_destroy - Input of &DRM_IOCTL_XE_EXEC_QUEUE_DESTROY
1308 * struct drm_xe_exec_queue_get_property - Input of &DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY
1311 * - %DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN
1332 * struct drm_xe_sync - sync object
1335 * - %DRM_XE_SYNC_TYPE_SYNCOBJ
1336 * - %DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ
1337 * - %DRM_XE_SYNC_TYPE_USER_FENCE
1340 * - %DRM_XE_SYNC_FLAG_SIGNAL
1344 * .. code-block:: C
1406 * struct drm_xe_exec - Input of &DRM_IOCTL_XE_EXEC
1413 * .. code-block:: C
1458 * struct drm_xe_wait_user_fence - Input of &DRM_IOCTL_XE_WAIT_USER_FENCE
1460 * Wait on user fence, XE will wake-up on every HW engine interrupt in the
1468 * - %DRM_XE_UFENCE_WAIT_OP_EQ
1469 * - %DRM_XE_UFENCE_WAIT_OP_NEQ
1470 * - %DRM_XE_UFENCE_WAIT_OP_GT
1471 * - %DRM_XE_UFENCE_WAIT_OP_GTE
1472 * - %DRM_XE_UFENCE_WAIT_OP_LT
1473 * - %DRM_XE_UFENCE_WAIT_OP_LTE
1476 * - %DRM_XE_UFENCE_WAIT_FLAG_ABSTIME
1477 * - %DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP
1480 * - 0xffu for u8
1481 * - 0xffffu for u16
1482 * - 0xffffffffu for u32
1483 * - 0xffffffffffffffffu for u64
1543 * enum drm_xe_observation_type - Observation stream types
1553 * enum drm_xe_observation_op - Observation stream ops
1567 * struct drm_xe_observation_param - Input of &DRM_XE_OBSERVATION
1586 * enum drm_xe_observation_ioctls - Observation stream fd ioctl's
1609 * enum drm_xe_oa_unit_type - OA unit types
1614 * sub-types of OAG. For OAR/OAC, use OAG.
1623 * struct drm_xe_oa_unit - describe OA unit
1635 /** @capabilities: OA capabilities bit-mask */
1648 /** @num_engines: number of engines in @eci array */
1651 /** @eci: engines attached to this OA unit */
1656 * struct drm_xe_query_oa_units - describe OA units
1665 * .. code-block:: C
1672 * poau = (u8 *)&qoa->oa_units[0];
1673 * for (int i = 0; i < qoa->num_oa_units; i++) {
1676 * poau += sizeof(*oau) + oau->num_engines * sizeof(oau->eci[0]);
1695 * enum drm_xe_oa_format_type - OA format types as specified in PRM/Bspec
1714 * enum drm_xe_oa_property_id - OA stream property id's
1823 * struct drm_xe_oa_config - OA metric configuration
1833 /** @uuid: String formatted like "%\08x-%\04x-%\04x-%\04x-%\012x" */
1847 * struct drm_xe_oa_stream_status - OA stream status returned from
1868 * struct drm_xe_oa_stream_info - OA stream info returned from
1883 * enum drm_xe_pxp_session_type - Supported PXP session types.
1903 * enum drm_xe_eu_stall_property_id - EU stall sampling input property ids.
1939 * struct drm_xe_query_eu_stall - Information about EU stall sampling.
1949 /** @capabilities: EU stall capabilities bit-mask */