1bfe1d560SDave Jiang /* SPDX-License-Identifier: GPL-2.0 */ 2bfe1d560SDave Jiang /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */ 3bfe1d560SDave Jiang #ifndef _IDXD_REGISTERS_H_ 4bfe1d560SDave Jiang #define _IDXD_REGISTERS_H_ 5bfe1d560SDave Jiang 6244da66cSDave Jiang #include <uapi/linux/idxd.h> 7244da66cSDave Jiang 8bfe1d560SDave Jiang /* PCI Config */ 9ade8a86bSDave Jiang #define DEVICE_VERSION_1 0x100 10ade8a86bSDave Jiang #define DEVICE_VERSION_2 0x200 11ade8a86bSDave Jiang 12bfe1d560SDave Jiang #define IDXD_MMIO_BAR 0 13bfe1d560SDave Jiang #define IDXD_WQ_BAR 2 148326be9fSDave Jiang #define IDXD_PORTAL_SIZE PAGE_SIZE 15bfe1d560SDave Jiang 16bfe1d560SDave Jiang /* MMIO Device BAR0 Registers */ 17bfe1d560SDave Jiang #define IDXD_VER_OFFSET 0x00 18bfe1d560SDave Jiang #define IDXD_VER_MAJOR_MASK 0xf0 19bfe1d560SDave Jiang #define IDXD_VER_MINOR_MASK 0x0f 20bfe1d560SDave Jiang #define GET_IDXD_VER_MAJOR(x) (((x) & IDXD_VER_MAJOR_MASK) >> 4) 21bfe1d560SDave Jiang #define GET_IDXD_VER_MINOR(x) ((x) & IDXD_VER_MINOR_MASK) 22bfe1d560SDave Jiang 23bfe1d560SDave Jiang union gen_cap_reg { 24bfe1d560SDave Jiang struct { 25bfe1d560SDave Jiang u64 block_on_fault:1; 26bfe1d560SDave Jiang u64 overlap_copy:1; 27bfe1d560SDave Jiang u64 cache_control_mem:1; 28bfe1d560SDave Jiang u64 cache_control_cache:1; 29eb15e715SDave Jiang u64 cmd_cap:1; 30bfe1d560SDave Jiang u64 rsvd:3; 31bfe1d560SDave Jiang u64 dest_readback:1; 32bfe1d560SDave Jiang u64 drain_readback:1; 331649091fSDave Jiang u64 rsvd2:3; 341649091fSDave Jiang u64 evl_support:2; 352442b747SDave Jiang u64 batch_continuation:1; 36bfe1d560SDave Jiang u64 max_xfer_shift:5; 37bfe1d560SDave Jiang u64 max_batch_shift:4; 38bfe1d560SDave Jiang u64 max_ims_mult:6; 39bfe1d560SDave Jiang u64 config_en:1; 40c5b64b68SDave Jiang u64 rsvd3:32; 41bfe1d560SDave Jiang }; 42bfe1d560SDave Jiang u64 bits; 43bfe1d560SDave Jiang } __packed; 44bfe1d560SDave Jiang #define IDXD_GENCAP_OFFSET 0x10 45bfe1d560SDave Jiang 46bfe1d560SDave Jiang union wq_cap_reg { 47bfe1d560SDave Jiang struct { 48bfe1d560SDave Jiang u64 total_wq_size:16; 49bfe1d560SDave Jiang u64 num_wqs:8; 50484f910eSDave Jiang u64 wqcfg_size:4; 51484f910eSDave Jiang u64 rsvd:20; 52bfe1d560SDave Jiang u64 shared_mode:1; 53bfe1d560SDave Jiang u64 dedicated_mode:1; 5492de5fa2SDave Jiang u64 wq_ats_support:1; 55bfe1d560SDave Jiang u64 priority:1; 56bfe1d560SDave Jiang u64 occupancy:1; 57bfe1d560SDave Jiang u64 occupancy_int:1; 58b0325aefSDave Jiang u64 op_config:1; 59f2dc3271SDave Jiang u64 wq_prs_support:1; 60f2dc3271SDave Jiang u64 rsvd4:8; 61bfe1d560SDave Jiang }; 62bfe1d560SDave Jiang u64 bits; 63bfe1d560SDave Jiang } __packed; 64bfe1d560SDave Jiang #define IDXD_WQCAP_OFFSET 0x20 65484f910eSDave Jiang #define IDXD_WQCFG_MIN 5 66bfe1d560SDave Jiang 67bfe1d560SDave Jiang union group_cap_reg { 68bfe1d560SDave Jiang struct { 69bfe1d560SDave Jiang u64 num_groups:8; 707ed6f1b8SDave Jiang u64 total_rdbufs:8; /* formerly total_tokens */ 717ed6f1b8SDave Jiang u64 rdbuf_ctrl:1; /* formerly token_en */ 727ed6f1b8SDave Jiang u64 rdbuf_limit:1; /* formerly token_limit */ 731f273752SDave Jiang u64 progress_limit:1; /* descriptor and batch descriptor */ 741f273752SDave Jiang u64 rsvd:45; 75bfe1d560SDave Jiang }; 76bfe1d560SDave Jiang u64 bits; 77bfe1d560SDave Jiang } __packed; 78bfe1d560SDave Jiang #define IDXD_GRPCAP_OFFSET 0x30 79bfe1d560SDave Jiang 80bfe1d560SDave Jiang union engine_cap_reg { 81bfe1d560SDave Jiang struct { 82bfe1d560SDave Jiang u64 num_engines:8; 83bfe1d560SDave Jiang u64 rsvd:56; 84bfe1d560SDave Jiang }; 85bfe1d560SDave Jiang u64 bits; 86bfe1d560SDave Jiang } __packed; 87bfe1d560SDave Jiang 88bfe1d560SDave Jiang #define IDXD_ENGCAP_OFFSET 0x38 89bfe1d560SDave Jiang 90bfe1d560SDave Jiang #define IDXD_OPCAP_NOOP 0x0001 91bfe1d560SDave Jiang #define IDXD_OPCAP_BATCH 0x0002 92bfe1d560SDave Jiang #define IDXD_OPCAP_MEMMOVE 0x0008 93bfe1d560SDave Jiang struct opcap { 94bfe1d560SDave Jiang u64 bits[4]; 95bfe1d560SDave Jiang }; 96bfe1d560SDave Jiang 97a8563a33SDave Jiang #define IDXD_MAX_OPCAP_BITS 256U 98a8563a33SDave Jiang 99bfe1d560SDave Jiang #define IDXD_OPCAP_OFFSET 0x40 100bfe1d560SDave Jiang 101bfe1d560SDave Jiang #define IDXD_TABLE_OFFSET 0x60 102bfe1d560SDave Jiang union offsets_reg { 103bfe1d560SDave Jiang struct { 104bfe1d560SDave Jiang u64 grpcfg:16; 105bfe1d560SDave Jiang u64 wqcfg:16; 106bfe1d560SDave Jiang u64 msix_perm:16; 107bfe1d560SDave Jiang u64 ims:16; 108bfe1d560SDave Jiang u64 perfmon:16; 109bfe1d560SDave Jiang u64 rsvd:48; 110bfe1d560SDave Jiang }; 111bfe1d560SDave Jiang u64 bits[2]; 112bfe1d560SDave Jiang } __packed; 113bfe1d560SDave Jiang 1142f8417a9SDave Jiang #define IDXD_TABLE_MULT 0x100 1152f8417a9SDave Jiang 116bfe1d560SDave Jiang #define IDXD_GENCFG_OFFSET 0x80 117bfe1d560SDave Jiang union gencfg_reg { 118bfe1d560SDave Jiang struct { 1197ed6f1b8SDave Jiang u32 rdbuf_limit:8; 120bfe1d560SDave Jiang u32 rsvd:4; 121bfe1d560SDave Jiang u32 user_int_en:1; 122244da66cSDave Jiang u32 evl_en:1; 123244da66cSDave Jiang u32 rsvd2:18; 124bfe1d560SDave Jiang }; 125bfe1d560SDave Jiang u32 bits; 126bfe1d560SDave Jiang } __packed; 127bfe1d560SDave Jiang 128bfe1d560SDave Jiang #define IDXD_GENCTRL_OFFSET 0x88 129bfe1d560SDave Jiang union genctrl_reg { 130bfe1d560SDave Jiang struct { 131bfe1d560SDave Jiang u32 softerr_int_en:1; 1325b0c68c4SDave Jiang u32 halt_int_en:1; 133244da66cSDave Jiang u32 evl_int_en:1; 134244da66cSDave Jiang u32 rsvd:29; 135bfe1d560SDave Jiang }; 136bfe1d560SDave Jiang u32 bits; 137bfe1d560SDave Jiang } __packed; 138bfe1d560SDave Jiang 139bfe1d560SDave Jiang #define IDXD_GENSTATS_OFFSET 0x90 140bfe1d560SDave Jiang union gensts_reg { 141bfe1d560SDave Jiang struct { 142bfe1d560SDave Jiang u32 state:2; 143bfe1d560SDave Jiang u32 reset_type:2; 144bfe1d560SDave Jiang u32 rsvd:28; 145bfe1d560SDave Jiang }; 146bfe1d560SDave Jiang u32 bits; 147bfe1d560SDave Jiang } __packed; 148bfe1d560SDave Jiang 149bfe1d560SDave Jiang enum idxd_device_status_state { 150bfe1d560SDave Jiang IDXD_DEVICE_STATE_DISABLED = 0, 151bfe1d560SDave Jiang IDXD_DEVICE_STATE_ENABLED, 152bfe1d560SDave Jiang IDXD_DEVICE_STATE_DRAIN, 153bfe1d560SDave Jiang IDXD_DEVICE_STATE_HALT, 154bfe1d560SDave Jiang }; 155bfe1d560SDave Jiang 156bfe1d560SDave Jiang enum idxd_device_reset_type { 157bfe1d560SDave Jiang IDXD_DEVICE_RESET_SOFTWARE = 0, 158bfe1d560SDave Jiang IDXD_DEVICE_RESET_FLR, 159bfe1d560SDave Jiang IDXD_DEVICE_RESET_WARM, 160bfe1d560SDave Jiang IDXD_DEVICE_RESET_COLD, 161bfe1d560SDave Jiang }; 162bfe1d560SDave Jiang 163bfe1d560SDave Jiang #define IDXD_INTCAUSE_OFFSET 0x98 164bfe1d560SDave Jiang #define IDXD_INTC_ERR 0x01 165bfe1d560SDave Jiang #define IDXD_INTC_CMD 0x02 166bfe1d560SDave Jiang #define IDXD_INTC_OCCUPY 0x04 167bfe1d560SDave Jiang #define IDXD_INTC_PERFMON_OVFL 0x08 16888d97ea8SDave Jiang #define IDXD_INTC_HALT_STATE 0x10 1692f431ba9SDave Jiang #define IDXD_INTC_EVL 0x20 17056fc39f5SDave Jiang #define IDXD_INTC_INT_HANDLE_REVOKED 0x80000000 171bfe1d560SDave Jiang 172bfe1d560SDave Jiang #define IDXD_CMD_OFFSET 0xa0 173bfe1d560SDave Jiang union idxd_command_reg { 174bfe1d560SDave Jiang struct { 175bfe1d560SDave Jiang u32 operand:20; 176bfe1d560SDave Jiang u32 cmd:5; 177bfe1d560SDave Jiang u32 rsvd:6; 178bfe1d560SDave Jiang u32 int_req:1; 179bfe1d560SDave Jiang }; 180bfe1d560SDave Jiang u32 bits; 181bfe1d560SDave Jiang } __packed; 182bfe1d560SDave Jiang 183bfe1d560SDave Jiang enum idxd_cmd { 184bfe1d560SDave Jiang IDXD_CMD_ENABLE_DEVICE = 1, 185bfe1d560SDave Jiang IDXD_CMD_DISABLE_DEVICE, 186bfe1d560SDave Jiang IDXD_CMD_DRAIN_ALL, 187bfe1d560SDave Jiang IDXD_CMD_ABORT_ALL, 188bfe1d560SDave Jiang IDXD_CMD_RESET_DEVICE, 189bfe1d560SDave Jiang IDXD_CMD_ENABLE_WQ, 190bfe1d560SDave Jiang IDXD_CMD_DISABLE_WQ, 191bfe1d560SDave Jiang IDXD_CMD_DRAIN_WQ, 192bfe1d560SDave Jiang IDXD_CMD_ABORT_WQ, 193bfe1d560SDave Jiang IDXD_CMD_RESET_WQ, 194bfe1d560SDave Jiang IDXD_CMD_DRAIN_PASID, 195bfe1d560SDave Jiang IDXD_CMD_ABORT_PASID, 196bfe1d560SDave Jiang IDXD_CMD_REQUEST_INT_HANDLE, 197eb15e715SDave Jiang IDXD_CMD_RELEASE_INT_HANDLE, 198bfe1d560SDave Jiang }; 199bfe1d560SDave Jiang 200eb15e715SDave Jiang #define CMD_INT_HANDLE_IMS 0x10000 201eb15e715SDave Jiang 202bfe1d560SDave Jiang #define IDXD_CMDSTS_OFFSET 0xa8 203bfe1d560SDave Jiang union cmdsts_reg { 204bfe1d560SDave Jiang struct { 205bfe1d560SDave Jiang u8 err; 206bfe1d560SDave Jiang u16 result; 207bfe1d560SDave Jiang u8 rsvd:7; 208bfe1d560SDave Jiang u8 active:1; 209bfe1d560SDave Jiang }; 210bfe1d560SDave Jiang u32 bits; 211bfe1d560SDave Jiang } __packed; 212bfe1d560SDave Jiang #define IDXD_CMDSTS_ACTIVE 0x80000000 213eb15e715SDave Jiang #define IDXD_CMDSTS_ERR_MASK 0xff 214eb15e715SDave Jiang #define IDXD_CMDSTS_RES_SHIFT 8 215bfe1d560SDave Jiang 216bfe1d560SDave Jiang enum idxd_cmdsts_err { 217bfe1d560SDave Jiang IDXD_CMDSTS_SUCCESS = 0, 218bfe1d560SDave Jiang IDXD_CMDSTS_INVAL_CMD, 219bfe1d560SDave Jiang IDXD_CMDSTS_INVAL_WQIDX, 220bfe1d560SDave Jiang IDXD_CMDSTS_HW_ERR, 221bfe1d560SDave Jiang /* enable device errors */ 222bfe1d560SDave Jiang IDXD_CMDSTS_ERR_DEV_ENABLED = 0x10, 223bfe1d560SDave Jiang IDXD_CMDSTS_ERR_CONFIG, 224bfe1d560SDave Jiang IDXD_CMDSTS_ERR_BUSMASTER_EN, 225bfe1d560SDave Jiang IDXD_CMDSTS_ERR_PASID_INVAL, 226bfe1d560SDave Jiang IDXD_CMDSTS_ERR_WQ_SIZE_ERANGE, 227bfe1d560SDave Jiang IDXD_CMDSTS_ERR_GRP_CONFIG, 228bfe1d560SDave Jiang IDXD_CMDSTS_ERR_GRP_CONFIG2, 229bfe1d560SDave Jiang IDXD_CMDSTS_ERR_GRP_CONFIG3, 230bfe1d560SDave Jiang IDXD_CMDSTS_ERR_GRP_CONFIG4, 231bfe1d560SDave Jiang /* enable wq errors */ 232bfe1d560SDave Jiang IDXD_CMDSTS_ERR_DEV_NOTEN = 0x20, 233bfe1d560SDave Jiang IDXD_CMDSTS_ERR_WQ_ENABLED, 234bfe1d560SDave Jiang IDXD_CMDSTS_ERR_WQ_SIZE, 235bfe1d560SDave Jiang IDXD_CMDSTS_ERR_WQ_PRIOR, 236bfe1d560SDave Jiang IDXD_CMDSTS_ERR_WQ_MODE, 237bfe1d560SDave Jiang IDXD_CMDSTS_ERR_BOF_EN, 238bfe1d560SDave Jiang IDXD_CMDSTS_ERR_PASID_EN, 239bfe1d560SDave Jiang IDXD_CMDSTS_ERR_MAX_BATCH_SIZE, 240bfe1d560SDave Jiang IDXD_CMDSTS_ERR_MAX_XFER_SIZE, 241bfe1d560SDave Jiang /* disable device errors */ 242bfe1d560SDave Jiang IDXD_CMDSTS_ERR_DIS_DEV_EN = 0x31, 243bfe1d560SDave Jiang /* disable WQ, drain WQ, abort WQ, reset WQ */ 244bfe1d560SDave Jiang IDXD_CMDSTS_ERR_DEV_NOT_EN, 245bfe1d560SDave Jiang /* request interrupt handle */ 246bfe1d560SDave Jiang IDXD_CMDSTS_ERR_INVAL_INT_IDX = 0x41, 247bfe1d560SDave Jiang IDXD_CMDSTS_ERR_NO_HANDLE, 248bfe1d560SDave Jiang }; 249bfe1d560SDave Jiang 250eb15e715SDave Jiang #define IDXD_CMDCAP_OFFSET 0xb0 251eb15e715SDave Jiang 252bfe1d560SDave Jiang #define IDXD_SWERR_OFFSET 0xc0 253bfe1d560SDave Jiang #define IDXD_SWERR_VALID 0x00000001 254bfe1d560SDave Jiang #define IDXD_SWERR_OVERFLOW 0x00000002 255bfe1d560SDave Jiang #define IDXD_SWERR_ACK (IDXD_SWERR_VALID | IDXD_SWERR_OVERFLOW) 256bfe1d560SDave Jiang union sw_err_reg { 257bfe1d560SDave Jiang struct { 258bfe1d560SDave Jiang u64 valid:1; 259bfe1d560SDave Jiang u64 overflow:1; 260bfe1d560SDave Jiang u64 desc_valid:1; 261bfe1d560SDave Jiang u64 wq_idx_valid:1; 262bfe1d560SDave Jiang u64 batch:1; 263bfe1d560SDave Jiang u64 fault_rw:1; 264bfe1d560SDave Jiang u64 priv:1; 265bfe1d560SDave Jiang u64 rsvd:1; 266bfe1d560SDave Jiang u64 error:8; 267bfe1d560SDave Jiang u64 wq_idx:8; 268bfe1d560SDave Jiang u64 rsvd2:8; 269bfe1d560SDave Jiang u64 operation:8; 270bfe1d560SDave Jiang u64 pasid:20; 271bfe1d560SDave Jiang u64 rsvd3:4; 272bfe1d560SDave Jiang 273bfe1d560SDave Jiang u64 batch_idx:16; 274bfe1d560SDave Jiang u64 rsvd4:16; 275bfe1d560SDave Jiang u64 invalid_flags:32; 276bfe1d560SDave Jiang 277bfe1d560SDave Jiang u64 fault_addr; 278bfe1d560SDave Jiang 279bfe1d560SDave Jiang u64 rsvd5; 280bfe1d560SDave Jiang }; 281bfe1d560SDave Jiang u64 bits[4]; 282bfe1d560SDave Jiang } __packed; 283bfe1d560SDave Jiang 2849f0d99b3SDave Jiang union iaa_cap_reg { 2859f0d99b3SDave Jiang struct { 2869f0d99b3SDave Jiang u64 dec_aecs_format_ver:1; 2879f0d99b3SDave Jiang u64 drop_init_bits:1; 2889f0d99b3SDave Jiang u64 chaining:1; 2899f0d99b3SDave Jiang u64 force_array_output_mod:1; 2909f0d99b3SDave Jiang u64 load_part_aecs:1; 2919f0d99b3SDave Jiang u64 comp_early_abort:1; 2929f0d99b3SDave Jiang u64 nested_comp:1; 2939f0d99b3SDave Jiang u64 diction_comp:1; 2949f0d99b3SDave Jiang u64 header_gen:1; 2959f0d99b3SDave Jiang u64 crypto_gcm:1; 2969f0d99b3SDave Jiang u64 crypto_cfb:1; 2979f0d99b3SDave Jiang u64 crypto_xts:1; 2989f0d99b3SDave Jiang u64 rsvd:52; 2999f0d99b3SDave Jiang }; 3009f0d99b3SDave Jiang u64 bits; 3019f0d99b3SDave Jiang } __packed; 3029f0d99b3SDave Jiang 3039f0d99b3SDave Jiang #define IDXD_IAACAP_OFFSET 0x180 3049f0d99b3SDave Jiang 305244da66cSDave Jiang #define IDXD_EVLCFG_OFFSET 0xe0 306244da66cSDave Jiang union evlcfg_reg { 307244da66cSDave Jiang struct { 308244da66cSDave Jiang u64 pasid_en:1; 309244da66cSDave Jiang u64 priv:1; 310244da66cSDave Jiang u64 rsvd:10; 311244da66cSDave Jiang u64 base_addr:52; 312244da66cSDave Jiang 313244da66cSDave Jiang u64 size:16; 314244da66cSDave Jiang u64 pasid:20; 315244da66cSDave Jiang u64 rsvd2:28; 316244da66cSDave Jiang }; 317244da66cSDave Jiang u64 bits[2]; 318244da66cSDave Jiang } __packed; 319244da66cSDave Jiang 3201649091fSDave Jiang #define IDXD_EVL_SIZE_MIN 0x0040 3211649091fSDave Jiang #define IDXD_EVL_SIZE_MAX 0xffff 3221649091fSDave Jiang 323bfe1d560SDave Jiang union msix_perm { 324bfe1d560SDave Jiang struct { 325bfe1d560SDave Jiang u32 rsvd:2; 326bfe1d560SDave Jiang u32 ignore:1; 327bfe1d560SDave Jiang u32 pasid_en:1; 328bfe1d560SDave Jiang u32 rsvd2:8; 329bfe1d560SDave Jiang u32 pasid:20; 330bfe1d560SDave Jiang }; 331bfe1d560SDave Jiang u32 bits; 332bfe1d560SDave Jiang } __packed; 333bfe1d560SDave Jiang 334bfe1d560SDave Jiang union group_flags { 335bfe1d560SDave Jiang struct { 3361f273752SDave Jiang u64 tc_a:3; 3371f273752SDave Jiang u64 tc_b:3; 3381f273752SDave Jiang u64 rsvd:1; 3391f273752SDave Jiang u64 use_rdbuf_limit:1; 3401f273752SDave Jiang u64 rdbufs_reserved:8; 3411f273752SDave Jiang u64 rsvd2:4; 3421f273752SDave Jiang u64 rdbufs_allowed:8; 3431f273752SDave Jiang u64 rsvd3:4; 3441f273752SDave Jiang u64 desc_progress_limit:2; 3457ca68fa3SDave Jiang u64 rsvd4:2; 3467ca68fa3SDave Jiang u64 batch_progress_limit:2; 3477ca68fa3SDave Jiang u64 rsvd5:26; 348bfe1d560SDave Jiang }; 3491f273752SDave Jiang u64 bits; 350bfe1d560SDave Jiang } __packed; 351bfe1d560SDave Jiang 352bfe1d560SDave Jiang struct grpcfg { 353bfe1d560SDave Jiang u64 wqs[4]; 354bfe1d560SDave Jiang u64 engines; 355bfe1d560SDave Jiang union group_flags flags; 356bfe1d560SDave Jiang } __packed; 357bfe1d560SDave Jiang 358bfe1d560SDave Jiang union wqcfg { 359bfe1d560SDave Jiang struct { 360bfe1d560SDave Jiang /* bytes 0-3 */ 361bfe1d560SDave Jiang u16 wq_size; 362bfe1d560SDave Jiang u16 rsvd; 363bfe1d560SDave Jiang 364bfe1d560SDave Jiang /* bytes 4-7 */ 365bfe1d560SDave Jiang u16 wq_thresh; 366bfe1d560SDave Jiang u16 rsvd1; 367bfe1d560SDave Jiang 368bfe1d560SDave Jiang /* bytes 8-11 */ 369bfe1d560SDave Jiang u32 mode:1; /* shared or dedicated */ 370bfe1d560SDave Jiang u32 bof:1; /* block on fault */ 37192de5fa2SDave Jiang u32 wq_ats_disable:1; 372f2dc3271SDave Jiang u32 wq_prs_disable:1; 373bfe1d560SDave Jiang u32 priority:4; 374bfe1d560SDave Jiang u32 pasid:20; 375bfe1d560SDave Jiang u32 pasid_en:1; 376bfe1d560SDave Jiang u32 priv:1; 377bfe1d560SDave Jiang u32 rsvd3:2; 378bfe1d560SDave Jiang 379bfe1d560SDave Jiang /* bytes 12-15 */ 380bfe1d560SDave Jiang u32 max_xfer_shift:5; 381bfe1d560SDave Jiang u32 max_batch_shift:4; 382bfe1d560SDave Jiang u32 rsvd4:23; 383bfe1d560SDave Jiang 384bfe1d560SDave Jiang /* bytes 16-19 */ 385bfe1d560SDave Jiang u16 occupancy_inth; 386bfe1d560SDave Jiang u16 occupancy_table_sel:1; 387bfe1d560SDave Jiang u16 rsvd5:15; 388bfe1d560SDave Jiang 389bfe1d560SDave Jiang /* bytes 20-23 */ 390bfe1d560SDave Jiang u16 occupancy_limit; 391bfe1d560SDave Jiang u16 occupancy_int_en:1; 392bfe1d560SDave Jiang u16 rsvd6:15; 393bfe1d560SDave Jiang 394bfe1d560SDave Jiang /* bytes 24-27 */ 395bfe1d560SDave Jiang u16 occupancy; 396bfe1d560SDave Jiang u16 occupancy_int:1; 397bfe1d560SDave Jiang u16 rsvd7:12; 398bfe1d560SDave Jiang u16 mode_support:1; 399bfe1d560SDave Jiang u16 wq_state:2; 400bfe1d560SDave Jiang 401bfe1d560SDave Jiang /* bytes 28-31 */ 402bfe1d560SDave Jiang u32 rsvd8; 403b0325aefSDave Jiang 404b0325aefSDave Jiang /* bytes 32-63 */ 405b0325aefSDave Jiang u64 op_config[4]; 406bfe1d560SDave Jiang }; 407b0325aefSDave Jiang u32 bits[16]; 408bfe1d560SDave Jiang } __packed; 409484f910eSDave Jiang 4108e50d392SDave Jiang #define WQCFG_PASID_IDX 2 4113157dd0aSDave Jiang #define WQCFG_PRIVL_IDX 2 412e753a64bSDave Jiang #define WQCFG_OCCUP_IDX 6 413e753a64bSDave Jiang 414e753a64bSDave Jiang #define WQCFG_OCCUP_MASK 0xffff 4158e50d392SDave Jiang 416484f910eSDave Jiang /* 417484f910eSDave Jiang * This macro calculates the offset into the WQCFG register 418484f910eSDave Jiang * idxd - struct idxd * 419484f910eSDave Jiang * n - wq id 420484f910eSDave Jiang * ofs - the index of the 32b dword for the config register 421484f910eSDave Jiang * 422484f910eSDave Jiang * The WQCFG register block is divided into groups per each wq. The n index 423484f910eSDave Jiang * allows us to move to the register group that's for that particular wq. 424484f910eSDave Jiang * Each register is 32bits. The ofs gives us the number of register to access. 425484f910eSDave Jiang */ 426484f910eSDave Jiang #define WQCFG_OFFSET(_idxd_dev, n, ofs) \ 427484f910eSDave Jiang ({\ 428484f910eSDave Jiang typeof(_idxd_dev) __idxd_dev = (_idxd_dev); \ 429484f910eSDave Jiang (__idxd_dev)->wqcfg_offset + (n) * (__idxd_dev)->wqcfg_size + sizeof(u32) * (ofs); \ 430484f910eSDave Jiang }) 431484f910eSDave Jiang 432484f910eSDave Jiang #define WQCFG_STRIDES(_idxd_dev) ((_idxd_dev)->wqcfg_size / sizeof(u32)) 433484f910eSDave Jiang 4345a712701SDave Jiang #define GRPCFG_SIZE 64 4355a712701SDave Jiang #define GRPWQCFG_STRIDES 4 4365a712701SDave Jiang 4375a712701SDave Jiang /* 4385a712701SDave Jiang * This macro calculates the offset into the GRPCFG register 4395a712701SDave Jiang * idxd - struct idxd * 440*0c154698SGuanjun * n - group id 441*0c154698SGuanjun * ofs - the index of the 64b qword for the config register 4425a712701SDave Jiang * 443*0c154698SGuanjun * The GRPCFG register block is divided into three sub-registers, which 444*0c154698SGuanjun * are GRPWQCFG, GRPENGCFG and GRPFLGCFG. The n index allows us to move 445*0c154698SGuanjun * to the register block that contains the three sub-registers. 446*0c154698SGuanjun * Each register block is 64bits. And the ofs gives us the offset 447*0c154698SGuanjun * within the GRPWQCFG register to access. 4485a712701SDave Jiang */ 4495a712701SDave Jiang #define GRPWQCFG_OFFSET(idxd_dev, n, ofs) ((idxd_dev)->grpcfg_offset +\ 4505a712701SDave Jiang (n) * GRPCFG_SIZE + sizeof(u64) * (ofs)) 4515a712701SDave Jiang #define GRPENGCFG_OFFSET(idxd_dev, n) ((idxd_dev)->grpcfg_offset + (n) * GRPCFG_SIZE + 32) 4525a712701SDave Jiang #define GRPFLGCFG_OFFSET(idxd_dev, n) ((idxd_dev)->grpcfg_offset + (n) * GRPCFG_SIZE + 40) 4535a712701SDave Jiang 45481dd4d4dSTom Zanussi /* Following is performance monitor registers */ 45581dd4d4dSTom Zanussi #define IDXD_PERFCAP_OFFSET 0x0 45681dd4d4dSTom Zanussi union idxd_perfcap { 45781dd4d4dSTom Zanussi struct { 45881dd4d4dSTom Zanussi u64 num_perf_counter:6; 45981dd4d4dSTom Zanussi u64 rsvd1:2; 46081dd4d4dSTom Zanussi u64 counter_width:8; 46181dd4d4dSTom Zanussi u64 num_event_category:4; 46281dd4d4dSTom Zanussi u64 global_event_category:16; 46381dd4d4dSTom Zanussi u64 filter:8; 46481dd4d4dSTom Zanussi u64 rsvd2:8; 46581dd4d4dSTom Zanussi u64 cap_per_counter:1; 46681dd4d4dSTom Zanussi u64 writeable_counter:1; 46781dd4d4dSTom Zanussi u64 counter_freeze:1; 46881dd4d4dSTom Zanussi u64 overflow_interrupt:1; 46981dd4d4dSTom Zanussi u64 rsvd3:8; 47081dd4d4dSTom Zanussi }; 47181dd4d4dSTom Zanussi u64 bits; 47281dd4d4dSTom Zanussi } __packed; 47381dd4d4dSTom Zanussi 47481dd4d4dSTom Zanussi #define IDXD_EVNTCAP_OFFSET 0x80 47581dd4d4dSTom Zanussi union idxd_evntcap { 47681dd4d4dSTom Zanussi struct { 47781dd4d4dSTom Zanussi u64 events:28; 47881dd4d4dSTom Zanussi u64 rsvd:36; 47981dd4d4dSTom Zanussi }; 48081dd4d4dSTom Zanussi u64 bits; 48181dd4d4dSTom Zanussi } __packed; 48281dd4d4dSTom Zanussi 48381dd4d4dSTom Zanussi struct idxd_event { 48481dd4d4dSTom Zanussi union { 48581dd4d4dSTom Zanussi struct { 48681dd4d4dSTom Zanussi u32 event_category:4; 48781dd4d4dSTom Zanussi u32 events:28; 48881dd4d4dSTom Zanussi }; 48981dd4d4dSTom Zanussi u32 val; 49081dd4d4dSTom Zanussi }; 49181dd4d4dSTom Zanussi } __packed; 49281dd4d4dSTom Zanussi 49381dd4d4dSTom Zanussi #define IDXD_CNTRCAP_OFFSET 0x800 49481dd4d4dSTom Zanussi struct idxd_cntrcap { 49581dd4d4dSTom Zanussi union { 49681dd4d4dSTom Zanussi struct { 49781dd4d4dSTom Zanussi u32 counter_width:8; 49881dd4d4dSTom Zanussi u32 rsvd:20; 49981dd4d4dSTom Zanussi u32 num_events:4; 50081dd4d4dSTom Zanussi }; 50181dd4d4dSTom Zanussi u32 val; 50281dd4d4dSTom Zanussi }; 50381dd4d4dSTom Zanussi struct idxd_event events[]; 50481dd4d4dSTom Zanussi } __packed; 50581dd4d4dSTom Zanussi 50681dd4d4dSTom Zanussi #define IDXD_PERFRST_OFFSET 0x10 50781dd4d4dSTom Zanussi union idxd_perfrst { 50881dd4d4dSTom Zanussi struct { 50981dd4d4dSTom Zanussi u32 perfrst_config:1; 51081dd4d4dSTom Zanussi u32 perfrst_counter:1; 51181dd4d4dSTom Zanussi u32 rsvd:30; 51281dd4d4dSTom Zanussi }; 51381dd4d4dSTom Zanussi u32 val; 51481dd4d4dSTom Zanussi } __packed; 51581dd4d4dSTom Zanussi 51681dd4d4dSTom Zanussi #define IDXD_OVFSTATUS_OFFSET 0x30 51781dd4d4dSTom Zanussi #define IDXD_PERFFRZ_OFFSET 0x20 51881dd4d4dSTom Zanussi #define IDXD_CNTRCFG_OFFSET 0x100 51981dd4d4dSTom Zanussi union idxd_cntrcfg { 52081dd4d4dSTom Zanussi struct { 52181dd4d4dSTom Zanussi u64 enable:1; 52281dd4d4dSTom Zanussi u64 interrupt_ovf:1; 52381dd4d4dSTom Zanussi u64 global_freeze_ovf:1; 52481dd4d4dSTom Zanussi u64 rsvd1:5; 52581dd4d4dSTom Zanussi u64 event_category:4; 52681dd4d4dSTom Zanussi u64 rsvd2:20; 52781dd4d4dSTom Zanussi u64 events:28; 52881dd4d4dSTom Zanussi u64 rsvd3:4; 52981dd4d4dSTom Zanussi }; 53081dd4d4dSTom Zanussi u64 val; 53181dd4d4dSTom Zanussi } __packed; 53281dd4d4dSTom Zanussi 53381dd4d4dSTom Zanussi #define IDXD_FLTCFG_OFFSET 0x300 53481dd4d4dSTom Zanussi 53581dd4d4dSTom Zanussi #define IDXD_CNTRDATA_OFFSET 0x200 53681dd4d4dSTom Zanussi union idxd_cntrdata { 53781dd4d4dSTom Zanussi struct { 53881dd4d4dSTom Zanussi u64 event_count_value; 53981dd4d4dSTom Zanussi }; 54081dd4d4dSTom Zanussi u64 val; 54181dd4d4dSTom Zanussi } __packed; 54281dd4d4dSTom Zanussi 54381dd4d4dSTom Zanussi union event_cfg { 54481dd4d4dSTom Zanussi struct { 54581dd4d4dSTom Zanussi u64 event_cat:4; 54681dd4d4dSTom Zanussi u64 event_enc:28; 54781dd4d4dSTom Zanussi }; 54881dd4d4dSTom Zanussi u64 val; 54981dd4d4dSTom Zanussi } __packed; 55081dd4d4dSTom Zanussi 55181dd4d4dSTom Zanussi union filter_cfg { 55281dd4d4dSTom Zanussi struct { 55381dd4d4dSTom Zanussi u64 wq:32; 55481dd4d4dSTom Zanussi u64 tc:8; 55581dd4d4dSTom Zanussi u64 pg_sz:4; 55681dd4d4dSTom Zanussi u64 xfer_sz:8; 55781dd4d4dSTom Zanussi u64 eng:8; 55881dd4d4dSTom Zanussi }; 55981dd4d4dSTom Zanussi u64 val; 56081dd4d4dSTom Zanussi } __packed; 56181dd4d4dSTom Zanussi 5622f431ba9SDave Jiang #define IDXD_EVLSTATUS_OFFSET 0xf0 5632f431ba9SDave Jiang 5642f431ba9SDave Jiang union evl_status_reg { 5652f431ba9SDave Jiang struct { 5662f431ba9SDave Jiang u32 head:16; 5672f431ba9SDave Jiang u32 rsvd:16; 5682f431ba9SDave Jiang u32 tail:16; 5692f431ba9SDave Jiang u32 rsvd2:14; 5702f431ba9SDave Jiang u32 int_pending:1; 5712f431ba9SDave Jiang u32 rsvd3:1; 5722f431ba9SDave Jiang }; 5732f431ba9SDave Jiang struct { 5742f431ba9SDave Jiang u32 bits_lower32; 5752f431ba9SDave Jiang u32 bits_upper32; 5762f431ba9SDave Jiang }; 5772f431ba9SDave Jiang u64 bits; 5782f431ba9SDave Jiang } __packed; 5792f431ba9SDave Jiang 5802442b747SDave Jiang #define IDXD_MAX_BATCH_IDENT 256 5812442b747SDave Jiang 582244da66cSDave Jiang struct __evl_entry { 583244da66cSDave Jiang u64 rsvd:2; 584244da66cSDave Jiang u64 desc_valid:1; 585244da66cSDave Jiang u64 wq_idx_valid:1; 586244da66cSDave Jiang u64 batch:1; 587244da66cSDave Jiang u64 fault_rw:1; 588244da66cSDave Jiang u64 priv:1; 589244da66cSDave Jiang u64 err_info_valid:1; 590244da66cSDave Jiang u64 error:8; 591244da66cSDave Jiang u64 wq_idx:8; 592244da66cSDave Jiang u64 batch_id:8; 593244da66cSDave Jiang u64 operation:8; 594244da66cSDave Jiang u64 pasid:20; 595244da66cSDave Jiang u64 rsvd2:4; 596244da66cSDave Jiang 597244da66cSDave Jiang u16 batch_idx; 598244da66cSDave Jiang u16 rsvd3; 599244da66cSDave Jiang union { 600244da66cSDave Jiang /* Invalid Flags 0x11 */ 601244da66cSDave Jiang u32 invalid_flags; 602244da66cSDave Jiang /* Invalid Int Handle 0x19 */ 603244da66cSDave Jiang /* Page fault 0x1a */ 604244da66cSDave Jiang /* Page fault 0x06, 0x1f, only operand_id */ 605244da66cSDave Jiang /* Page fault before drain or in batch, 0x26, 0x27 */ 606244da66cSDave Jiang struct { 607244da66cSDave Jiang u16 int_handle; 608244da66cSDave Jiang u16 rci:1; 609244da66cSDave Jiang u16 ims:1; 610244da66cSDave Jiang u16 rcr:1; 611244da66cSDave Jiang u16 first_err_in_batch:1; 612244da66cSDave Jiang u16 rsvd4_2:9; 613244da66cSDave Jiang u16 operand_id:3; 614244da66cSDave Jiang }; 615244da66cSDave Jiang }; 616244da66cSDave Jiang u64 fault_addr; 617244da66cSDave Jiang u64 rsvd5; 618244da66cSDave Jiang } __packed; 619244da66cSDave Jiang 620244da66cSDave Jiang struct dsa_evl_entry { 621244da66cSDave Jiang struct __evl_entry e; 622244da66cSDave Jiang struct dsa_completion_record cr; 623244da66cSDave Jiang } __packed; 624244da66cSDave Jiang 625244da66cSDave Jiang struct iax_evl_entry { 626244da66cSDave Jiang struct __evl_entry e; 627244da66cSDave Jiang u64 rsvd[4]; 628244da66cSDave Jiang struct iax_completion_record cr; 629244da66cSDave Jiang } __packed; 630244da66cSDave Jiang 631bfe1d560SDave Jiang #endif 632