1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27 #include "dm_services.h"
28 #include "dc.h"
29
30 #include "dcn31/dcn31_init.h"
31
32 #include "resource.h"
33 #include "include/irq_service_interface.h"
34 #include "dcn316_resource.h"
35
36 #include "dcn20/dcn20_resource.h"
37 #include "dcn30/dcn30_resource.h"
38 #include "dcn31/dcn31_resource.h"
39
40 #include "dcn10/dcn10_ipp.h"
41 #include "dcn30/dcn30_hubbub.h"
42 #include "dcn31/dcn31_hubbub.h"
43 #include "dcn30/dcn30_mpc.h"
44 #include "dcn31/dcn31_hubp.h"
45 #include "irq/dcn31/irq_service_dcn31.h"
46 #include "dcn30/dcn30_dpp.h"
47 #include "dcn31/dcn31_optc.h"
48 #include "dcn20/dcn20_hwseq.h"
49 #include "dcn30/dcn30_hwseq.h"
50 #include "dce110/dce110_hwseq.h"
51 #include "dcn30/dcn30_opp.h"
52 #include "dcn20/dcn20_dsc.h"
53 #include "dcn30/dcn30_vpg.h"
54 #include "dcn30/dcn30_afmt.h"
55 #include "dcn30/dcn30_dio_stream_encoder.h"
56 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
57 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
58 #include "dcn31/dcn31_apg.h"
59 #include "dcn31/dcn31_dio_link_encoder.h"
60 #include "dcn31/dcn31_vpg.h"
61 #include "dcn31/dcn31_afmt.h"
62 #include "dce/dce_clock_source.h"
63 #include "dce/dce_audio.h"
64 #include "dce/dce_hwseq.h"
65 #include "clk_mgr.h"
66 #include "virtual/virtual_stream_encoder.h"
67 #include "dce110/dce110_resource.h"
68 #include "dml/display_mode_vba.h"
69 #include "dml/dcn31/dcn31_fpu.h"
70 #include "dcn31/dcn31_dccg.h"
71 #include "dcn10/dcn10_resource.h"
72 #include "dcn31/dcn31_panel_cntl.h"
73
74 #include "dcn30/dcn30_dwb.h"
75 #include "dcn30/dcn30_mmhubbub.h"
76
77 #include "dcn/dcn_3_1_6_offset.h"
78 #include "dcn/dcn_3_1_6_sh_mask.h"
79 #include "dpcs/dpcs_4_2_3_offset.h"
80 #include "dpcs/dpcs_4_2_3_sh_mask.h"
81
82 #define regBIF_BX1_BIOS_SCRATCH_2 0x003a
83 #define regBIF_BX1_BIOS_SCRATCH_2_BASE_IDX 1
84 #define regBIF_BX1_BIOS_SCRATCH_3 0x003b
85 #define regBIF_BX1_BIOS_SCRATCH_3_BASE_IDX 1
86 #define regBIF_BX1_BIOS_SCRATCH_6 0x003e
87 #define regBIF_BX1_BIOS_SCRATCH_6_BASE_IDX 1
88
89 #define regDCHUBBUB_DEBUG_CTRL_0 0x04d6
90 #define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX 2
91 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10
92 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x01FF0000L
93
94 #define DCN_BASE__INST0_SEG0 0x00000012
95 #define DCN_BASE__INST0_SEG1 0x000000C0
96 #define DCN_BASE__INST0_SEG2 0x000034C0
97 #define DCN_BASE__INST0_SEG3 0x00009000
98 #define DCN_BASE__INST0_SEG4 0x02403C00
99 #define DCN_BASE__INST0_SEG5 0
100
101 #define DPCS_BASE__INST0_SEG0 0x00000012
102 #define DPCS_BASE__INST0_SEG1 0x000000C0
103 #define DPCS_BASE__INST0_SEG2 0x000034C0
104 #define DPCS_BASE__INST0_SEG3 0x00009000
105 #define DPCS_BASE__INST0_SEG4 0x02403C00
106 #define DPCS_BASE__INST0_SEG5 0
107
108 #define NBIO_BASE__INST0_SEG0 0x00000000
109 #define NBIO_BASE__INST0_SEG1 0x00000014
110 #define NBIO_BASE__INST0_SEG2 0x00000D20
111 #define NBIO_BASE__INST0_SEG3 0x00010400
112 #define NBIO_BASE__INST0_SEG4 0x0241B000
113 #define NBIO_BASE__INST0_SEG5 0x04040000
114
115 #include "reg_helper.h"
116 #include "dce/dmub_abm.h"
117 #include "dce/dmub_psr.h"
118 #include "dce/dce_aux.h"
119 #include "dce/dce_i2c.h"
120
121 #include "dml/dcn30/display_mode_vba_30.h"
122 #include "vm_helper.h"
123 #include "dcn20/dcn20_vmid.h"
124
125 #include "link_enc_cfg.h"
126
127 #define DCN3_16_MAX_DET_SIZE 384
128 #define DCN3_16_CRB_SEGMENT_SIZE_KB 64
129
130 enum dcn31_clk_src_array_id {
131 DCN31_CLK_SRC_PLL0,
132 DCN31_CLK_SRC_PLL1,
133 DCN31_CLK_SRC_PLL2,
134 DCN31_CLK_SRC_PLL3,
135 DCN31_CLK_SRC_PLL4,
136 DCN30_CLK_SRC_TOTAL
137 };
138
139 /* begin *********************
140 * macros to expend register list macro defined in HW object header file
141 */
142
143 /* DCN */
144 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
145
146 #define BASE(seg) BASE_INNER(seg)
147
148 #define SR(reg_name)\
149 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
150 reg ## reg_name
151
152 #define SRI(reg_name, block, id)\
153 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
154 reg ## block ## id ## _ ## reg_name
155
156 #define SRI2(reg_name, block, id)\
157 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
158 reg ## reg_name
159
160 #define SRIR(var_name, reg_name, block, id)\
161 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
162 reg ## block ## id ## _ ## reg_name
163
164 #define SRII(reg_name, block, id)\
165 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
166 reg ## block ## id ## _ ## reg_name
167
168 #define SRII_MPC_RMU(reg_name, block, id)\
169 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
170 reg ## block ## id ## _ ## reg_name
171
172 #define SRII_DWB(reg_name, temp_name, block, id)\
173 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
174 reg ## block ## id ## _ ## temp_name
175
176 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \
177 .field_name = reg_name ## __ ## field_name ## post_fix
178
179 #define DCCG_SRII(reg_name, block, id)\
180 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
181 reg ## block ## id ## _ ## reg_name
182
183 #define VUPDATE_SRII(reg_name, block, id)\
184 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
185 reg ## reg_name ## _ ## block ## id
186
187 /* NBIO */
188 #define NBIO_BASE_INNER(seg) \
189 NBIO_BASE__INST0_SEG ## seg
190
191 #define NBIO_BASE(seg) \
192 NBIO_BASE_INNER(seg)
193
194 #define NBIO_SR(reg_name)\
195 .reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \
196 regBIF_BX1_ ## reg_name
197
198 static const struct bios_registers bios_regs = {
199 NBIO_SR(BIOS_SCRATCH_3),
200 NBIO_SR(BIOS_SCRATCH_6)
201 };
202
203 #define clk_src_regs(index, pllid)\
204 [index] = {\
205 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\
206 }
207
208 static const struct dce110_clk_src_regs clk_src_regs[] = {
209 clk_src_regs(0, A),
210 clk_src_regs(1, B),
211 clk_src_regs(2, C),
212 clk_src_regs(3, D),
213 clk_src_regs(4, E)
214 };
215
216 static const struct dce110_clk_src_shift cs_shift = {
217 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
218 };
219
220 static const struct dce110_clk_src_mask cs_mask = {
221 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
222 };
223
224 #define abm_regs(id)\
225 [id] = {\
226 ABM_DCN302_REG_LIST(id)\
227 }
228
229 static const struct dce_abm_registers abm_regs[] = {
230 abm_regs(0),
231 abm_regs(1),
232 abm_regs(2),
233 abm_regs(3),
234 };
235
236 static const struct dce_abm_shift abm_shift = {
237 ABM_MASK_SH_LIST_DCN30(__SHIFT)
238 };
239
240 static const struct dce_abm_mask abm_mask = {
241 ABM_MASK_SH_LIST_DCN30(_MASK)
242 };
243
244 #define audio_regs(id)\
245 [id] = {\
246 AUD_COMMON_REG_LIST(id)\
247 }
248
249 static const struct dce_audio_registers audio_regs[] = {
250 audio_regs(0),
251 audio_regs(1),
252 audio_regs(2),
253 audio_regs(3),
254 audio_regs(4),
255 audio_regs(5),
256 audio_regs(6)
257 };
258
259 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
260 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
261 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
262 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
263
264 static const struct dce_audio_shift audio_shift = {
265 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
266 };
267
268 static const struct dce_audio_mask audio_mask = {
269 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
270 };
271
272 #define vpg_regs(id)\
273 [id] = {\
274 VPG_DCN31_REG_LIST(id)\
275 }
276
277 static const struct dcn31_vpg_registers vpg_regs[] = {
278 vpg_regs(0),
279 vpg_regs(1),
280 vpg_regs(2),
281 vpg_regs(3),
282 vpg_regs(4),
283 vpg_regs(5),
284 vpg_regs(6),
285 vpg_regs(7),
286 vpg_regs(8),
287 vpg_regs(9),
288 };
289
290 static const struct dcn31_vpg_shift vpg_shift = {
291 DCN31_VPG_MASK_SH_LIST(__SHIFT)
292 };
293
294 static const struct dcn31_vpg_mask vpg_mask = {
295 DCN31_VPG_MASK_SH_LIST(_MASK)
296 };
297
298 #define afmt_regs(id)\
299 [id] = {\
300 AFMT_DCN31_REG_LIST(id)\
301 }
302
303 static const struct dcn31_afmt_registers afmt_regs[] = {
304 afmt_regs(0),
305 afmt_regs(1),
306 afmt_regs(2),
307 afmt_regs(3),
308 afmt_regs(4),
309 afmt_regs(5)
310 };
311
312 static const struct dcn31_afmt_shift afmt_shift = {
313 DCN31_AFMT_MASK_SH_LIST(__SHIFT)
314 };
315
316 static const struct dcn31_afmt_mask afmt_mask = {
317 DCN31_AFMT_MASK_SH_LIST(_MASK)
318 };
319
320
321 #define apg_regs(id)\
322 [id] = {\
323 APG_DCN31_REG_LIST(id)\
324 }
325
326 static const struct dcn31_apg_registers apg_regs[] = {
327 apg_regs(0),
328 apg_regs(1),
329 apg_regs(2),
330 apg_regs(3)
331 };
332
333 static const struct dcn31_apg_shift apg_shift = {
334 DCN31_APG_MASK_SH_LIST(__SHIFT)
335 };
336
337 static const struct dcn31_apg_mask apg_mask = {
338 DCN31_APG_MASK_SH_LIST(_MASK)
339 };
340
341
342 #define stream_enc_regs(id)\
343 [id] = {\
344 SE_DCN3_REG_LIST(id)\
345 }
346
347 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
348 stream_enc_regs(0),
349 stream_enc_regs(1),
350 stream_enc_regs(2),
351 stream_enc_regs(3),
352 stream_enc_regs(4)
353 };
354
355 static const struct dcn10_stream_encoder_shift se_shift = {
356 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
357 };
358
359 static const struct dcn10_stream_encoder_mask se_mask = {
360 SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
361 };
362
363
364 #define aux_regs(id)\
365 [id] = {\
366 DCN2_AUX_REG_LIST(id)\
367 }
368
369 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
370 aux_regs(0),
371 aux_regs(1),
372 aux_regs(2),
373 aux_regs(3),
374 aux_regs(4)
375 };
376
377 #define hpd_regs(id)\
378 [id] = {\
379 HPD_REG_LIST(id)\
380 }
381
382 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
383 hpd_regs(0),
384 hpd_regs(1),
385 hpd_regs(2),
386 hpd_regs(3),
387 hpd_regs(4)
388 };
389
390 #define link_regs(id, phyid)\
391 [id] = {\
392 LE_DCN31_REG_LIST(id), \
393 UNIPHY_DCN2_REG_LIST(phyid), \
394 DPCS_DCN31_REG_LIST(id), \
395 }
396
397 static const struct dce110_aux_registers_shift aux_shift = {
398 DCN_AUX_MASK_SH_LIST(__SHIFT)
399 };
400
401 static const struct dce110_aux_registers_mask aux_mask = {
402 DCN_AUX_MASK_SH_LIST(_MASK)
403 };
404
405 static const struct dcn10_link_enc_registers link_enc_regs[] = {
406 link_regs(0, A),
407 link_regs(1, B),
408 link_regs(2, C),
409 link_regs(3, D),
410 link_regs(4, E)
411 };
412
413 static const struct dcn10_link_enc_shift le_shift = {
414 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \
415 DPCS_DCN31_MASK_SH_LIST(__SHIFT)
416 };
417
418 static const struct dcn10_link_enc_mask le_mask = {
419 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \
420 DPCS_DCN31_MASK_SH_LIST(_MASK)
421 };
422
423
424
425 #define hpo_dp_stream_encoder_reg_list(id)\
426 [id] = {\
427 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\
428 }
429
430 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = {
431 hpo_dp_stream_encoder_reg_list(0),
432 hpo_dp_stream_encoder_reg_list(1),
433 hpo_dp_stream_encoder_reg_list(2),
434 hpo_dp_stream_encoder_reg_list(3),
435 };
436
437 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
438 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
439 };
440
441 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
442 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
443 };
444
445
446 #define hpo_dp_link_encoder_reg_list(id)\
447 [id] = {\
448 DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\
449 DCN3_1_RDPCSTX_REG_LIST(0),\
450 DCN3_1_RDPCSTX_REG_LIST(1),\
451 DCN3_1_RDPCSTX_REG_LIST(2),\
452 DCN3_1_RDPCSTX_REG_LIST(3),\
453 DCN3_1_RDPCSTX_REG_LIST(4)\
454 }
455
456 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = {
457 hpo_dp_link_encoder_reg_list(0),
458 hpo_dp_link_encoder_reg_list(1),
459 };
460
461 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
462 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
463 };
464
465 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
466 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
467 };
468
469
470 #define dpp_regs(id)\
471 [id] = {\
472 DPP_REG_LIST_DCN30(id),\
473 }
474
475 static const struct dcn3_dpp_registers dpp_regs[] = {
476 dpp_regs(0),
477 dpp_regs(1),
478 dpp_regs(2),
479 dpp_regs(3)
480 };
481
482 static const struct dcn3_dpp_shift tf_shift = {
483 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
484 };
485
486 static const struct dcn3_dpp_mask tf_mask = {
487 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
488 };
489
490 #define opp_regs(id)\
491 [id] = {\
492 OPP_REG_LIST_DCN30(id),\
493 }
494
495 static const struct dcn20_opp_registers opp_regs[] = {
496 opp_regs(0),
497 opp_regs(1),
498 opp_regs(2),
499 opp_regs(3)
500 };
501
502 static const struct dcn20_opp_shift opp_shift = {
503 OPP_MASK_SH_LIST_DCN20(__SHIFT)
504 };
505
506 static const struct dcn20_opp_mask opp_mask = {
507 OPP_MASK_SH_LIST_DCN20(_MASK)
508 };
509
510 #define aux_engine_regs(id)\
511 [id] = {\
512 AUX_COMMON_REG_LIST0(id), \
513 .AUXN_IMPCAL = 0, \
514 .AUXP_IMPCAL = 0, \
515 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
516 }
517
518 static const struct dce110_aux_registers aux_engine_regs[] = {
519 aux_engine_regs(0),
520 aux_engine_regs(1),
521 aux_engine_regs(2),
522 aux_engine_regs(3),
523 aux_engine_regs(4)
524 };
525
526 #define dwbc_regs_dcn3(id)\
527 [id] = {\
528 DWBC_COMMON_REG_LIST_DCN30(id),\
529 }
530
531 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
532 dwbc_regs_dcn3(0),
533 };
534
535 static const struct dcn30_dwbc_shift dwbc30_shift = {
536 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
537 };
538
539 static const struct dcn30_dwbc_mask dwbc30_mask = {
540 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
541 };
542
543 #define mcif_wb_regs_dcn3(id)\
544 [id] = {\
545 MCIF_WB_COMMON_REG_LIST_DCN30(id),\
546 }
547
548 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
549 mcif_wb_regs_dcn3(0)
550 };
551
552 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
553 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
554 };
555
556 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
557 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
558 };
559
560 #define dsc_regsDCN20(id)\
561 [id] = {\
562 DSC_REG_LIST_DCN20(id)\
563 }
564
565 static const struct dcn20_dsc_registers dsc_regs[] = {
566 dsc_regsDCN20(0),
567 dsc_regsDCN20(1),
568 dsc_regsDCN20(2)
569 };
570
571 static const struct dcn20_dsc_shift dsc_shift = {
572 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
573 };
574
575 static const struct dcn20_dsc_mask dsc_mask = {
576 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
577 };
578
579 static const struct dcn30_mpc_registers mpc_regs = {
580 MPC_REG_LIST_DCN3_0(0),
581 MPC_REG_LIST_DCN3_0(1),
582 MPC_REG_LIST_DCN3_0(2),
583 MPC_REG_LIST_DCN3_0(3),
584 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
585 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
586 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
587 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
588 MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
589 MPC_RMU_REG_LIST_DCN3AG(0),
590 MPC_RMU_REG_LIST_DCN3AG(1),
591 //MPC_RMU_REG_LIST_DCN3AG(2),
592 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
593 };
594
595 static const struct dcn30_mpc_shift mpc_shift = {
596 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
597 };
598
599 static const struct dcn30_mpc_mask mpc_mask = {
600 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
601 };
602
603 #define optc_regs(id)\
604 [id] = {OPTC_COMMON_REG_LIST_DCN3_1(id)}
605
606 static const struct dcn_optc_registers optc_regs[] = {
607 optc_regs(0),
608 optc_regs(1),
609 optc_regs(2),
610 optc_regs(3)
611 };
612
613 static const struct dcn_optc_shift optc_shift = {
614 OPTC_COMMON_MASK_SH_LIST_DCN3_1(__SHIFT)
615 };
616
617 static const struct dcn_optc_mask optc_mask = {
618 OPTC_COMMON_MASK_SH_LIST_DCN3_1(_MASK)
619 };
620
621 #define hubp_regs(id)\
622 [id] = {\
623 HUBP_REG_LIST_DCN30(id)\
624 }
625
626 static const struct dcn_hubp2_registers hubp_regs[] = {
627 hubp_regs(0),
628 hubp_regs(1),
629 hubp_regs(2),
630 hubp_regs(3)
631 };
632
633
634 static const struct dcn_hubp2_shift hubp_shift = {
635 HUBP_MASK_SH_LIST_DCN31(__SHIFT)
636 };
637
638 static const struct dcn_hubp2_mask hubp_mask = {
639 HUBP_MASK_SH_LIST_DCN31(_MASK)
640 };
641 static const struct dcn_hubbub_registers hubbub_reg = {
642 HUBBUB_REG_LIST_DCN31(0)
643 };
644
645 static const struct dcn_hubbub_shift hubbub_shift = {
646 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT)
647 };
648
649 static const struct dcn_hubbub_mask hubbub_mask = {
650 HUBBUB_MASK_SH_LIST_DCN31(_MASK)
651 };
652
653 static const struct dccg_registers dccg_regs = {
654 DCCG_REG_LIST_DCN31()
655 };
656
657 static const struct dccg_shift dccg_shift = {
658 DCCG_MASK_SH_LIST_DCN31(__SHIFT)
659 };
660
661 static const struct dccg_mask dccg_mask = {
662 DCCG_MASK_SH_LIST_DCN31(_MASK)
663 };
664
665
666 #define SRII2(reg_name_pre, reg_name_post, id)\
667 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
668 ## id ## _ ## reg_name_post ## _BASE_IDX) + \
669 reg ## reg_name_pre ## id ## _ ## reg_name_post
670
671
672 #define HWSEQ_DCN31_REG_LIST()\
673 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
674 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
675 SR(DIO_MEM_PWR_CTRL), \
676 SR(ODM_MEM_PWR_CTRL3), \
677 SR(DMU_MEM_PWR_CNTL), \
678 SR(MMHUBBUB_MEM_PWR_CNTL), \
679 SR(DCCG_GATE_DISABLE_CNTL), \
680 SR(DCCG_GATE_DISABLE_CNTL2), \
681 SR(DCFCLK_CNTL),\
682 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
683 SRII(PIXEL_RATE_CNTL, OTG, 0), \
684 SRII(PIXEL_RATE_CNTL, OTG, 1),\
685 SRII(PIXEL_RATE_CNTL, OTG, 2),\
686 SRII(PIXEL_RATE_CNTL, OTG, 3),\
687 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
688 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
689 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
690 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
691 SR(MICROSECOND_TIME_BASE_DIV), \
692 SR(MILLISECOND_TIME_BASE_DIV), \
693 SR(DISPCLK_FREQ_CHANGE_CNTL), \
694 SR(RBBMIF_TIMEOUT_DIS), \
695 SR(RBBMIF_TIMEOUT_DIS_2), \
696 SR(DCHUBBUB_CRC_CTRL), \
697 SR(DPP_TOP0_DPP_CRC_CTRL), \
698 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
699 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
700 SR(MPC_CRC_CTRL), \
701 SR(MPC_CRC_RESULT_GB), \
702 SR(MPC_CRC_RESULT_C), \
703 SR(MPC_CRC_RESULT_AR), \
704 SR(DOMAIN0_PG_CONFIG), \
705 SR(DOMAIN1_PG_CONFIG), \
706 SR(DOMAIN2_PG_CONFIG), \
707 SR(DOMAIN3_PG_CONFIG), \
708 SR(DOMAIN16_PG_CONFIG), \
709 SR(DOMAIN17_PG_CONFIG), \
710 SR(DOMAIN18_PG_CONFIG), \
711 SR(DOMAIN0_PG_STATUS), \
712 SR(DOMAIN1_PG_STATUS), \
713 SR(DOMAIN2_PG_STATUS), \
714 SR(DOMAIN3_PG_STATUS), \
715 SR(DOMAIN16_PG_STATUS), \
716 SR(DOMAIN17_PG_STATUS), \
717 SR(DOMAIN18_PG_STATUS), \
718 SR(D1VGA_CONTROL), \
719 SR(D2VGA_CONTROL), \
720 SR(D3VGA_CONTROL), \
721 SR(D4VGA_CONTROL), \
722 SR(D5VGA_CONTROL), \
723 SR(D6VGA_CONTROL), \
724 SR(DC_IP_REQUEST_CNTL), \
725 SR(AZALIA_AUDIO_DTO), \
726 SR(AZALIA_CONTROLLER_CLOCK_GATING), \
727 SR(HPO_TOP_HW_CONTROL)
728
729 static const struct dce_hwseq_registers hwseq_reg = {
730 HWSEQ_DCN31_REG_LIST()
731 };
732
733 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\
734 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
735 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
736 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \
737 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
738 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
739 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
740 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
741 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
742 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
743 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
744 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
745 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
746 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
747 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
748 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
749 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
750 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
751 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
752 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
753 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
754 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
755 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
756 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
757 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
758 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
759 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
760 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
761 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \
762 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
763 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
764 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \
765 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
766 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh)
767
768 static const struct dce_hwseq_shift hwseq_shift = {
769 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT)
770 };
771
772 static const struct dce_hwseq_mask hwseq_mask = {
773 HWSEQ_DCN31_MASK_SH_LIST(_MASK)
774 };
775 #define vmid_regs(id)\
776 [id] = {\
777 DCN20_VMID_REG_LIST(id)\
778 }
779
780 static const struct dcn_vmid_registers vmid_regs[] = {
781 vmid_regs(0),
782 vmid_regs(1),
783 vmid_regs(2),
784 vmid_regs(3),
785 vmid_regs(4),
786 vmid_regs(5),
787 vmid_regs(6),
788 vmid_regs(7),
789 vmid_regs(8),
790 vmid_regs(9),
791 vmid_regs(10),
792 vmid_regs(11),
793 vmid_regs(12),
794 vmid_regs(13),
795 vmid_regs(14),
796 vmid_regs(15)
797 };
798
799 static const struct dcn20_vmid_shift vmid_shifts = {
800 DCN20_VMID_MASK_SH_LIST(__SHIFT)
801 };
802
803 static const struct dcn20_vmid_mask vmid_masks = {
804 DCN20_VMID_MASK_SH_LIST(_MASK)
805 };
806
807 static const struct resource_caps res_cap_dcn31 = {
808 .num_timing_generator = 4,
809 .num_opp = 4,
810 .num_video_plane = 4,
811 .num_audio = 5,
812 .num_stream_encoder = 5,
813 .num_dig_link_enc = 5,
814 .num_hpo_dp_stream_encoder = 4,
815 .num_hpo_dp_link_encoder = 2,
816 .num_pll = 5,
817 .num_dwb = 1,
818 .num_ddc = 5,
819 .num_vmid = 16,
820 .num_mpc_3dlut = 2,
821 .num_dsc = 3,
822 };
823
824 static const struct dc_plane_cap plane_cap = {
825 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
826 .per_pixel_alpha = true,
827
828 .pixel_format_support = {
829 .argb8888 = true,
830 .nv12 = true,
831 .fp16 = true,
832 .p010 = true,
833 .ayuv = false,
834 },
835
836 .max_upscale_factor = {
837 .argb8888 = 16000,
838 .nv12 = 16000,
839 .fp16 = 16000
840 },
841
842 // 6:1 downscaling ratio: 1000/6 = 166.666
843 .max_downscale_factor = {
844 .argb8888 = 167,
845 .nv12 = 167,
846 .fp16 = 167
847 },
848 64,
849 64
850 };
851
852 static const struct dc_debug_options debug_defaults_drv = {
853 .disable_z10 = true, /*hw not support it*/
854 .disable_dmcu = true,
855 .force_abm_enable = false,
856 .timing_trace = false,
857 .clock_trace = true,
858 .disable_pplib_clock_request = false,
859 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
860 .force_single_disp_pipe_split = false,
861 .disable_dcc = DCC_ENABLE,
862 .vsr_support = true,
863 .performance_trace = false,
864 .max_downscale_src_width = 4096,/*upto true 4k*/
865 .disable_pplib_wm_range = false,
866 .scl_reset_length10 = true,
867 .sanity_checks = false,
868 .underflow_assert_delay_us = 0xFFFFFFFF,
869 .dwb_fi_phase = -1, // -1 = disable,
870 .dmub_command_table = true,
871 .pstate_enabled = true,
872 .use_max_lb = true,
873 .enable_mem_low_power = {
874 .bits = {
875 .vga = true,
876 .i2c = true,
877 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
878 .dscl = true,
879 .cm = true,
880 .mpc = true,
881 .optc = true,
882 .vpg = true,
883 .afmt = true,
884 }
885 },
886 .enable_legacy_fast_update = true,
887 .using_dml2 = false,
888 };
889
890 static const struct dc_panel_config panel_config_defaults = {
891 .psr = {
892 .disable_psr = false,
893 .disallow_psrsu = false,
894 .disallow_replay = false,
895 },
896 .ilr = {
897 .optimize_edp_link_rate = true,
898 },
899 };
900
dcn31_dpp_destroy(struct dpp ** dpp)901 static void dcn31_dpp_destroy(struct dpp **dpp)
902 {
903 kfree(TO_DCN20_DPP(*dpp));
904 *dpp = NULL;
905 }
906
dcn31_dpp_create(struct dc_context * ctx,uint32_t inst)907 static struct dpp *dcn31_dpp_create(
908 struct dc_context *ctx,
909 uint32_t inst)
910 {
911 struct dcn3_dpp *dpp =
912 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
913
914 if (!dpp)
915 return NULL;
916
917 if (dpp3_construct(dpp, ctx, inst,
918 &dpp_regs[inst], &tf_shift, &tf_mask))
919 return &dpp->base;
920
921 BREAK_TO_DEBUGGER();
922 kfree(dpp);
923 return NULL;
924 }
925
dcn31_opp_create(struct dc_context * ctx,uint32_t inst)926 static struct output_pixel_processor *dcn31_opp_create(
927 struct dc_context *ctx, uint32_t inst)
928 {
929 struct dcn20_opp *opp =
930 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
931
932 if (!opp) {
933 BREAK_TO_DEBUGGER();
934 return NULL;
935 }
936
937 dcn20_opp_construct(opp, ctx, inst,
938 &opp_regs[inst], &opp_shift, &opp_mask);
939 return &opp->base;
940 }
941
dcn31_aux_engine_create(struct dc_context * ctx,uint32_t inst)942 static struct dce_aux *dcn31_aux_engine_create(
943 struct dc_context *ctx,
944 uint32_t inst)
945 {
946 struct aux_engine_dce110 *aux_engine =
947 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
948
949 if (!aux_engine)
950 return NULL;
951
952 dce110_aux_engine_construct(aux_engine, ctx, inst,
953 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
954 &aux_engine_regs[inst],
955 &aux_mask,
956 &aux_shift,
957 ctx->dc->caps.extended_aux_timeout_support);
958
959 return &aux_engine->base;
960 }
961 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
962
963 static const struct dce_i2c_registers i2c_hw_regs[] = {
964 i2c_inst_regs(1),
965 i2c_inst_regs(2),
966 i2c_inst_regs(3),
967 i2c_inst_regs(4),
968 i2c_inst_regs(5),
969 };
970
971 static const struct dce_i2c_shift i2c_shifts = {
972 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
973 };
974
975 static const struct dce_i2c_mask i2c_masks = {
976 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
977 };
978
dcn31_i2c_hw_create(struct dc_context * ctx,uint32_t inst)979 static struct dce_i2c_hw *dcn31_i2c_hw_create(
980 struct dc_context *ctx,
981 uint32_t inst)
982 {
983 struct dce_i2c_hw *dce_i2c_hw =
984 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
985
986 if (!dce_i2c_hw)
987 return NULL;
988
989 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
990 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
991
992 return dce_i2c_hw;
993 }
dcn31_mpc_create(struct dc_context * ctx,int num_mpcc,int num_rmu)994 static struct mpc *dcn31_mpc_create(
995 struct dc_context *ctx,
996 int num_mpcc,
997 int num_rmu)
998 {
999 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
1000 GFP_KERNEL);
1001
1002 if (!mpc30)
1003 return NULL;
1004
1005 dcn30_mpc_construct(mpc30, ctx,
1006 &mpc_regs,
1007 &mpc_shift,
1008 &mpc_mask,
1009 num_mpcc,
1010 num_rmu);
1011
1012 return &mpc30->base;
1013 }
1014
dcn31_hubbub_create(struct dc_context * ctx)1015 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx)
1016 {
1017 int i;
1018
1019 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
1020 GFP_KERNEL);
1021
1022 if (!hubbub3)
1023 return NULL;
1024
1025 hubbub31_construct(hubbub3, ctx,
1026 &hubbub_reg,
1027 &hubbub_shift,
1028 &hubbub_mask,
1029 dcn3_16_ip.det_buffer_size_kbytes,
1030 dcn3_16_ip.pixel_chunk_size_kbytes,
1031 dcn3_16_ip.config_return_buffer_size_in_kbytes);
1032
1033
1034 for (i = 0; i < res_cap_dcn31.num_vmid; i++) {
1035 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1036
1037 vmid->ctx = ctx;
1038
1039 vmid->regs = &vmid_regs[i];
1040 vmid->shifts = &vmid_shifts;
1041 vmid->masks = &vmid_masks;
1042 }
1043
1044 return &hubbub3->base;
1045 }
1046
dcn31_timing_generator_create(struct dc_context * ctx,uint32_t instance)1047 static struct timing_generator *dcn31_timing_generator_create(
1048 struct dc_context *ctx,
1049 uint32_t instance)
1050 {
1051 struct optc *tgn10 =
1052 kzalloc(sizeof(struct optc), GFP_KERNEL);
1053
1054 if (!tgn10)
1055 return NULL;
1056
1057 tgn10->base.inst = instance;
1058 tgn10->base.ctx = ctx;
1059
1060 tgn10->tg_regs = &optc_regs[instance];
1061 tgn10->tg_shift = &optc_shift;
1062 tgn10->tg_mask = &optc_mask;
1063
1064 dcn31_timing_generator_init(tgn10);
1065
1066 return &tgn10->base;
1067 }
1068
1069 static const struct encoder_feature_support link_enc_feature = {
1070 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1071 .max_hdmi_pixel_clock = 600000,
1072 .hdmi_ycbcr420_supported = true,
1073 .dp_ycbcr420_supported = true,
1074 .fec_supported = true,
1075 .flags.bits.IS_HBR2_CAPABLE = true,
1076 .flags.bits.IS_HBR3_CAPABLE = true,
1077 .flags.bits.IS_TPS3_CAPABLE = true,
1078 .flags.bits.IS_TPS4_CAPABLE = true
1079 };
1080
dcn31_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)1081 static struct link_encoder *dcn31_link_encoder_create(
1082 struct dc_context *ctx,
1083 const struct encoder_init_data *enc_init_data)
1084 {
1085 struct dcn20_link_encoder *enc20 =
1086 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1087
1088 if (!enc20)
1089 return NULL;
1090
1091 dcn31_link_encoder_construct(enc20,
1092 enc_init_data,
1093 &link_enc_feature,
1094 &link_enc_regs[enc_init_data->transmitter],
1095 &link_enc_aux_regs[enc_init_data->channel - 1],
1096 &link_enc_hpd_regs[enc_init_data->hpd_source],
1097 &le_shift,
1098 &le_mask);
1099
1100 return &enc20->enc10.base;
1101 }
1102
1103 /* Create a minimal link encoder object not associated with a particular
1104 * physical connector.
1105 * resource_funcs.link_enc_create_minimal
1106 */
dcn31_link_enc_create_minimal(struct dc_context * ctx,enum engine_id eng_id)1107 static struct link_encoder *dcn31_link_enc_create_minimal(
1108 struct dc_context *ctx, enum engine_id eng_id)
1109 {
1110 struct dcn20_link_encoder *enc20;
1111
1112 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
1113 return NULL;
1114
1115 enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1116 if (!enc20)
1117 return NULL;
1118
1119 dcn31_link_encoder_construct_minimal(
1120 enc20,
1121 ctx,
1122 &link_enc_feature,
1123 &link_enc_regs[eng_id - ENGINE_ID_DIGA],
1124 eng_id);
1125
1126 return &enc20->enc10.base;
1127 }
1128
dcn31_panel_cntl_create(const struct panel_cntl_init_data * init_data)1129 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1130 {
1131 struct dcn31_panel_cntl *panel_cntl =
1132 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL);
1133
1134 if (!panel_cntl)
1135 return NULL;
1136
1137 dcn31_panel_cntl_construct(panel_cntl, init_data);
1138
1139 return &panel_cntl->base;
1140 }
1141
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)1142 static void read_dce_straps(
1143 struct dc_context *ctx,
1144 struct resource_straps *straps)
1145 {
1146 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1147 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1148
1149 }
1150
dcn31_create_audio(struct dc_context * ctx,unsigned int inst)1151 static struct audio *dcn31_create_audio(
1152 struct dc_context *ctx, unsigned int inst)
1153 {
1154 return dce_audio_create(ctx, inst,
1155 &audio_regs[inst], &audio_shift, &audio_mask);
1156 }
1157
dcn31_vpg_create(struct dc_context * ctx,uint32_t inst)1158 static struct vpg *dcn31_vpg_create(
1159 struct dc_context *ctx,
1160 uint32_t inst)
1161 {
1162 struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL);
1163
1164 if (!vpg31)
1165 return NULL;
1166
1167 vpg31_construct(vpg31, ctx, inst,
1168 &vpg_regs[inst],
1169 &vpg_shift,
1170 &vpg_mask);
1171
1172 return &vpg31->base;
1173 }
1174
dcn31_afmt_create(struct dc_context * ctx,uint32_t inst)1175 static struct afmt *dcn31_afmt_create(
1176 struct dc_context *ctx,
1177 uint32_t inst)
1178 {
1179 struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL);
1180
1181 if (!afmt31)
1182 return NULL;
1183
1184 afmt31_construct(afmt31, ctx, inst,
1185 &afmt_regs[inst],
1186 &afmt_shift,
1187 &afmt_mask);
1188
1189 // Light sleep by default, no need to power down here
1190
1191 return &afmt31->base;
1192 }
1193
1194
dcn31_apg_create(struct dc_context * ctx,uint32_t inst)1195 static struct apg *dcn31_apg_create(
1196 struct dc_context *ctx,
1197 uint32_t inst)
1198 {
1199 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
1200
1201 if (!apg31)
1202 return NULL;
1203
1204 apg31_construct(apg31, ctx, inst,
1205 &apg_regs[inst],
1206 &apg_shift,
1207 &apg_mask);
1208
1209 return &apg31->base;
1210 }
1211
1212
dcn316_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1213 static struct stream_encoder *dcn316_stream_encoder_create(
1214 enum engine_id eng_id,
1215 struct dc_context *ctx)
1216 {
1217 struct dcn10_stream_encoder *enc1;
1218 struct vpg *vpg;
1219 struct afmt *afmt;
1220 int vpg_inst;
1221 int afmt_inst;
1222
1223 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1224 if (eng_id <= ENGINE_ID_DIGF) {
1225 vpg_inst = eng_id;
1226 afmt_inst = eng_id;
1227 } else
1228 return NULL;
1229
1230 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1231 vpg = dcn31_vpg_create(ctx, vpg_inst);
1232 afmt = dcn31_afmt_create(ctx, afmt_inst);
1233
1234 if (!enc1 || !vpg || !afmt) {
1235 kfree(enc1);
1236 kfree(vpg);
1237 kfree(afmt);
1238 return NULL;
1239 }
1240
1241 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1242 eng_id, vpg, afmt,
1243 &stream_enc_regs[eng_id],
1244 &se_shift, &se_mask);
1245
1246 return &enc1->base;
1247 }
1248
1249
dcn31_hpo_dp_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1250 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create(
1251 enum engine_id eng_id,
1252 struct dc_context *ctx)
1253 {
1254 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1255 struct vpg *vpg;
1256 struct apg *apg;
1257 uint32_t hpo_dp_inst;
1258 uint32_t vpg_inst;
1259 uint32_t apg_inst;
1260
1261 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1262 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1263
1264 /* Mapping of VPG register blocks to HPO DP block instance:
1265 * VPG[6] -> HPO_DP[0]
1266 * VPG[7] -> HPO_DP[1]
1267 * VPG[8] -> HPO_DP[2]
1268 * VPG[9] -> HPO_DP[3]
1269 */
1270 vpg_inst = hpo_dp_inst + 6;
1271
1272 /* Mapping of APG register blocks to HPO DP block instance:
1273 * APG[0] -> HPO_DP[0]
1274 * APG[1] -> HPO_DP[1]
1275 * APG[2] -> HPO_DP[2]
1276 * APG[3] -> HPO_DP[3]
1277 */
1278 apg_inst = hpo_dp_inst;
1279
1280 /* allocate HPO stream encoder and create VPG sub-block */
1281 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
1282 vpg = dcn31_vpg_create(ctx, vpg_inst);
1283 apg = dcn31_apg_create(ctx, apg_inst);
1284
1285 if (!hpo_dp_enc31 || !vpg || !apg) {
1286 kfree(hpo_dp_enc31);
1287 kfree(vpg);
1288 kfree(apg);
1289 return NULL;
1290 }
1291
1292 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1293 hpo_dp_inst, eng_id, vpg, apg,
1294 &hpo_dp_stream_enc_regs[hpo_dp_inst],
1295 &hpo_dp_se_shift, &hpo_dp_se_mask);
1296
1297 return &hpo_dp_enc31->base;
1298 }
1299
dcn31_hpo_dp_link_encoder_create(uint8_t inst,struct dc_context * ctx)1300 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(
1301 uint8_t inst,
1302 struct dc_context *ctx)
1303 {
1304 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1305
1306 /* allocate HPO link encoder */
1307 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
1308 if (!hpo_dp_enc31)
1309 return NULL; /* out of memory */
1310
1311 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
1312 &hpo_dp_link_enc_regs[inst],
1313 &hpo_dp_le_shift, &hpo_dp_le_mask);
1314
1315 return &hpo_dp_enc31->base;
1316 }
1317
1318
dcn31_hwseq_create(struct dc_context * ctx)1319 static struct dce_hwseq *dcn31_hwseq_create(
1320 struct dc_context *ctx)
1321 {
1322 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1323
1324 if (hws) {
1325 hws->ctx = ctx;
1326 hws->regs = &hwseq_reg;
1327 hws->shifts = &hwseq_shift;
1328 hws->masks = &hwseq_mask;
1329 }
1330 return hws;
1331 }
1332 static const struct resource_create_funcs res_create_funcs = {
1333 .read_dce_straps = read_dce_straps,
1334 .create_audio = dcn31_create_audio,
1335 .create_stream_encoder = dcn316_stream_encoder_create,
1336 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1337 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1338 .create_hwseq = dcn31_hwseq_create,
1339 };
1340
dcn316_resource_destruct(struct dcn316_resource_pool * pool)1341 static void dcn316_resource_destruct(struct dcn316_resource_pool *pool)
1342 {
1343 unsigned int i;
1344
1345 for (i = 0; i < pool->base.stream_enc_count; i++) {
1346 if (pool->base.stream_enc[i] != NULL) {
1347 if (pool->base.stream_enc[i]->vpg != NULL) {
1348 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1349 pool->base.stream_enc[i]->vpg = NULL;
1350 }
1351 if (pool->base.stream_enc[i]->afmt != NULL) {
1352 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1353 pool->base.stream_enc[i]->afmt = NULL;
1354 }
1355 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1356 pool->base.stream_enc[i] = NULL;
1357 }
1358 }
1359
1360 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1361 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1362 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1363 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1364 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1365 }
1366 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1367 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1368 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1369 }
1370 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1371 pool->base.hpo_dp_stream_enc[i] = NULL;
1372 }
1373 }
1374
1375 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1376 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1377 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1378 pool->base.hpo_dp_link_enc[i] = NULL;
1379 }
1380 }
1381
1382 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1383 if (pool->base.dscs[i] != NULL)
1384 dcn20_dsc_destroy(&pool->base.dscs[i]);
1385 }
1386
1387 if (pool->base.mpc != NULL) {
1388 kfree(TO_DCN20_MPC(pool->base.mpc));
1389 pool->base.mpc = NULL;
1390 }
1391 if (pool->base.hubbub != NULL) {
1392 kfree(pool->base.hubbub);
1393 pool->base.hubbub = NULL;
1394 }
1395 for (i = 0; i < pool->base.pipe_count; i++) {
1396 if (pool->base.dpps[i] != NULL)
1397 dcn31_dpp_destroy(&pool->base.dpps[i]);
1398
1399 if (pool->base.ipps[i] != NULL)
1400 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1401
1402 if (pool->base.hubps[i] != NULL) {
1403 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1404 pool->base.hubps[i] = NULL;
1405 }
1406
1407 if (pool->base.irqs != NULL) {
1408 dal_irq_service_destroy(&pool->base.irqs);
1409 }
1410 }
1411
1412 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1413 if (pool->base.engines[i] != NULL)
1414 dce110_engine_destroy(&pool->base.engines[i]);
1415 if (pool->base.hw_i2cs[i] != NULL) {
1416 kfree(pool->base.hw_i2cs[i]);
1417 pool->base.hw_i2cs[i] = NULL;
1418 }
1419 if (pool->base.sw_i2cs[i] != NULL) {
1420 kfree(pool->base.sw_i2cs[i]);
1421 pool->base.sw_i2cs[i] = NULL;
1422 }
1423 }
1424
1425 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1426 if (pool->base.opps[i] != NULL)
1427 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1428 }
1429
1430 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1431 if (pool->base.timing_generators[i] != NULL) {
1432 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1433 pool->base.timing_generators[i] = NULL;
1434 }
1435 }
1436
1437 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1438 if (pool->base.dwbc[i] != NULL) {
1439 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1440 pool->base.dwbc[i] = NULL;
1441 }
1442 if (pool->base.mcif_wb[i] != NULL) {
1443 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1444 pool->base.mcif_wb[i] = NULL;
1445 }
1446 }
1447
1448 for (i = 0; i < pool->base.audio_count; i++) {
1449 if (pool->base.audios[i])
1450 dce_aud_destroy(&pool->base.audios[i]);
1451 }
1452
1453 for (i = 0; i < pool->base.clk_src_count; i++) {
1454 if (pool->base.clock_sources[i] != NULL) {
1455 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1456 pool->base.clock_sources[i] = NULL;
1457 }
1458 }
1459
1460 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1461 if (pool->base.mpc_lut[i] != NULL) {
1462 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1463 pool->base.mpc_lut[i] = NULL;
1464 }
1465 if (pool->base.mpc_shaper[i] != NULL) {
1466 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1467 pool->base.mpc_shaper[i] = NULL;
1468 }
1469 }
1470
1471 if (pool->base.dp_clock_source != NULL) {
1472 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1473 pool->base.dp_clock_source = NULL;
1474 }
1475
1476 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1477 if (pool->base.multiple_abms[i] != NULL)
1478 dce_abm_destroy(&pool->base.multiple_abms[i]);
1479 }
1480
1481 if (pool->base.psr != NULL)
1482 dmub_psr_destroy(&pool->base.psr);
1483
1484 if (pool->base.dccg != NULL)
1485 dcn_dccg_destroy(&pool->base.dccg);
1486 }
1487
dcn31_hubp_create(struct dc_context * ctx,uint32_t inst)1488 static struct hubp *dcn31_hubp_create(
1489 struct dc_context *ctx,
1490 uint32_t inst)
1491 {
1492 struct dcn20_hubp *hubp2 =
1493 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1494
1495 if (!hubp2)
1496 return NULL;
1497
1498 if (hubp31_construct(hubp2, ctx, inst,
1499 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1500 return &hubp2->base;
1501
1502 BREAK_TO_DEBUGGER();
1503 kfree(hubp2);
1504 return NULL;
1505 }
1506
dcn31_dwbc_create(struct dc_context * ctx,struct resource_pool * pool)1507 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1508 {
1509 int i;
1510 uint32_t pipe_count = pool->res_cap->num_dwb;
1511
1512 for (i = 0; i < pipe_count; i++) {
1513 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1514 GFP_KERNEL);
1515
1516 if (!dwbc30) {
1517 dm_error("DC: failed to create dwbc30!\n");
1518 return false;
1519 }
1520
1521 dcn30_dwbc_construct(dwbc30, ctx,
1522 &dwbc30_regs[i],
1523 &dwbc30_shift,
1524 &dwbc30_mask,
1525 i);
1526
1527 pool->dwbc[i] = &dwbc30->base;
1528 }
1529 return true;
1530 }
1531
dcn31_mmhubbub_create(struct dc_context * ctx,struct resource_pool * pool)1532 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1533 {
1534 int i;
1535 uint32_t pipe_count = pool->res_cap->num_dwb;
1536
1537 for (i = 0; i < pipe_count; i++) {
1538 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1539 GFP_KERNEL);
1540
1541 if (!mcif_wb30) {
1542 dm_error("DC: failed to create mcif_wb30!\n");
1543 return false;
1544 }
1545
1546 dcn30_mmhubbub_construct(mcif_wb30, ctx,
1547 &mcif_wb30_regs[i],
1548 &mcif_wb30_shift,
1549 &mcif_wb30_mask,
1550 i);
1551
1552 pool->mcif_wb[i] = &mcif_wb30->base;
1553 }
1554 return true;
1555 }
1556
dcn31_dsc_create(struct dc_context * ctx,uint32_t inst)1557 static struct display_stream_compressor *dcn31_dsc_create(
1558 struct dc_context *ctx, uint32_t inst)
1559 {
1560 struct dcn20_dsc *dsc =
1561 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1562
1563 if (!dsc) {
1564 BREAK_TO_DEBUGGER();
1565 return NULL;
1566 }
1567
1568 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1569 return &dsc->base;
1570 }
1571
dcn316_destroy_resource_pool(struct resource_pool ** pool)1572 static void dcn316_destroy_resource_pool(struct resource_pool **pool)
1573 {
1574 struct dcn316_resource_pool *dcn31_pool = TO_DCN316_RES_POOL(*pool);
1575
1576 dcn316_resource_destruct(dcn31_pool);
1577 kfree(dcn31_pool);
1578 *pool = NULL;
1579 }
1580
dcn31_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)1581 static struct clock_source *dcn31_clock_source_create(
1582 struct dc_context *ctx,
1583 struct dc_bios *bios,
1584 enum clock_source_id id,
1585 const struct dce110_clk_src_regs *regs,
1586 bool dp_clk_src)
1587 {
1588 struct dce110_clk_src *clk_src =
1589 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1590
1591 if (!clk_src)
1592 return NULL;
1593
1594 if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
1595 regs, &cs_shift, &cs_mask)) {
1596 clk_src->base.dp_clk_src = dp_clk_src;
1597 return &clk_src->base;
1598 }
1599
1600 kfree(clk_src);
1601
1602 BREAK_TO_DEBUGGER();
1603 return NULL;
1604 }
1605
is_dual_plane(enum surface_pixel_format format)1606 static bool is_dual_plane(enum surface_pixel_format format)
1607 {
1608 return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA;
1609 }
1610
dcn316_populate_dml_pipes_from_context(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,bool fast_validate)1611 static int dcn316_populate_dml_pipes_from_context(
1612 struct dc *dc, struct dc_state *context,
1613 display_e2e_pipe_params_st *pipes,
1614 bool fast_validate)
1615 {
1616 int i, pipe_cnt;
1617 struct resource_context *res_ctx = &context->res_ctx;
1618 struct pipe_ctx *pipe = 0;
1619 const int max_usable_det = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - DCN3_16_MIN_COMPBUF_SIZE_KB;
1620
1621 DC_FP_START();
1622 dcn31x_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1623 DC_FP_END();
1624
1625 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1626 struct dc_crtc_timing *timing;
1627
1628 if (!res_ctx->pipe_ctx[i].stream)
1629 continue;
1630 pipe = &res_ctx->pipe_ctx[i];
1631 timing = &pipe->stream->timing;
1632
1633 /*
1634 * Immediate flip can be set dynamically after enabling the plane.
1635 * We need to require support for immediate flip or underflow can be
1636 * intermittently experienced depending on peak b/w requirements.
1637 */
1638 pipes[pipe_cnt].pipe.src.immediate_flip = true;
1639
1640 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
1641 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
1642 pipes[pipe_cnt].pipe.src.dcc_rate = 3;
1643 pipes[pipe_cnt].dout.dsc_input_bpc = 0;
1644 DC_FP_START();
1645 dcn31_zero_pipe_dcc_fraction(pipes, pipe_cnt);
1646 DC_FP_END();
1647
1648 if (pipes[pipe_cnt].dout.dsc_enable) {
1649 switch (timing->display_color_depth) {
1650 case COLOR_DEPTH_888:
1651 pipes[pipe_cnt].dout.dsc_input_bpc = 8;
1652 break;
1653 case COLOR_DEPTH_101010:
1654 pipes[pipe_cnt].dout.dsc_input_bpc = 10;
1655 break;
1656 case COLOR_DEPTH_121212:
1657 pipes[pipe_cnt].dout.dsc_input_bpc = 12;
1658 break;
1659 default:
1660 ASSERT(0);
1661 break;
1662 }
1663 }
1664
1665 pipe_cnt++;
1666 }
1667
1668 if (pipe_cnt)
1669 context->bw_ctx.dml.ip.det_buffer_size_kbytes =
1670 (max_usable_det / DCN3_16_CRB_SEGMENT_SIZE_KB / pipe_cnt) * DCN3_16_CRB_SEGMENT_SIZE_KB;
1671 if (context->bw_ctx.dml.ip.det_buffer_size_kbytes > DCN3_16_MAX_DET_SIZE)
1672 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_16_MAX_DET_SIZE;
1673 ASSERT(context->bw_ctx.dml.ip.det_buffer_size_kbytes >= DCN3_16_DEFAULT_DET_SIZE);
1674 dc->config.enable_4to1MPC = false;
1675 if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {
1676 if (is_dual_plane(pipe->plane_state->format)
1677 && pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) {
1678 dc->config.enable_4to1MPC = true;
1679 context->bw_ctx.dml.ip.det_buffer_size_kbytes =
1680 (max_usable_det / DCN3_16_CRB_SEGMENT_SIZE_KB / 4) * DCN3_16_CRB_SEGMENT_SIZE_KB;
1681 } else if (!is_dual_plane(pipe->plane_state->format)) {
1682 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;
1683 pipes[0].pipe.src.unbounded_req_mode = true;
1684 }
1685 }
1686
1687 return pipe_cnt;
1688 }
1689
dcn316_get_panel_config_defaults(struct dc_panel_config * panel_config)1690 static void dcn316_get_panel_config_defaults(struct dc_panel_config *panel_config)
1691 {
1692 *panel_config = panel_config_defaults;
1693 }
1694
1695 static struct dc_cap_funcs cap_funcs = {
1696 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1697 };
1698
1699 static struct resource_funcs dcn316_res_pool_funcs = {
1700 .destroy = dcn316_destroy_resource_pool,
1701 .link_enc_create = dcn31_link_encoder_create,
1702 .link_enc_create_minimal = dcn31_link_enc_create_minimal,
1703 .link_encs_assign = link_enc_cfg_link_encs_assign,
1704 .link_enc_unassign = link_enc_cfg_link_enc_unassign,
1705 .panel_cntl_create = dcn31_panel_cntl_create,
1706 .validate_bandwidth = dcn31_validate_bandwidth,
1707 .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg,
1708 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
1709 .populate_dml_pipes = dcn316_populate_dml_pipes_from_context,
1710 .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
1711 .release_pipe = dcn20_release_pipe,
1712 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1713 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1714 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1715 .populate_dml_writeback_from_context = dcn31_populate_dml_writeback_from_context,
1716 .set_mcif_arb_params = dcn31_set_mcif_arb_params,
1717 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1718 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1719 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1720 .update_bw_bounding_box = dcn316_update_bw_bounding_box,
1721 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1722 .get_panel_config_defaults = dcn316_get_panel_config_defaults,
1723 };
1724
dcn316_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn316_resource_pool * pool)1725 static bool dcn316_resource_construct(
1726 uint8_t num_virtual_links,
1727 struct dc *dc,
1728 struct dcn316_resource_pool *pool)
1729 {
1730 int i;
1731 struct dc_context *ctx = dc->ctx;
1732 struct irq_service_init_data init_data;
1733
1734 ctx->dc_bios->regs = &bios_regs;
1735
1736 pool->base.res_cap = &res_cap_dcn31;
1737
1738 pool->base.funcs = &dcn316_res_pool_funcs;
1739
1740 /*************************************************
1741 * Resource + asic cap harcoding *
1742 *************************************************/
1743 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1744 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1745 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1746 dc->caps.max_downscale_ratio = 600;
1747 dc->caps.i2c_speed_in_khz = 100;
1748 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.5 w/a applied by default*/
1749 dc->caps.max_cursor_size = 256;
1750 dc->caps.min_horizontal_blanking_period = 80;
1751 dc->caps.dmdata_alloc_size = 2048;
1752 dc->caps.max_slave_planes = 2;
1753 dc->caps.max_slave_yuv_planes = 2;
1754 dc->caps.max_slave_rgb_planes = 2;
1755 dc->caps.post_blend_color_processing = true;
1756 dc->caps.force_dp_tps4_for_cp2520 = true;
1757 if (dc->config.forceHBR2CP2520)
1758 dc->caps.force_dp_tps4_for_cp2520 = false;
1759 dc->caps.dp_hpo = true;
1760 dc->caps.dp_hdmi21_pcon_support = true;
1761 dc->caps.edp_dsc_support = true;
1762 dc->caps.extended_aux_timeout_support = true;
1763 dc->caps.dmcub_support = true;
1764 dc->caps.is_apu = true;
1765
1766 /* Color pipeline capabilities */
1767 dc->caps.color.dpp.dcn_arch = 1;
1768 dc->caps.color.dpp.input_lut_shared = 0;
1769 dc->caps.color.dpp.icsc = 1;
1770 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1771 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1772 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1773 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1774 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1775 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1776 dc->caps.color.dpp.post_csc = 1;
1777 dc->caps.color.dpp.gamma_corr = 1;
1778 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1779
1780 dc->caps.color.dpp.hw_3d_lut = 1;
1781 dc->caps.color.dpp.ogam_ram = 1;
1782 // no OGAM ROM on DCN301
1783 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1784 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1785 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1786 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1787 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1788 dc->caps.color.dpp.ocsc = 0;
1789
1790 dc->caps.color.mpc.gamut_remap = 1;
1791 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
1792 dc->caps.color.mpc.ogam_ram = 1;
1793 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1794 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1795 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1796 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1797 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1798 dc->caps.color.mpc.ocsc = 1;
1799
1800 /* read VBIOS LTTPR caps */
1801 {
1802 if (ctx->dc_bios->funcs->get_lttpr_caps) {
1803 enum bp_result bp_query_result;
1804 uint8_t is_vbios_lttpr_enable = 0;
1805
1806 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1807 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1808 }
1809
1810 /* interop bit is implicit */
1811 {
1812 dc->caps.vbios_lttpr_aware = true;
1813 }
1814 }
1815
1816 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1817 dc->debug = debug_defaults_drv;
1818
1819 // Init the vm_helper
1820 if (dc->vm_helper)
1821 vm_helper_init(dc->vm_helper, 16);
1822
1823 /*************************************************
1824 * Create resources *
1825 *************************************************/
1826
1827 /* Clock Sources for Pixel Clock*/
1828 pool->base.clock_sources[DCN31_CLK_SRC_PLL0] =
1829 dcn31_clock_source_create(ctx, ctx->dc_bios,
1830 CLOCK_SOURCE_COMBO_PHY_PLL0,
1831 &clk_src_regs[0], false);
1832 pool->base.clock_sources[DCN31_CLK_SRC_PLL1] =
1833 dcn31_clock_source_create(ctx, ctx->dc_bios,
1834 CLOCK_SOURCE_COMBO_PHY_PLL1,
1835 &clk_src_regs[1], false);
1836 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
1837 dcn31_clock_source_create(ctx, ctx->dc_bios,
1838 CLOCK_SOURCE_COMBO_PHY_PLL2,
1839 &clk_src_regs[2], false);
1840 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
1841 dcn31_clock_source_create(ctx, ctx->dc_bios,
1842 CLOCK_SOURCE_COMBO_PHY_PLL3,
1843 &clk_src_regs[3], false);
1844 pool->base.clock_sources[DCN31_CLK_SRC_PLL4] =
1845 dcn31_clock_source_create(ctx, ctx->dc_bios,
1846 CLOCK_SOURCE_COMBO_PHY_PLL4,
1847 &clk_src_regs[4], false);
1848
1849 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;
1850
1851 /* todo: not reuse phy_pll registers */
1852 pool->base.dp_clock_source =
1853 dcn31_clock_source_create(ctx, ctx->dc_bios,
1854 CLOCK_SOURCE_ID_DP_DTO,
1855 &clk_src_regs[0], true);
1856
1857 for (i = 0; i < pool->base.clk_src_count; i++) {
1858 if (pool->base.clock_sources[i] == NULL) {
1859 dm_error("DC: failed to create clock sources!\n");
1860 BREAK_TO_DEBUGGER();
1861 goto create_fail;
1862 }
1863 }
1864
1865 /* TODO: DCCG */
1866 pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1867 if (pool->base.dccg == NULL) {
1868 dm_error("DC: failed to create dccg!\n");
1869 BREAK_TO_DEBUGGER();
1870 goto create_fail;
1871 }
1872
1873 /* TODO: IRQ */
1874 init_data.ctx = dc->ctx;
1875 pool->base.irqs = dal_irq_service_dcn31_create(&init_data);
1876 if (!pool->base.irqs)
1877 goto create_fail;
1878
1879 /* HUBBUB */
1880 pool->base.hubbub = dcn31_hubbub_create(ctx);
1881 if (pool->base.hubbub == NULL) {
1882 BREAK_TO_DEBUGGER();
1883 dm_error("DC: failed to create hubbub!\n");
1884 goto create_fail;
1885 }
1886
1887 /* HUBPs, DPPs, OPPs and TGs */
1888 for (i = 0; i < pool->base.pipe_count; i++) {
1889 pool->base.hubps[i] = dcn31_hubp_create(ctx, i);
1890 if (pool->base.hubps[i] == NULL) {
1891 BREAK_TO_DEBUGGER();
1892 dm_error(
1893 "DC: failed to create hubps!\n");
1894 goto create_fail;
1895 }
1896
1897 pool->base.dpps[i] = dcn31_dpp_create(ctx, i);
1898 if (pool->base.dpps[i] == NULL) {
1899 BREAK_TO_DEBUGGER();
1900 dm_error(
1901 "DC: failed to create dpps!\n");
1902 goto create_fail;
1903 }
1904 }
1905
1906 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1907 pool->base.opps[i] = dcn31_opp_create(ctx, i);
1908 if (pool->base.opps[i] == NULL) {
1909 BREAK_TO_DEBUGGER();
1910 dm_error(
1911 "DC: failed to create output pixel processor!\n");
1912 goto create_fail;
1913 }
1914 }
1915
1916 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1917 pool->base.timing_generators[i] = dcn31_timing_generator_create(
1918 ctx, i);
1919 if (pool->base.timing_generators[i] == NULL) {
1920 BREAK_TO_DEBUGGER();
1921 dm_error("DC: failed to create tg!\n");
1922 goto create_fail;
1923 }
1924 }
1925 pool->base.timing_generator_count = i;
1926
1927 /* PSR */
1928 pool->base.psr = dmub_psr_create(ctx);
1929 if (pool->base.psr == NULL) {
1930 dm_error("DC: failed to create psr obj!\n");
1931 BREAK_TO_DEBUGGER();
1932 goto create_fail;
1933 }
1934
1935 /* ABM */
1936 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1937 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
1938 &abm_regs[i],
1939 &abm_shift,
1940 &abm_mask);
1941 if (pool->base.multiple_abms[i] == NULL) {
1942 dm_error("DC: failed to create abm for pipe %d!\n", i);
1943 BREAK_TO_DEBUGGER();
1944 goto create_fail;
1945 }
1946 }
1947
1948 /* MPC and DSC */
1949 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
1950 if (pool->base.mpc == NULL) {
1951 BREAK_TO_DEBUGGER();
1952 dm_error("DC: failed to create mpc!\n");
1953 goto create_fail;
1954 }
1955
1956 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1957 pool->base.dscs[i] = dcn31_dsc_create(ctx, i);
1958 if (pool->base.dscs[i] == NULL) {
1959 BREAK_TO_DEBUGGER();
1960 dm_error("DC: failed to create display stream compressor %d!\n", i);
1961 goto create_fail;
1962 }
1963 }
1964
1965 /* DWB and MMHUBBUB */
1966 if (!dcn31_dwbc_create(ctx, &pool->base)) {
1967 BREAK_TO_DEBUGGER();
1968 dm_error("DC: failed to create dwbc!\n");
1969 goto create_fail;
1970 }
1971
1972 if (!dcn31_mmhubbub_create(ctx, &pool->base)) {
1973 BREAK_TO_DEBUGGER();
1974 dm_error("DC: failed to create mcif_wb!\n");
1975 goto create_fail;
1976 }
1977
1978 /* AUX and I2C */
1979 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1980 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);
1981 if (pool->base.engines[i] == NULL) {
1982 BREAK_TO_DEBUGGER();
1983 dm_error(
1984 "DC:failed to create aux engine!!\n");
1985 goto create_fail;
1986 }
1987 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);
1988 if (pool->base.hw_i2cs[i] == NULL) {
1989 BREAK_TO_DEBUGGER();
1990 dm_error(
1991 "DC:failed to create hw i2c!!\n");
1992 goto create_fail;
1993 }
1994 pool->base.sw_i2cs[i] = NULL;
1995 }
1996
1997 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
1998 if (!resource_construct(num_virtual_links, dc, &pool->base,
1999 &res_create_funcs))
2000 goto create_fail;
2001
2002 /* HW Sequencer and Plane caps */
2003 dcn31_hw_sequencer_construct(dc);
2004
2005 dc->caps.max_planes = pool->base.pipe_count;
2006
2007 for (i = 0; i < dc->caps.max_planes; ++i)
2008 dc->caps.planes[i] = plane_cap;
2009
2010 dc->cap_funcs = cap_funcs;
2011
2012 dc->dcn_ip->max_num_dpp = dcn3_16_ip.max_num_dpp;
2013
2014 return true;
2015
2016 create_fail:
2017
2018 dcn316_resource_destruct(pool);
2019
2020 return false;
2021 }
2022
dcn316_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)2023 struct resource_pool *dcn316_create_resource_pool(
2024 const struct dc_init_data *init_data,
2025 struct dc *dc)
2026 {
2027 struct dcn316_resource_pool *pool =
2028 kzalloc(sizeof(struct dcn316_resource_pool), GFP_KERNEL);
2029
2030 if (!pool)
2031 return NULL;
2032
2033 if (dcn316_resource_construct(init_data->num_virtual_links, dc, pool))
2034 return &pool->base;
2035
2036 BREAK_TO_DEBUGGER();
2037 kfree(pool);
2038 return NULL;
2039 }
2040