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/linux/Documentation/devicetree/bindings/phy/
H A Dbrcm,sr-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/brcm,sr-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom Stingray PCIe PHY
10 - Ray Jui <ray.jui@broadcom.com>
14 PHY index goes from 0 to 7.
16 For the internal PAXC based root complex, PHY index is always 8.
20 const: brcm,sr-pcie-phy
25 '#phy-cells':
[all …]
/linux/drivers/phy/broadcom/
H A Dphy-bcm-sr-pcie.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Broadcom
12 #include <linux/phy/phy.h>
18 #define SR_PAXC_PHY_IDX (SR_NR_PCIE_PHYS - 1)
40 * struct sr_pcie_phy - Stingray PCIe PHY
42 * @core: pointer to the Stingray PCIe PHY core control
43 * @index: PHY index
44 * @phy: pointer to the kernel PHY device
49 struct phy *phy; member
53 * struct sr_pcie_phy_core - Stingray PCIe PHY core control
[all …]
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PHY_BCM63XX_USBH) += phy-bcm63xx-usbh.o
3 obj-$(CONFIG_PHY_CYGNUS_PCIE) += phy-bcm-cygnus-pcie.o
4 obj-$(CONFIG_BCM_KONA_USB2_PHY) += phy-bcm-kona-usb2.o
5 obj-$(CONFIG_PHY_BCM_NS_USB2) += phy-bcm-ns-usb2.o
6 obj-$(CONFIG_PHY_BCM_NS_USB3) += phy-bcm-ns-usb3.o
7 obj-$(CONFIG_PHY_NS2_PCIE) += phy-bcm-ns2-pcie.o
8 obj-$(CONFIG_PHY_NS2_USB_DRD) += phy-bcm-ns2-usbdrd.o
9 obj-$(CONFIG_PHY_BRCM_SATA) += phy-brcm-sata.o
10 obj-$(CONFIG_PHY_BRCM_USB) += phy-brcm-usb-dvr.o
[all …]
/linux/arch/arm64/boot/dts/broadcom/stingray/
H A Dstingray-pcie.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
6 pcie8: pcie@60400000 {
7 compatible = "brcm,iproc-pcie-paxc-v2";
9 linux,pci-domain = <8>;
11 bus-range = <0x0 0x1>;
13 #address-cells = <3>;
14 #size-cells = <2>;
18 dma-coherent;
20 msi-map = <0x100 &gic_its 0x2000 0x1>, /* PF0 */
21 <0x108 &gic_its 0x2040 0x8>, /* PF0-VF0-7 */
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/linux/drivers/pci/controller/
H A Dpcie-brcmstb.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2009 - 2019 Broadcom */
15 #include <linux/irqchip/irq-msi-lib.h>
27 #include <linux/pci-ecam.h>
38 /* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
41 /* Broadcom STB PCIe Register Offsets */
166 /* PCIe parameters */
171 #define BRCM_INT_PCI_MSI_MASK GENMASK(BRCM_INT_PCI_MSI_NR - 1, 0)
173 32 - BRCM_INT_PCI_MSI_LEGACY_NR)
201 #define IDX_ADDR(pcie) ((pcie)->cfg->offsets[EXT_CFG_INDEX]) argument
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dbrcm,iproc-clocks.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/brcm,iproc-clocks.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ray Jui <rjui@broadcom.com>
11 - Scott Branden <sbranden@broadcom.com>
25 - brcm,bcm63138-armpll
26 - brcm,cygnus-armpll
27 - brcm,cygnus-genpll
28 - brcm,cygnus-lcpll0
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/linux/arch/arm64/boot/dts/ti/
H A Dk3-am642-hummingboard-t.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2023 Josua Mayer <josua@solid-run.com>
5 * DTS for SolidRun AM642 HummingBoard-T,
10 /dts-v1/;
12 #include <dt-bindings/leds/common.h>
13 #include <dt-bindings/phy/phy.h>
15 #include "k3-am642.dtsi"
16 #include "k3-am642-sr-som.dtsi"
19 model = "SolidRun AM642 HummingBoard-T";
20 compatible = "solidrun,am642-hummingboard-t", "solidrun,am642-sr-som", "ti,am642";
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/linux/arch/arm64/boot/dts/marvell/
H A Dcn9130-cf-pro.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2024 Josua Mayer <josua@solid-run.com>
9 /dts-v1/;
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/leds/common.h>
15 #include "cn9130-sr-som.dtsi"
16 #include "cn9130-cf.dtsi"
20 compatible = "solidrun,cn9130-clearfog-pro",
21 "solidrun,cn9130-sr-som", "marvell,cn9130";
23 gpio-keys {
[all …]
/linux/arch/powerpc/boot/dts/
H A Dglacier.dts4 * Copyright 2008-2010 DENX Software Engineering, Stefan Roese <sr@denx.de>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
30 #address-cells = <1>;
31 #size-cells = <0>;
37 clock-frequency = <0>; /* Filled in by U-Boot */
38 timebase-frequency = <0>; /* Filled in by U-Boot */
39 i-cache-line-size = <32>;
[all …]
H A Dcanyonlands.dts4 * Copyright 2008-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
28 #address-cells = <1>;
29 #size-cells = <0>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
37 i-cache-line-size = <32>;
[all …]
H A Dicon.dts4 * Copyright 2010 DENX Software Engineering, Stefan Roese <sr@denx.de>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <2>;
18 dcr-parent = <&{/cpus/cpu@0}>;
28 #address-cells = <1>;
29 #size-cells = <0>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
37 i-cache-line-size = <32>;
[all …]
/linux/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_type_e610.h1 /* SPDX-License-Identifier: GPL-2.0 */
76 * using ixgbe_read_netlist_module, we need to account for the 2-word TLV
160 /* PHY commands */
235 /* Get PHY capabilities (indirect 0x0600) */
240 /* 18.0 - Report qualified modules */
242 /* 18.1 - 18.3 : Report mode
243 * 000b - Report topology capabilities, without media
244 * 001b - Report topology capabilities, with media
245 * 010b - Report Active configuration
246 * 011b - Report PHY Type and FEC mode capabilities
[all …]
H A Dixgbe_main.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2024 Intel Corporation. */
66 "Copyright (c) 1999-2016 Intel Corporation.";
82 /* ixgbe_pci_tbl - PCI Device ID Table
162 …"Maximum number of virtual functions to allocate per physical function - default is zero and maxim…
168 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
171 static int debug = -1;
193 return dev && (dev->netdev_ops == &ixgbe_netdev_ops); in netif_is_ixgbe()
202 parent_bus = adapter->pdev->bus->parent; in ixgbe_read_pci_cfg_word_parent()
204 return -1; in ixgbe_read_pci_cfg_word_parent()
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3399-gru-chromebook.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Google Gru-Chromebook shared properties
8 #include "rk3399-gru.dtsi"
11 pp900_ap: regulator-pp900-ap {
12 compatible = "regulator-fixed";
13 regulator-name = "pp900_ap";
16 regulator-always-on;
17 regulator-boot-on;
18 regulator-min-microvolt = <900000>;
19 regulator-max-microvolt = <900000>;
[all …]
/linux/Documentation/networking/device_drivers/ethernet/marvell/
H A Docteontx2.rst1 .. SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
12 - `Overview`_
13 - `Drivers`_
14 - `Basic packet flow`_
15 - `Devlink health reporters`_
16 - `Quality of service`_
17 - `RVU representors`_
24 PCI-compatible physical and virtual functions. Each functional block
26 RVU supports multiple PCIe SRIOV physical functions (PFs) and virtual
32 - Network pool or buffer allocator (NPA)
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/linux/Documentation/networking/device_drivers/ethernet/intel/
H A Dice.rst1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 2018-2021 Intel Corporation.
13 - Overview
14 - Identifying Your Adapter
15 - Important Notes
16 - Additional Features & Configurations
17 - Performance Optimization
28 This driver supports XDP (Express Data Path) and AF_XDP zero-copy. Note that
43 -------------------------------------------
45 tolerate a limited amount of system latency during PCIe and DMA transactions.
[all …]
/linux/drivers/net/ethernet/
H A Djme.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
7 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
9 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
34 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args)
39 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args); \
80 u8 sr; member
377 #define NET_STAT(priv) (priv->dev->stats)
387 #define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi);
389 if (!napi_disable_pending(&priv->napi)) \
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/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
[all …]
/linux/drivers/net/ethernet/intel/igb/
H A Digb_main.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
56 "Copyright (c) 2007-2014 Intel Corporation.";
208 static int debug = -1;
253 /* igb_regdump - register printout routine */
260 switch (reginfo->ofs) { in igb_regdump()
310 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); in igb_regdump()
314 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); in igb_regdump()
315 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], in igb_regdump()
319 /* igb_dump - Print registers, Tx-rings and Rx-rings */
[all …]
/linux/drivers/net/ethernet/chelsio/cxgb4vf/
H A Dcxgb4vf_main.c2 * This file is part of the Chelsio T4 PCI-E SR-IOV Virtual Function Ethernet
5 * Copyright (c) 2009-2010 Chelsio Communications, Inc. All rights reserved.
17 * - Redistributions of source code must retain the above
21 * - Redistributions in binary form must reproduce the above
42 #include <linux/dma-mapping.h>
74 * order MSI-X then MSI. This parameter determines which of these schemes the
77 * msi = 2: choose from among MSI-X and MSI
82 * the PCI-E SR-IOV standard).
91 MODULE_PARM_DESC(msi, "whether to use MSI-X or MSI");
112 * list entries are 64-bit PCI DMA addresses. And since the state of
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/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_reg.h3 * Copyright (c) 2007-2013 Broadcom Corporation
13 * R - Read only
14 * RC - Clear on read
15 * RW - Read/Write
16 * ST - Statistics register (clear on read)
17 * W - Write only
18 * WB - Wide bus register - the size is over 32 bits and it should be
20 * WR - Write Clear (write 1 to clear the bit)
32 /* [RW 1] Initiate the ATC array - reset all the valid bits */
56 * BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. Warning -
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/linux/drivers/net/ethernet/chelsio/cxgb3/
H A Dcxgb3_main.c2 * Copyright (c) 2003-2008 Chelsio, Inc. All rights reserved.
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
38 #include <linux/dma-mapping.h>
77 #define PORT_MASK ((1 << MAX_NPORTS) - 1)
99 CH_DEVICE(0x35, 6), /* T3C20-derived T3C10 */
100 CH_DEVICE(0x36, 3), /* S320E-CR */
101 CH_DEVICE(0x37, 7), /* N320E-G2 */
117 * order MSI-X, MSI, legacy pin interrupts. This parameter determines which
127 MODULE_PARM_DESC(msi, "whether to use MSI or MSI-X");
[all …]
/linux/drivers/net/ethernet/chelsio/cxgb4/
H A Dcxgb4_main.c4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
109 /* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is
126 #define FW4_CFNAME "cxgb4/t4-config.txt"
127 #define FW5_CFNAME "cxgb4/t5-config.txt"
128 #define FW6_CFNAME "cxgb4/t6-config.txt"
144 * order MSI-X, MSI, legacy INTx interrupts. This parameter determines which
154 MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)");
158 * offset by 2 bytes in order to have the IP headers line up on 4-byte
[all …]
/linux/drivers/net/ethernet/sfc/
H A Dmcdi_pcol.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
29 * we shouldn't touch PCIe config. */
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
38 /* The rest of these are firmware-defined */
46 /* Values to be written to the per-port status dword in shared
71 * | | \--- Response
72 * | \------- Error
[all …]
/linux/drivers/net/ethernet/sfc/siena/
H A Dmcdi_pcol.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
29 * we shouldn't touch PCIe config. */
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
38 /* The rest of these are firmware-defined */
46 /* Values to be written to the per-port status dword in shared
71 * | | \--- Response
72 * | \------- Error
[all …]

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