Lines Matching +full:sr +full:- +full:pcie +full:- +full:phy

1 /* SPDX-License-Identifier: GPL-2.0-only */
3  * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
7  * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
9  * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
34 	printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args)
39 		printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args); \
80 	u8	sr;  member
377 #define NET_STAT(priv) (priv->dev->stats)
387 #define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi);
389 	if (!napi_disable_pending(&priv->napi)) \
390 		napi_disable(&priv->napi);
392 	napi_schedule_prep(&priv->napi)
394 	__napi_schedule(&priv->napi);
492 	JME_TXTRHD	= JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
512 	JME_PHY_PWR	= JME_PHY | 0x24, /* New PHY Power Ctrl Register */
513 	JME_PHY_CS	= JME_PHY | 0x28, /* PHY Ctrl and Status Register */
514 	JME_PHY_LINK	= JME_PHY | 0x30, /* PHY Link Status Register */
520 	JME_GPREG0	= JME_MISC | 0x08, /* General purpose REG-0 */
521 	JME_GPREG1	= JME_MISC | 0x0C, /* General purpose REG-1 */
524 	JME_IENS	= JME_MISC | 0x28, /* Intr Enable - Setting Port */
525 	JME_IENC	= JME_MISC | 0x2C, /* Interrupt Enable - Clear Port */
747 /*	Extern PHY common register 2	*/
880  * New PHY Power Control Register
888 				       * (an internal free-running clock)
895  * Giga PHY Status Registers
963  * General Purpose REG-0
1003  * General Purpose REG-1
1189 	printk(KERN_DEBUG "%s: %-20s %08x@%s\n", jme->dev->name,  in reg_dbg()
1202 	return readl(jme->regs + reg);  in jread32()
1208 	writel(val, jme->regs + reg);  in jwrite32()
1209 	reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);  in jwrite32()
1218 	writel(val, jme->regs + reg);  in jwrite32f()
1219 	readl(jme->regs + reg);  in jwrite32f()
1220 	reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);  in jwrite32f()
1224  * PHY Regs