Home
last modified time | relevance | path

Searched +full:spi +full:- +full:present +full:- +full:mask (Results 1 – 25 of 55) sorted by relevance

123

/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dpinctrl-mcp23s08.txt2 8-/16-bit I/O expander with serial interface (I2C/SPI)
5 - compatible : Should be
6 - "mcp,mcp23s08" (DEPRECATED) for 8 GPIO SPI version
7 - "mcp,mcp23s17" (DEPRECATED) for 16 GPIO SPI version
8 - "mcp,mcp23008" (DEPRECATED) for 8 GPIO I2C version or
9 - "mcp,mcp23017" (DEPRECATED) for 16 GPIO I2C version of the chip
11 - "microchip,mcp23s08" for 8 GPIO SPI version
12 - "microchip,mcp23s17" for 16 GPIO SPI version
13 - "microchip,mcp23s18" for 16 GPIO SPI version
14 - "microchip,mcp23008" for 8 GPIO I2C version or
[all …]
H A Dmicrochip,mcp23s08.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip I/O expander with serial interface (I2C/SPI)
10 - Himanshu Bhavani <himanshu.bhavani@siliconsignals.io>
14 chips.These chips provide 8 or 16 GPIO pins with either I2C or SPI interface.
17 - $ref: /schemas/spi/spi-peripheral-props.yaml#
22 - microchip,mcp23s08
23 - microchip,mcp23s17
24 - microchip,mcp23s18
[all …]
/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Drenesas,idt821034.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Herve Codina <herve.codina@bootlin.com>
16 The time-slots used by the codec must be set and so, the properties
17 'dai-tdm-slot-num', 'dai-tdm-slot-width', 'dai-tdm-slot-tx-mask' and
18 'dai-tdm-slot-rx-mask' must be present in the ALSA sound card node for
19 sub-nodes that involve the codec. The codec uses one 8bit time-slot per
21 'dai-tdm-tdm-slot-with' must be set to 8.
26 - $ref: /schemas/spi/spi-peripheral-props.yaml#
[all …]
H A Dinfineon,peb2466.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Herve Codina <herve.codina@bootlin.com>
13 The Infineon PEB2466 codec is a programmable DSP-based four channels codec
16 The time-slots used by the codec must be set and so, the properties
17 'dai-tdm-slot-num', 'dai-tdm-slot-width', 'dai-tdm-slot-tx-mask' and
18 'dai-tdm-slot-rx-mask' must be present in the sound card node for sub-nodes
19 that involve the codec. The codec uses one 8bit time-slot per channel.
20 'dai-tdm-tdm-slot-with' must be set to 8.
[all …]
/freebsd/sys/contrib/device-tree/Bindings/dma/
H A Dste-dma40.txt4 - compatible: "stericsson,dma40"
5 - reg: Address range of the DMAC registers
6 - reg-names: Names of the above areas to use during resource look-up
7 - interrupt: Should contain the DMAC interrupt number
8 - #dma-cells: must be <3>
9 - memcpy-channels: Channels to be used for memcpy
12 - dma-channels: Number of channels supported by hardware - if not present
14 - disabled-channels: Channels which can not be used
18 dma: dma-controller@801c0000 {
19 compatible = "stericsson,db8500-dma40", "stericsson,dma40";
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDKernelCodeT.h1 //===-- AMDGPUKernelCodeT.h - Print AMDGPU assembly code ---------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
16 //---------------------------------------------------------------------------//
18 //---------------------------------------------------------------------------//
42 // Sets val bits for specified mask in specified dst packed instance.
43 #define AMD_HSA_BITS_SET(dst, mask, val) \ argument
44 dst &= (~(1 << mask ## _SHIFT) & ~mask); \
45 dst |= (((val) << mask ## _SHIFT) & mask)
[all …]
/freebsd/sys/dev/safe/
H A Dsafereg.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
33 * Register definitions for SafeNet SafeXcel-1141 crypto device.
68 #define SAFE_HM_STAT 0x00a4 /* Host Masked Status (read-only) */
69 #define SAFE_HI_CLR 0x00a4 /* Host Clear Interrupt (write-only) */
70 #define SAFE_HI_MASK 0x00a8 /* Host Mask Control */
125 #define SAFE_PE_CSR_XECODE_BADSPI 6 /* IPsec SPI mismatch */
129 #define SAFE_PE_CSR_PAD_16 0x08000000 /* pad to 16-byte boundary */
130 #define SAFE_PE_CSR_PAD_32 0x10000000 /* pad to 32-byte boundary */
131 #define SAFE_PE_CSR_PAD_64 0x20000000 /* pad to 64-byte boundary */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Darm,gic.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
14 interrupts (PPI), shared processor interrupts (SPI) and software
22 - $ref: /schemas/interrupt-controller.yaml#
27 - items:
28 - enum:
29 - arm,arm11mp-gic
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/apple/
H A Dt600x-die0.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * Devices used on die 0 on the Apple T6002 "M1 Ultra" SoC and present on
10 nco: clock-controller@28e03c000 {
11 compatible = "apple,t6000-nco", "apple,nco";
14 #clock-cells = <1>;
17 aic: interrupt-controller@28e100000 {
18 compatible = "apple,t6000-aic", "apple,aic2";
19 #interrupt-cells = <4>;
20 interrupt-controller;
23 reg-names = "core", "event";
[all …]
/freebsd/sys/dev/bhnd/cores/chipc/
H A Dchipcreg.h1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
5 * Copyright (c) 2010-2015 Broadcom Corporation
10 * distributed with the Asus RT-N16 firmware source code release.
61 #define CHIPC_INTM 0x24 /**< interrupt mask */
77 /* siba backplane configuration broadcast (siba-only) */
81 #define CHIPC_GPIOPU 0x58 /**< pull-up mask (rev >= 20) */
82 #define CHIPC_GPIOPD 0x5C /**< pull down mask (rev >= 20) */
88 #define CHIPC_GPIOINTM 0x74 /**< gpio interrupt mask */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/soc/tegra/
H A Dnvidia,tegra20-pmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/tegra/nvidia,tegra20-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-pmc
17 - nvidia,tegra30-pmc
18 - nvidia,tegra114-pmc
19 - nvidia,tegra124-pmc
[all …]
/freebsd/sys/contrib/device-tree/Bindings/arm/tegra/
H A Dnvidia,tegra20-pmc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-pmc
17 - nvidia,tegra30-pmc
18 - nvidia,tegra114-pmc
19 - nvidia,tegra124-pmc
[all …]
/freebsd/sys/contrib/device-tree/src/arm/renesas/
H A Dr7s9210.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r7s9210-cpg-mssr.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <1>;
16 #size-cells = <1>;
20 #clock-cells = <0>;
21 compatible = "fixed-clock";
23 clock-frequency = <0>;
27 #clock-cells = <0>;
[all …]
H A Dr7s72100.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-14 Renesas Solutions Corp.
6 * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
9 #include <dt-bindings/clock/r7s72100-clock.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
15 #address-cells = <1>;
16 #size-cells = <1>;
32 #clock-cells = <0>;
33 compatible = "fixed-factor-clock";
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/marvell/
H A Darmada-3720-turris-mox.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include <dt-bindings/bus/moxtet.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include "armada-372x.dtsi"
16 compatible = "cznic,turris-mox", "marvell,armada3720",
28 stdout-path = "serial0:115200n8";
37 compatible = "gpio-leds";
41 linux,default-trigger = "default-on";
[all …]
/freebsd/sys/dev/igc/
H A Digc_nvm.c1 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
13 * igc_init_nvm_ops_generic - Initialize NVM function pointers
16 * Setups up the function pointers to no-op functions
20 struct igc_nvm_info *nvm = &hw->nvm; in igc_init_nvm_ops_generic()
24 nvm->ops.init_params = igc_null_ops_generic; in igc_init_nvm_ops_generic()
25 nvm->ops.acquire = igc_null_ops_generic; in igc_init_nvm_ops_generic()
26 nvm->ops.read = igc_null_read_nvm; in igc_init_nvm_ops_generic()
27 nvm->ops.release = igc_null_nvm_generic; in igc_init_nvm_ops_generic()
28 nvm->ops.reload = igc_reload_nvm_generic; in igc_init_nvm_ops_generic()
[all …]
/freebsd/sys/dev/qcom_qup/
H A Dqcom_spi_hw.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
55 #include <dev/spibus/spi.h>
78 sc->config.input_block_size = 4; in qcom_spi_hw_read_controller_transfer_sizes()
80 sc->config.input_block_size = val * 16; in qcom_spi_hw_read_controller_transfer_sizes()
86 sc->config.output_block_size = 4; in qcom_spi_hw_read_controller_transfer_sizes()
88 sc->config.output_block_size = val * 16; in qcom_spi_hw_read_controller_transfer_sizes()
93 sc->config.input_fifo_size = in qcom_spi_hw_read_controller_transfer_sizes()
94 sc->config.input_block_size * (2 << val); in qcom_spi_hw_read_controller_transfer_sizes()
99 sc->config.output_fifo_size = in qcom_spi_hw_read_controller_transfer_sizes()
[all …]
/freebsd/sys/dev/e1000/
H A De1000_nvm.c2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
40 * e1000_init_nvm_ops_generic - Initialize NVM function pointers
43 * Setups up the function pointers to no-op functions
47 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_init_nvm_ops_generic()
51 nvm->ops.init_params = e1000_null_ops_generic; in e1000_init_nvm_ops_generic()
52 nvm->ops.acquire = e1000_null_ops_generic; in e1000_init_nvm_ops_generic()
53 nvm->ops.read = e1000_null_read_nvm; in e1000_init_nvm_ops_generic()
54 nvm->ops.release = e1000_null_nvm_generic; in e1000_init_nvm_ops_generic()
55 nvm->ops.reload = e1000_reload_nvm_generic; in e1000_init_nvm_ops_generic()
[all …]
H A De1000_defines.h2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
94 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
122 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
144 /* mask to determine if packets should be dropped due to frame errors */
152 /* Same mask, but for extended and packet split descriptors */
172 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
173 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
261 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
263 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
[all …]
/freebsd/sys/netipsec/
H A Dkey.c3 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
127 * - SAs that are not in DEAD state will have (total external reference + 1)
130 * - SAs that are in DEAD state will have (total external reference)
225 (key_addrprotohash(&(idx)->src, &(idx)->dst, &(idx)->ul_proto) & \
272 (key_addrprotohash(&(idx)->src, &(idx)->dst, &(idx)->proto) & \
277 /* Hash table for lookup in SAD using SPI */
285 #define SAVHASH_HASHVAL(spi) (key_u32hash(spi) & V_savhash_mask) argument
286 #define SAVHASH_HASH(spi) &V_savhashtbl[SAVHASH_HASHVAL(spi)] argument
296 switch (dst->sa.sa_family) { in key_addrprotohash()
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dfsl-ls208xa.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
6 * Copyright 2017-2020 NXP
12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
32 #address-cells = <1>;
[all …]
H A Dfsl-lx2160a.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 // Device Tree Include file for Layerscape-LX2160A family SoC.
5 // Copyright 2018-2020 NXP
7 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
[all …]
/freebsd/sys/dev/ixgbe/
H A Dixgbe_common.c2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
64 * ixgbe_init_ops_generic - Inits function ptrs
71 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; in ixgbe_init_ops_generic()
72 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_init_ops_generic()
78 eeprom->ops.init_params = ixgbe_init_eeprom_params_generic; in ixgbe_init_ops_generic()
81 eeprom->ops.read = ixgbe_read_eerd_generic; in ixgbe_init_ops_generic()
82 eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_generic; in ixgbe_init_ops_generic()
84 eeprom->ops.read = ixgbe_read_eeprom_bit_bang_generic; in ixgbe_init_ops_generic()
85 eeprom->ops.read_buffer = in ixgbe_init_ops_generic()
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/exynos/google/
H A Dgs101.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2019-2023 Google LLC
6 * Copyright 2023 Linaro Ltd - <peter.griffin@linaro.org>
9 #include <dt-bindings/clock/google,gs101.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/soc/samsung,exynos-usi.h>
16 #address-cells = <2>;
17 #size-cells = <1>;
19 interrupt-parent = <&gic>;
[all …]
/freebsd/sys/dev/ae/
H A Dif_aereg.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
74 /* Interrupt mask register. */
84 #define AE_EADDR0_REG 0x1488 /* 5 - 2 bytes */
85 #define AE_EADDR1_REG 0x148c /* 1 - 0 bytes */
89 * L2 supports 64-bit addressing but all rings base addresses
97 Should be 120-byte aligned (i.e.
99 have 128-byte alignment). */
100 #define AE_TXD_BUFSIZE_REG 0x1548 /* Size of TxD ring in 4-byte units.
101 Should be 4-byte aligned. */
[all …]

123