Lines Matching +full:spi +full:- +full:present +full:- +full:mask

1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
33  * Register definitions for SafeNet SafeXcel-1141 crypto device.
68 #define	SAFE_HM_STAT		0x00a4	/* Host Masked Status (read-only) */
69 #define	SAFE_HI_CLR		0x00a4	/* Host Clear Interrupt (write-only) */
70 #define	SAFE_HI_MASK		0x00a8	/* Host Mask Control */
125 #define	SAFE_PE_CSR_XECODE_BADSPI	6	/* IPsec SPI mismatch */
129 #define	SAFE_PE_CSR_PAD_16	0x08000000	/* pad to 16-byte boundary */
130 #define	SAFE_PE_CSR_PAD_32	0x10000000	/* pad to 32-byte boundary */
131 #define	SAFE_PE_CSR_PAD_64	0x20000000	/* pad to 64-byte boundary */
132 #define	SAFE_PE_CSR_PAD_128	0x40000000	/* pad to 128-byte boundary */
133 #define	SAFE_PE_CSR_PAD_256	0x80000000	/* pad to 256-byte boundary */
162 #define	SAFE_HI_CFG_AUTOCLR	0x00000002	/* auto-clear pulse interrupt */
164 #define	SAFE_ENDIAN_PASS	0x000000e4	/* straight pass-thru */
165 #define	SAFE_ENDIAN_SWAB	0x0000001b	/* swap bytes in 32-bit word */
192 #define	SAFE_PE_DMASTAT_SPIMIS	0x00000080	/* SPI mismatch */
197 #define	SAFE_PE_DMASTAT_PEISIZE	0x003ff000	/* PE input size:32-bit words */
198 #define	SAFE_PE_DMASTAT_PEOSIZE	0xffc00000	/* PE out. size:32-bit words */
238 #define	SAFE_DEVINFO_DES	0x00000100	/* DES/3DES support present */
239 #define	SAFE_DEVINFO_ARC4	0x00000200	/* ARC4 support present */
240 #define	SAFE_DEVINFO_AES	0x00000400	/* AES support present */
241 #define	SAFE_DEVINFO_MD5	0x00001000	/* MD5 support present */
242 #define	SAFE_DEVINFO_SHA1	0x00002000	/* SHA-1 support present */
243 #define	SAFE_DEVINFO_RIPEMD	0x00004000	/* RIPEMD support present */
244 #define	SAFE_DEVINFO_DEFLATE	0x00010000	/* Deflate support present */
245 #define	SAFE_DEVINFO_SARAM	0x00100000	/* on-chip SA RAM present */
246 #define	SAFE_DEVINFO_EMIBUS	0x00200000	/* EMI bus present */
247 #define	SAFE_DEVINFO_PKEY	0x00400000	/* public key support present */
248 #define	SAFE_DEVINFO_RNG	0x00800000	/* RNG present */
259 #define	SAFE_PK_FUNC_LSHIFT	0x00000040	/* Left-shift function */
260 #define	SAFE_PK_FUNC_RSHIFT	0x00000080	/* Right-shift function */
264 #define	SAFE_PK_FUNC_EXP16	0x00002000	/* Exponentiate (4-bit ACT) */
265 #define	SAFE_PK_FUNC_EXP4	0x00004000	/* Exponentiate (2-bit ACT) */
269 #define	SAFE_RNG_CTRL_PRE_LFSR	0x00000001	/* enable output pre-LFSR */
288 	u_int32_t	d_csr;			/* per-packet control/status */
322 	u_int32_t	sa_spi;			/* SPI */
324 	u_int32_t	sa_seqmask[2];		/* sequence number mask */
334 #define	SAFE_SA_CMD0_OP_BOTH	0x00000001	/* encrypt-hash/hash-decrypto */
335 #define	SAFE_SA_CMD0_OP_HASH	0x00000003	/* hash (outbound-only) */
356 #define	SAFE_SA_CMD0_SHA1	0x00001000	/* SHA-1 hash algorithm */
390 #define	SAFE_SA_CMD1_64BIT	0x00000000	/* 64-bit crypto feedback */
391 #define	SAFE_SA_CMD1_8BIT	0x00000400	/* 8-bit crypto feedback */
392 #define	SAFE_SA_CMD1_1BIT	0x00000800	/* 1-bit crypto feedback */
393 #define	SAFE_SA_CMD1_128BIT	0x00000c00	/* 128-bit crypto feedback */
400 #define	SAFE_SA_CMD1_AES128	0x02000000	/* 128-bit AES key */
401 #define	SAFE_SA_CMD1_AES192	0x03000000	/* 192-bit AES key */
402 #define	SAFE_SA_CMD1_AES256	0x04000000	/* 256-bit AES key */