Lines Matching +full:spi +full:- +full:present +full:- +full:mask
2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
94 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
122 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
144 /* mask to determine if packets should be dropped due to frame errors */
152 /* Same mask, but for extended and packet split descriptors */
172 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
173 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
261 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
263 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
264 #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
325 #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
340 #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
341 #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
343 /* Constants used to interpret the masked PCI-X bus speed. */
344 #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus spd 50-66MHz */
345 #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus spd 66-100MHz */
346 #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus spd 100-133MHz*/
365 /* 1000/H is not supported, nor spec-compliant. */
420 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
578 #define E1000_PBA_ECC_COUNTER_MASK 0xFFF00000 /* ECC counter mask */
601 /* This defines the bits that are set in the Interrupt Mask
616 /* Interrupt Mask Set */
639 /* Extended Interrupt Mask Set */
727 /* Loop limit on how long we wait for auto-negotiation to complete */
742 #define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */
743 #define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
750 #define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */
751 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
754 #define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */
769 #define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */
821 #define E1000_TTQF_DISABLE_MASK 0xF0008000 /* TTQF Disable Mask */
823 #define E1000_TTQF_PROTOCOL_MASK 0xFF /* TTQF Protocol Mask */
832 #define E1000_TTQF_RX_QUEUE_MASK 0x70000 /* TTQF Queue Mask */
833 #define E1000_TTQF_MASK_ENABLE 0x10000000 /* TTQF Mask Enable Bit */
834 #define E1000_IMIR_CLEAR_MASK 0xF001FFFF /* IMIR Reg Clear Mask */
837 #define E1000_IMIREXT_CLEAR_MASK 0x7FFFF /* IMIREXT Reg Clear Mask */
986 /* 1000BASE-T Control Register */
1002 /* 1000BASE-T Status Register */
1025 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
1026 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1038 #define E1000_EECD_PRES 0x00000100 /* NVM Present */
1046 #define E1000_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */
1153 /* Mask bits for fields in Word 0x24 of the NVM */
1162 /* Mask bits for fields in Word 0x0f of the NVM */
1168 /* Mask bits for fields in Word 0x1a of the NVM */
1171 /* Mask bits for fields in Word 0x03 of the EEPROM */
1192 /* NVM Commands - Microwire */
1199 /* NVM Commands - SPI */
1203 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1207 /* SPI NVM Status Register */
1231 /* PCI/PCI-X/PCI-EX Config space */
1255 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1306 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
1317 * 1 = 50-80M
1318 * 2 = 80-110M
1319 * 3 = 110-140M
1382 * 15-5: page
1383 * 4-0: register offset
1401 /* Page 193 - Port Control Registers */
1406 /* Page 194 - KMRN Registers */
1450 /* Tx Rate-Scheduler Config fields */
1467 /* DMA Coalescing BMC-to-OS Watchdog Enable */
1516 #define E1000_STATUS_LAN_ID_MASK 0x00000000C /* Mask for Lan ID field */