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Searched +full:speed +full:- +full:grade (Results 1 – 18 of 18) sorted by relevance

/linux/Documentation/devicetree/bindings/clock/
H A Dxlnx,clocking-wizard.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
20 - xlnx,clocking-wizard
21 - xlnx,clocking-wizard-v5.2
22 - xlnx,clocking-wizard-v6.0
23 - xlnx,versal-clk-wizard
29 "#clock-cells":
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H A Dsilabs,si5341.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mike Looijmans <mike.looijmans@topic.nl>
18 https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
20 https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
22 https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf
33 chip at boot, in case you have a (pre-)programmed device. If the PLL is not
37 The device type, speed grade and revision are determined runtime by probing.
42 - silabs,si5340
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/linux/Documentation/devicetree/bindings/cpufreq/
H A Dimx-cpufreq-dt.txt1 i.MX CPUFreq-DT OPP bindings
5 "speed grading" value which are written in fuses. These bits are combined with
6 the opp-supported-hw values for each OPP to check if the OPP is allowed.
9 --------------------
11 For each opp entry in 'operating-points-v2' table:
12 - opp-supported-hw: Two bitmaps indicating:
13 - Supported speed grade mask
14 - Supported market segment mask
21 --------
24 compatible = "operating-points-v2";
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/linux/Documentation/devicetree/bindings/nvmem/
H A Dimx-ocotp.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/imx-ocotp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX On-Chip OTP Controller (OCOTP)
10 - Shawn Guo <shawnguo@kernel.org>
11 - Sascha Hauer <s.hauer@pengutronix.de>
12 - Fabio Estevam <festevam@gmail.com>
15 This binding represents the on-chip eFuse OTP controller found on
20 - $ref: nvmem.yaml#
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/linux/drivers/cpufreq/
H A Dsun50i-cpufreq-nvmem.c1 // SPDX-License-Identifier: GPL-2.0
5 * The sun50i-cpufreq-nvmem driver reads the efuse value from the SoC to
13 #include <linux/arm-smccc.h>
16 #include <linux/nvmem-consumer.h>
42 * the slowest bin. Expected efuse values are 1-3, slowest in sun50i_h6_efuse_xlate()
46 return efuse_value - 1; in sun50i_h6_efuse_xlate()
79 * returned speedbin index is 4 -> 0/2 -> 3 -> 1, from worst to best.
118 pr_warn("sun50i-cpufreq-nvmem: unknown speed bin 0x%x, using default bin 0\n", in sun50i_h616_efuse_xlate()
140 { .compatible = "allwinner,sun50i-h6-operating-points",
143 { .compatible = "allwinner,sun50i-a100-operating-points",
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/linux/drivers/clk/
H A Dclk-si544.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
39 /* Max freq depends on speed grade */
45 /* VCO range is 10.8 .. 12.1 GHz, max depends on speed grade */
68 * struct clk_si544_muldiv - Multiplier/divider settings
73 * If ls_div_bits is non-zero, hs_div must be even
74 * @delta_m: Frequency shift for small -950..+950 ppm changes, 24 bit
87 return regmap_update_bits(data->regmap, SI544_REG_OE_STATE, in si544_enable_output()
111 err = regmap_read(data->regmap, SI544_REG_OE_STATE, &val); in si544_is_prepared()
125 err = regmap_bulk_read(data->regmap, SI544_REG_HS_DIV, reg, 2); in si544_get_muldiv()
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H A Dclk-axi-clkgen.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2012-2013 Analog Devices Inc.
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
9 #include <linux/adi-axi-common.h>
12 #include <linux/clk-provider.h>
151 d_min = max(DIV_ROUND_UP(fin, limits->fpfd_max), 1); in axi_clkgen_calc_params()
152 d_max = min(fin / limits->fpfd_min, 80); in axi_clkgen_calc_params()
155 fvco_min_fract = limits->fvco_min << fract_shift; in axi_clkgen_calc_params()
156 fvco_max_fract = limits->fvco_max << fract_shift; in axi_clkgen_calc_params()
171 if (abs(f - fout) < abs(best_f - fout)) { in axi_clkgen_calc_params()
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/linux/drivers/clk/xilinx/
H A Dclk-xlnx-clock-wizard.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013 - 2021 Xilinx
14 #include <linux/clk-provider.h>
88 /* Divider limits, from UG572 Table 3-4 for Ultrascale+ */
112 #define div_mask(width) ((1 << (width)) - 1)
125 * struct clk_wzrd - Clock wizard private data structure
132 * @speed_grade: Speed grade of the device
148 * struct clk_wzrd_divider - clock divider specific to clk_wzrd
150 * @hw: handle between common and hardware-specific interfaces
186 /* maximum frequencies for input/output clocks per speed grade */
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/linux/arch/arm/boot/dts/ti/omap/
H A Domap34xx.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/media/omap3-isp.h>
16 /* OMAP343x/OMAP35xx variants OPP1-6 */
17 operating-points-v2 = <&cpu0_opp_table>;
19 clock-latency = <300000>; /* From legacy driver */
20 #cooling-cells = <2>;
24 cpu0_opp_table: opp-table {
25 compatible = "operating-points-v2-ti-cpu";
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H A Dam5729-beagleboneai.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014-2019 Texas Instruments Incorporated - https://www.ti.com/
6 /dts-v1/;
9 #include "am57xx-commercial-grade.dtsi"
10 #include "dra74x-mmc-iodelay.dtsi"
11 #include "dra74-ipu-dsp-common.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/pinctrl/dra.h>
18 compatible = "beagle,am5729-beagleboneai", "ti,am5728",
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/linux/drivers/staging/most/Documentation/
H A Ddriver_usage.txt5 access a MOST network: The Automotive Information Backbone and the de-facto
6 standard for high-bandwidth automotive multimedia networking.
9 for the efficient and low-cost transport of control, real-time and packet
12 also supports various speed grades up to 150 Mbps.
23 of Automotive Grade Linux to create open source software solutions for
128 - buffer_size
130 - subbuffer_size
131 configure the sub-buffer size for this channel (needed for
133 - num_buffers
135 - datatype
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/linux/Documentation/driver-api/thermal/
H A Dpower_allocator.rst6 -----------
20 --------------
23 Proportional-Integral-Derivative controller (PID controller) with
29 - e = desired_temperature - current_temperature
30 - err_integral is the sum of previous errors
31 - diff_err = e - previous_error
39 | +----------+ +---+
40 | +----->| diff_err |-->| X |------+
41 | | +----------+ +---+ |
47 +---+ | +-------+ +---+ +---+ +---+ +----------+
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/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-a100.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/sun50i-a100-ccu.h>
8 #include <dt-bindings/clock/sun50i-a100-r-ccu.h>
9 #include <dt-bindings/reset/sun50i-a100-ccu.h>
10 #include <dt-bindings/reset/sun50i-a100-r-ccu.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
18 #address-cells = <1>;
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H A Dsun50i-h616.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/sun50i-h616-ccu.h>
8 #include <dt-bindings/clock/sun50i-h6-r-ccu.h>
9 #include <dt-bindings/clock/sun6i-rtc.h>
10 #include <dt-bindings/reset/sun50i-h616-ccu.h>
11 #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
12 #include <dt-bindings/thermal/thermal.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
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H A Dsun50i-h6.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/sun50i-h6-ccu.h>
6 #include <dt-bindings/clock/sun50i-h6-r-ccu.h>
7 #include <dt-bindings/clock/sun6i-rtc.h>
8 #include <dt-bindings/clock/sun8i-de2.h>
9 #include <dt-bindings/clock/sun8i-tcon-top.h>
10 #include <dt-bindings/reset/sun50i-h6-ccu.h>
11 #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
12 #include <dt-bindings/reset/sun8i-de2.h>
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/linux/drivers/usb/serial/
H A Dftdi_sio_ids.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Philipp Gühring - pg@futureware.at - added the Device ID of the USB relais
25 #define FTDI_4232H_PID 0x6011 /* Quad channel hi-speed device */
26 #define FTDI_232H_PID 0x6014 /* Single channel hi-speed device */
27 #define FTDI_FTX_PID 0x6015 /* FT-X series (FT201X, FT230X, FT231X, etc) */
28 #define FTDI_FT2233HP_PID 0x6040 /* Dual channel hi-speed device with PD */
29 #define FTDI_FT4233HP_PID 0x6041 /* Quad channel hi-speed device with PD */
30 #define FTDI_FT2232HP_PID 0x6042 /* Dual channel hi-speed device with PD */
31 #define FTDI_FT4232HP_PID 0x6043 /* Quad channel hi-speed device with PD */
32 #define FTDI_FT233HP_PID 0x6044 /* Dual channel hi-speed device with PD */
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/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mn.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mn-clock.h>
7 #include <dt-bindings/power/imx8mn-power.h>
8 #include <dt-bindings/reset/imx8mq-reset.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
14 #include "imx8mn-pinfunc.h"
17 interrupt-parent = <&gic>;
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/linux/drivers/net/ethernet/sfc/siena/
H A Dmcdi_pcol.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
38 /* The rest of these are firmware-defined */
46 /* Values to be written to the per-port status dword in shared
71 * | | \--- Response
72 * | \------- Error
73 * \------------------------------ Resync (always set)
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