Lines Matching +full:speed +full:- +full:grade

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
20       - xlnx,clocking-wizard
21       - xlnx,clocking-wizard-v5.2
22       - xlnx,clocking-wizard-v6.0
23       - xlnx,versal-clk-wizard
29   "#clock-cells":
34       - description: clock input
35       - description: axi clock
37   clock-names:
39       - const: clk_in1
40       - const: s_axi_aclk
43   xlnx,speed-grade:
47       Speed grade of the device. Higher the speed grade faster is the FPGA device.
49   xlnx,nr-outputs:
57   - compatible
58   - reg
59   - "#clock-cells"
60   - clocks
61   - clock-names
62   - xlnx,speed-grade
63   - xlnx,nr-outputs
68   - |
69     clock-controller@b0000000  {
70         compatible = "xlnx,clocking-wizard";
72         #clock-cells = <1>;
73         xlnx,speed-grade = <1>;
74         xlnx,nr-outputs = <6>;
75         clock-names = "clk_in1", "s_axi_aclk";