1// SPDX-License-Identifier: GPL-2.0 2// 3// Copyright 2014 Freescale Semiconductor, Inc. 4 5#include <dt-bindings/clock/imx6sx-clock.h> 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/input/input.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include "imx6sx-pinfunc.h" 10 11/ { 12 #address-cells = <1>; 13 #size-cells = <1>; 14 /* 15 * The decompressor and also some bootloaders rely on a 16 * pre-existing /chosen node to be available to insert the 17 * command line and merge other ATAGS info. 18 */ 19 chosen {}; 20 21 aliases { 22 can0 = &flexcan1; 23 can1 = &flexcan2; 24 ethernet0 = &fec1; 25 ethernet1 = &fec2; 26 gpio0 = &gpio1; 27 gpio1 = &gpio2; 28 gpio2 = &gpio3; 29 gpio3 = &gpio4; 30 gpio4 = &gpio5; 31 gpio5 = &gpio6; 32 gpio6 = &gpio7; 33 i2c0 = &i2c1; 34 i2c1 = &i2c2; 35 i2c2 = &i2c3; 36 i2c3 = &i2c4; 37 mmc0 = &usdhc1; 38 mmc1 = &usdhc2; 39 mmc2 = &usdhc3; 40 mmc3 = &usdhc4; 41 serial0 = &uart1; 42 serial1 = &uart2; 43 serial2 = &uart3; 44 serial3 = &uart4; 45 serial4 = &uart5; 46 serial5 = &uart6; 47 spi0 = &ecspi1; 48 spi1 = &ecspi2; 49 spi2 = &ecspi3; 50 spi3 = &ecspi4; 51 spi4 = &ecspi5; 52 usb0 = &usbotg1; 53 usb1 = &usbotg2; 54 usb2 = &usbh; 55 usbphy0 = &usbphy1; 56 usbphy1 = &usbphy2; 57 }; 58 59 cpus { 60 #address-cells = <1>; 61 #size-cells = <0>; 62 63 cpu0: cpu@0 { 64 compatible = "arm,cortex-a9"; 65 device_type = "cpu"; 66 reg = <0>; 67 next-level-cache = <&L2>; 68 operating-points = < 69 /* kHz uV */ 70 996000 1250000 71 792000 1175000 72 396000 1075000 73 198000 975000 74 >; 75 fsl,soc-operating-points = < 76 /* ARM kHz SOC uV */ 77 996000 1175000 78 792000 1175000 79 396000 1175000 80 198000 1175000 81 >; 82 clock-latency = <61036>; /* two CLK32 periods */ 83 #cooling-cells = <2>; 84 clocks = <&clks IMX6SX_CLK_ARM>, 85 <&clks IMX6SX_CLK_PLL2_PFD2>, 86 <&clks IMX6SX_CLK_STEP>, 87 <&clks IMX6SX_CLK_PLL1_SW>, 88 <&clks IMX6SX_CLK_PLL1_SYS>; 89 clock-names = "arm", "pll2_pfd2_396m", "step", 90 "pll1_sw", "pll1_sys"; 91 arm-supply = <®_arm>; 92 soc-supply = <®_soc>; 93 nvmem-cells = <&cpu_speed_grade>; 94 nvmem-cell-names = "speed_grade"; 95 }; 96 }; 97 98 ckil: clock-ckil { 99 compatible = "fixed-clock"; 100 #clock-cells = <0>; 101 clock-frequency = <32768>; 102 clock-output-names = "ckil"; 103 }; 104 105 osc: clock-osc { 106 compatible = "fixed-clock"; 107 #clock-cells = <0>; 108 clock-frequency = <24000000>; 109 clock-output-names = "osc"; 110 }; 111 112 ipp_di0: clock-ipp-di0 { 113 compatible = "fixed-clock"; 114 #clock-cells = <0>; 115 clock-frequency = <0>; 116 clock-output-names = "ipp_di0"; 117 }; 118 119 ipp_di1: clock-ipp-di1 { 120 compatible = "fixed-clock"; 121 #clock-cells = <0>; 122 clock-frequency = <0>; 123 clock-output-names = "ipp_di1"; 124 }; 125 126 anaclk1: clock-anaclk1 { 127 compatible = "fixed-clock"; 128 #clock-cells = <0>; 129 clock-frequency = <0>; 130 clock-output-names = "anaclk1"; 131 }; 132 133 anaclk2: clock-anaclk2 { 134 compatible = "fixed-clock"; 135 #clock-cells = <0>; 136 clock-frequency = <0>; 137 clock-output-names = "anaclk2"; 138 }; 139 140 mqs: mqs { 141 compatible = "fsl,imx6sx-mqs"; 142 gpr = <&gpr>; 143 status = "disabled"; 144 }; 145 146 pmu { 147 compatible = "arm,cortex-a9-pmu"; 148 interrupt-parent = <&gpc>; 149 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 150 }; 151 152 usbphynop1: usbphynop1 { 153 compatible = "usb-nop-xceiv"; 154 #phy-cells = <0>; 155 }; 156 157 soc: soc { 158 #address-cells = <1>; 159 #size-cells = <1>; 160 compatible = "simple-bus"; 161 interrupt-parent = <&gpc>; 162 ranges; 163 164 ocram_s: sram@8f8000 { 165 compatible = "mmio-sram"; 166 reg = <0x008f8000 0x4000>; 167 ranges = <0 0x008f8000 0x4000>; 168 #address-cells = <1>; 169 #size-cells = <1>; 170 clocks = <&clks IMX6SX_CLK_OCRAM_S>; 171 }; 172 173 ocram: sram@900000 { 174 compatible = "mmio-sram"; 175 reg = <0x00900000 0x20000>; 176 ranges = <0 0x00900000 0x20000>; 177 #address-cells = <1>; 178 #size-cells = <1>; 179 clocks = <&clks IMX6SX_CLK_OCRAM>; 180 }; 181 182 intc: interrupt-controller@a01000 { 183 compatible = "arm,cortex-a9-gic"; 184 #interrupt-cells = <3>; 185 interrupt-controller; 186 reg = <0x00a01000 0x1000>, 187 <0x00a00100 0x100>; 188 interrupt-parent = <&intc>; 189 }; 190 191 L2: cache-controller@a02000 { 192 compatible = "arm,pl310-cache"; 193 reg = <0x00a02000 0x1000>; 194 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 195 cache-unified; 196 cache-level = <2>; 197 arm,tag-latency = <4 2 3>; 198 arm,data-latency = <4 2 3>; 199 }; 200 201 gpu: gpu@1800000 { 202 compatible = "vivante,gc"; 203 reg = <0x01800000 0x4000>; 204 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 205 clocks = <&clks IMX6SX_CLK_GPU>, 206 <&clks IMX6SX_CLK_GPU>, 207 <&clks IMX6SX_CLK_GPU>; 208 clock-names = "bus", "core", "shader"; 209 power-domains = <&pd_pu>; 210 }; 211 212 dma_apbh: dma-controller@1804000 { 213 compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh"; 214 reg = <0x01804000 0x2000>; 215 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 219 #dma-cells = <1>; 220 dma-channels = <4>; 221 clocks = <&clks IMX6SX_CLK_APBH_DMA>; 222 }; 223 224 gpmi: nand-controller@1806000 { 225 compatible = "fsl,imx6sx-gpmi-nand"; 226 #address-cells = <1>; 227 #size-cells = <1>; 228 reg = <0x01806000 0x2000>, <0x01808000 0x4000>; 229 reg-names = "gpmi-nand", "bch"; 230 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 231 interrupt-names = "bch"; 232 clocks = <&clks IMX6SX_CLK_GPMI_IO>, 233 <&clks IMX6SX_CLK_GPMI_APB>, 234 <&clks IMX6SX_CLK_GPMI_BCH>, 235 <&clks IMX6SX_CLK_GPMI_BCH_APB>, 236 <&clks IMX6SX_CLK_PER1_BCH>; 237 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", 238 "gpmi_bch_apb", "per1_bch"; 239 dmas = <&dma_apbh 0>; 240 dma-names = "rx-tx"; 241 status = "disabled"; 242 }; 243 244 aips1: bus@2000000 { 245 compatible = "fsl,aips-bus", "simple-bus"; 246 #address-cells = <1>; 247 #size-cells = <1>; 248 reg = <0x02000000 0x100000>; 249 ranges; 250 251 spba-bus@2000000 { 252 compatible = "fsl,spba-bus", "simple-bus"; 253 #address-cells = <1>; 254 #size-cells = <1>; 255 reg = <0x02000000 0x40000>; 256 ranges; 257 258 spdif: spdif@2004000 { 259 compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif"; 260 reg = <0x02004000 0x4000>; 261 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 262 dmas = <&sdma 14 18 0>, 263 <&sdma 15 18 0>; 264 dma-names = "rx", "tx"; 265 clocks = <&clks IMX6SX_CLK_SPDIF_GCLK>, 266 <&clks IMX6SX_CLK_OSC>, 267 <&clks IMX6SX_CLK_SPDIF>, 268 <&clks 0>, <&clks 0>, <&clks 0>, 269 <&clks IMX6SX_CLK_IPG>, 270 <&clks 0>, <&clks 0>, 271 <&clks IMX6SX_CLK_SPBA>; 272 clock-names = "core", "rxtx0", 273 "rxtx1", "rxtx2", 274 "rxtx3", "rxtx4", 275 "rxtx5", "rxtx6", 276 "rxtx7", "spba"; 277 status = "disabled"; 278 }; 279 280 ecspi1: spi@2008000 { 281 #address-cells = <1>; 282 #size-cells = <0>; 283 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; 284 reg = <0x02008000 0x4000>; 285 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 286 clocks = <&clks IMX6SX_CLK_ECSPI1>, 287 <&clks IMX6SX_CLK_ECSPI1>; 288 clock-names = "ipg", "per"; 289 status = "disabled"; 290 }; 291 292 ecspi2: spi@200c000 { 293 #address-cells = <1>; 294 #size-cells = <0>; 295 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; 296 reg = <0x0200c000 0x4000>; 297 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 298 clocks = <&clks IMX6SX_CLK_ECSPI2>, 299 <&clks IMX6SX_CLK_ECSPI2>; 300 clock-names = "ipg", "per"; 301 status = "disabled"; 302 }; 303 304 ecspi3: spi@2010000 { 305 #address-cells = <1>; 306 #size-cells = <0>; 307 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; 308 reg = <0x02010000 0x4000>; 309 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 310 clocks = <&clks IMX6SX_CLK_ECSPI3>, 311 <&clks IMX6SX_CLK_ECSPI3>; 312 clock-names = "ipg", "per"; 313 status = "disabled"; 314 }; 315 316 ecspi4: spi@2014000 { 317 #address-cells = <1>; 318 #size-cells = <0>; 319 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; 320 reg = <0x02014000 0x4000>; 321 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 322 clocks = <&clks IMX6SX_CLK_ECSPI4>, 323 <&clks IMX6SX_CLK_ECSPI4>; 324 clock-names = "ipg", "per"; 325 status = "disabled"; 326 }; 327 328 uart1: serial@2020000 { 329 compatible = "fsl,imx6sx-uart", 330 "fsl,imx6q-uart", "fsl,imx21-uart"; 331 reg = <0x02020000 0x4000>; 332 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 333 clocks = <&clks IMX6SX_CLK_UART_IPG>, 334 <&clks IMX6SX_CLK_UART_SERIAL>; 335 clock-names = "ipg", "per"; 336 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; 337 dma-names = "rx", "tx"; 338 status = "disabled"; 339 }; 340 341 esai: esai@2024000 { 342 compatible = "fsl,imx35-esai"; 343 reg = <0x02024000 0x4000>; 344 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 345 clocks = <&clks IMX6SX_CLK_ESAI_IPG>, 346 <&clks IMX6SX_CLK_ESAI_EXTAL>, 347 <&clks IMX6SX_CLK_ESAI_IPG>, 348 <&clks IMX6SX_CLK_SPBA>; 349 clock-names = "core", "extal", 350 "fsys", "spba"; 351 dmas = <&sdma 23 21 0>, 352 <&sdma 24 21 0>; 353 dma-names = "rx", "tx"; 354 status = "disabled"; 355 }; 356 357 ssi1: ssi@2028000 { 358 #sound-dai-cells = <0>; 359 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; 360 reg = <0x02028000 0x4000>; 361 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 362 clocks = <&clks IMX6SX_CLK_SSI1_IPG>, 363 <&clks IMX6SX_CLK_SSI1>; 364 clock-names = "ipg", "baud"; 365 dmas = <&sdma 37 1 0>, <&sdma 38 1 0>; 366 dma-names = "rx", "tx"; 367 fsl,fifo-depth = <15>; 368 status = "disabled"; 369 }; 370 371 ssi2: ssi@202c000 { 372 #sound-dai-cells = <0>; 373 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; 374 reg = <0x0202c000 0x4000>; 375 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 376 clocks = <&clks IMX6SX_CLK_SSI2_IPG>, 377 <&clks IMX6SX_CLK_SSI2>; 378 clock-names = "ipg", "baud"; 379 dmas = <&sdma 41 1 0>, <&sdma 42 1 0>; 380 dma-names = "rx", "tx"; 381 fsl,fifo-depth = <15>; 382 status = "disabled"; 383 }; 384 385 ssi3: ssi@2030000 { 386 #sound-dai-cells = <0>; 387 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; 388 reg = <0x02030000 0x4000>; 389 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 390 clocks = <&clks IMX6SX_CLK_SSI3_IPG>, 391 <&clks IMX6SX_CLK_SSI3>; 392 clock-names = "ipg", "baud"; 393 dmas = <&sdma 45 1 0>, <&sdma 46 1 0>; 394 dma-names = "rx", "tx"; 395 fsl,fifo-depth = <15>; 396 status = "disabled"; 397 }; 398 399 asrc: asrc@2034000 { 400 compatible = "fsl,imx6sx-asrc", "fsl,imx53-asrc"; 401 reg = <0x02034000 0x4000>; 402 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 403 clocks = <&clks IMX6SX_CLK_ASRC_IPG>, 404 <&clks IMX6SX_CLK_ASRC_MEM>, <&clks 0>, 405 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, 406 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, 407 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, 408 <&clks IMX6SX_CLK_SPDIF>, <&clks 0>, <&clks 0>, 409 <&clks IMX6SX_CLK_SPBA>; 410 clock-names = "mem", "ipg", "asrck_0", 411 "asrck_1", "asrck_2", "asrck_3", "asrck_4", 412 "asrck_5", "asrck_6", "asrck_7", "asrck_8", 413 "asrck_9", "asrck_a", "asrck_b", "asrck_c", 414 "asrck_d", "asrck_e", "asrck_f", "spba"; 415 dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, 416 <&sdma 19 23 1>, <&sdma 20 23 1>, 417 <&sdma 21 23 1>, <&sdma 22 23 1>; 418 dma-names = "rxa", "rxb", "rxc", 419 "txa", "txb", "txc"; 420 fsl,asrc-rate = <48000>; 421 fsl,asrc-width = <16>; 422 status = "okay"; 423 }; 424 }; 425 426 pwm1: pwm@2080000 { 427 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 428 reg = <0x02080000 0x4000>; 429 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 430 clocks = <&clks IMX6SX_CLK_PWM1>, 431 <&clks IMX6SX_CLK_PWM1>; 432 clock-names = "ipg", "per"; 433 #pwm-cells = <3>; 434 }; 435 436 pwm2: pwm@2084000 { 437 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 438 reg = <0x02084000 0x4000>; 439 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 440 clocks = <&clks IMX6SX_CLK_PWM2>, 441 <&clks IMX6SX_CLK_PWM2>; 442 clock-names = "ipg", "per"; 443 #pwm-cells = <3>; 444 }; 445 446 pwm3: pwm@2088000 { 447 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 448 reg = <0x02088000 0x4000>; 449 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 450 clocks = <&clks IMX6SX_CLK_PWM3>, 451 <&clks IMX6SX_CLK_PWM3>; 452 clock-names = "ipg", "per"; 453 #pwm-cells = <3>; 454 }; 455 456 pwm4: pwm@208c000 { 457 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 458 reg = <0x0208c000 0x4000>; 459 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 460 clocks = <&clks IMX6SX_CLK_PWM4>, 461 <&clks IMX6SX_CLK_PWM4>; 462 clock-names = "ipg", "per"; 463 #pwm-cells = <3>; 464 }; 465 466 flexcan1: can@2090000 { 467 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan"; 468 reg = <0x02090000 0x4000>; 469 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 470 clocks = <&clks IMX6SX_CLK_CAN1_IPG>, 471 <&clks IMX6SX_CLK_CAN1_SERIAL>; 472 clock-names = "ipg", "per"; 473 fsl,stop-mode = <&gpr 0x10 1>; 474 status = "disabled"; 475 }; 476 477 flexcan2: can@2094000 { 478 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan"; 479 reg = <0x02094000 0x4000>; 480 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 481 clocks = <&clks IMX6SX_CLK_CAN2_IPG>, 482 <&clks IMX6SX_CLK_CAN2_SERIAL>; 483 clock-names = "ipg", "per"; 484 fsl,stop-mode = <&gpr 0x10 2>; 485 status = "disabled"; 486 }; 487 488 gpt: timer@2098000 { 489 compatible = "fsl,imx6sx-gpt", "fsl,imx6dl-gpt"; 490 reg = <0x02098000 0x4000>; 491 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 492 clocks = <&clks IMX6SX_CLK_GPT_BUS>, 493 <&clks IMX6SX_CLK_GPT_3M>; 494 clock-names = "ipg", "per"; 495 }; 496 497 gpio1: gpio@209c000 { 498 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; 499 reg = <0x0209c000 0x4000>; 500 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 501 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 502 gpio-controller; 503 #gpio-cells = <2>; 504 interrupt-controller; 505 #interrupt-cells = <2>; 506 gpio-ranges = <&iomuxc 0 5 26>; 507 }; 508 509 gpio2: gpio@20a0000 { 510 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; 511 reg = <0x020a0000 0x4000>; 512 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 514 gpio-controller; 515 #gpio-cells = <2>; 516 interrupt-controller; 517 #interrupt-cells = <2>; 518 gpio-ranges = <&iomuxc 0 31 20>; 519 }; 520 521 gpio3: gpio@20a4000 { 522 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; 523 reg = <0x020a4000 0x4000>; 524 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 526 gpio-controller; 527 #gpio-cells = <2>; 528 interrupt-controller; 529 #interrupt-cells = <2>; 530 gpio-ranges = <&iomuxc 0 51 29>; 531 }; 532 533 gpio4: gpio@20a8000 { 534 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; 535 reg = <0x020a8000 0x4000>; 536 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 537 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 538 gpio-controller; 539 #gpio-cells = <2>; 540 interrupt-controller; 541 #interrupt-cells = <2>; 542 gpio-ranges = <&iomuxc 0 80 32>; 543 }; 544 545 gpio5: gpio@20ac000 { 546 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; 547 reg = <0x020ac000 0x4000>; 548 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 549 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 550 gpio-controller; 551 #gpio-cells = <2>; 552 interrupt-controller; 553 #interrupt-cells = <2>; 554 gpio-ranges = <&iomuxc 0 112 24>; 555 }; 556 557 gpio6: gpio@20b0000 { 558 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; 559 reg = <0x020b0000 0x4000>; 560 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 562 gpio-controller; 563 #gpio-cells = <2>; 564 interrupt-controller; 565 #interrupt-cells = <2>; 566 gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>; 567 }; 568 569 gpio7: gpio@20b4000 { 570 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; 571 reg = <0x020b4000 0x4000>; 572 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 574 gpio-controller; 575 #gpio-cells = <2>; 576 interrupt-controller; 577 #interrupt-cells = <2>; 578 gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>; 579 }; 580 581 kpp: keypad@20b8000 { 582 compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp"; 583 reg = <0x020b8000 0x4000>; 584 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 585 clocks = <&clks IMX6SX_CLK_IPG>; 586 status = "disabled"; 587 }; 588 589 wdog1: watchdog@20bc000 { 590 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; 591 reg = <0x020bc000 0x4000>; 592 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 593 clocks = <&clks IMX6SX_CLK_IPG>; 594 }; 595 596 wdog2: watchdog@20c0000 { 597 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; 598 reg = <0x020c0000 0x4000>; 599 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 600 clocks = <&clks IMX6SX_CLK_IPG>; 601 status = "disabled"; 602 }; 603 604 clks: clock-controller@20c4000 { 605 compatible = "fsl,imx6sx-ccm"; 606 reg = <0x020c4000 0x4000>; 607 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 608 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 609 #clock-cells = <1>; 610 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>, <&anaclk1>, <&anaclk2>; 611 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "anaclk1", "anaclk2"; 612 }; 613 614 anatop: anatop@20c8000 { 615 compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop", 616 "syscon", "simple-mfd"; 617 reg = <0x020c8000 0x1000>; 618 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 619 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 620 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 621 622 reg_vdd1p1: regulator-1p1 { 623 compatible = "fsl,anatop-regulator"; 624 regulator-name = "vdd1p1"; 625 regulator-min-microvolt = <1000000>; 626 regulator-max-microvolt = <1200000>; 627 regulator-always-on; 628 anatop-reg-offset = <0x110>; 629 anatop-vol-bit-shift = <8>; 630 anatop-vol-bit-width = <5>; 631 anatop-min-bit-val = <4>; 632 anatop-min-voltage = <800000>; 633 anatop-max-voltage = <1375000>; 634 anatop-enable-bit = <0>; 635 }; 636 637 reg_vdd3p0: regulator-3p0 { 638 compatible = "fsl,anatop-regulator"; 639 regulator-name = "vdd3p0"; 640 regulator-min-microvolt = <2800000>; 641 regulator-max-microvolt = <3150000>; 642 regulator-always-on; 643 anatop-reg-offset = <0x120>; 644 anatop-vol-bit-shift = <8>; 645 anatop-vol-bit-width = <5>; 646 anatop-min-bit-val = <0>; 647 anatop-min-voltage = <2625000>; 648 anatop-max-voltage = <3400000>; 649 anatop-enable-bit = <0>; 650 }; 651 652 reg_vdd2p5: regulator-2p5 { 653 compatible = "fsl,anatop-regulator"; 654 regulator-name = "vdd2p5"; 655 regulator-min-microvolt = <2250000>; 656 regulator-max-microvolt = <2750000>; 657 regulator-always-on; 658 anatop-reg-offset = <0x130>; 659 anatop-vol-bit-shift = <8>; 660 anatop-vol-bit-width = <5>; 661 anatop-min-bit-val = <0>; 662 anatop-min-voltage = <2100000>; 663 anatop-max-voltage = <2875000>; 664 anatop-enable-bit = <0>; 665 }; 666 667 reg_arm: regulator-vddcore { 668 compatible = "fsl,anatop-regulator"; 669 regulator-name = "vddarm"; 670 regulator-min-microvolt = <725000>; 671 regulator-max-microvolt = <1450000>; 672 regulator-always-on; 673 anatop-reg-offset = <0x140>; 674 anatop-vol-bit-shift = <0>; 675 anatop-vol-bit-width = <5>; 676 anatop-delay-reg-offset = <0x170>; 677 anatop-delay-bit-shift = <24>; 678 anatop-delay-bit-width = <2>; 679 anatop-min-bit-val = <1>; 680 anatop-min-voltage = <725000>; 681 anatop-max-voltage = <1450000>; 682 }; 683 684 reg_pcie: regulator-vddpcie { 685 compatible = "fsl,anatop-regulator"; 686 regulator-name = "vddpcie"; 687 regulator-min-microvolt = <725000>; 688 regulator-max-microvolt = <1450000>; 689 anatop-reg-offset = <0x140>; 690 anatop-vol-bit-shift = <9>; 691 anatop-vol-bit-width = <5>; 692 anatop-delay-reg-offset = <0x170>; 693 anatop-delay-bit-shift = <26>; 694 anatop-delay-bit-width = <2>; 695 anatop-min-bit-val = <1>; 696 anatop-min-voltage = <725000>; 697 anatop-max-voltage = <1450000>; 698 }; 699 700 reg_soc: regulator-vddsoc { 701 compatible = "fsl,anatop-regulator"; 702 regulator-name = "vddsoc"; 703 regulator-min-microvolt = <725000>; 704 regulator-max-microvolt = <1450000>; 705 regulator-always-on; 706 anatop-reg-offset = <0x140>; 707 anatop-vol-bit-shift = <18>; 708 anatop-vol-bit-width = <5>; 709 anatop-delay-reg-offset = <0x170>; 710 anatop-delay-bit-shift = <28>; 711 anatop-delay-bit-width = <2>; 712 anatop-min-bit-val = <1>; 713 anatop-min-voltage = <725000>; 714 anatop-max-voltage = <1450000>; 715 }; 716 717 tempmon: tempmon { 718 compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon"; 719 interrupt-parent = <&gpc>; 720 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 721 fsl,tempmon = <&anatop>; 722 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; 723 nvmem-cell-names = "calib", "temp_grade"; 724 clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>; 725 }; 726 }; 727 728 usbphy1: usbphy@20c9000 { 729 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy"; 730 reg = <0x020c9000 0x1000>; 731 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 732 clocks = <&clks IMX6SX_CLK_USBPHY1>; 733 fsl,anatop = <&anatop>; 734 }; 735 736 usbphy2: usbphy@20ca000 { 737 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy"; 738 reg = <0x020ca000 0x1000>; 739 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 740 clocks = <&clks IMX6SX_CLK_USBPHY2>; 741 fsl,anatop = <&anatop>; 742 }; 743 744 snvs: snvs@20cc000 { 745 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; 746 reg = <0x020cc000 0x4000>; 747 748 snvs_rtc: snvs-rtc-lp { 749 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 750 regmap = <&snvs>; 751 offset = <0x34>; 752 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 753 }; 754 755 snvs_poweroff: snvs-poweroff { 756 compatible = "syscon-poweroff"; 757 regmap = <&snvs>; 758 offset = <0x38>; 759 value = <0x60>; 760 mask = <0x60>; 761 status = "disabled"; 762 }; 763 764 snvs_pwrkey: snvs-powerkey { 765 compatible = "fsl,sec-v4.0-pwrkey"; 766 regmap = <&snvs>; 767 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 768 linux,keycode = <KEY_POWER>; 769 wakeup-source; 770 status = "disabled"; 771 }; 772 }; 773 774 epit1: epit@20d0000 { 775 reg = <0x020d0000 0x4000>; 776 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 777 }; 778 779 epit2: epit@20d4000 { 780 reg = <0x020d4000 0x4000>; 781 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 782 }; 783 784 src: reset-controller@20d8000 { 785 compatible = "fsl,imx6sx-src", "fsl,imx51-src"; 786 reg = <0x020d8000 0x4000>; 787 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 788 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 789 #reset-cells = <1>; 790 }; 791 792 gpc: gpc@20dc000 { 793 compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc"; 794 reg = <0x020dc000 0x4000>; 795 interrupt-controller; 796 #interrupt-cells = <3>; 797 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 798 interrupt-parent = <&intc>; 799 clocks = <&clks IMX6SX_CLK_IPG>; 800 clock-names = "ipg"; 801 802 pgc { 803 #address-cells = <1>; 804 #size-cells = <0>; 805 806 power-domain@0 { 807 reg = <0>; 808 #power-domain-cells = <0>; 809 }; 810 811 pd_pu: power-domain@1 { 812 reg = <1>; 813 #power-domain-cells = <0>; 814 power-supply = <®_soc>; 815 clocks = <&clks IMX6SX_CLK_GPU>; 816 }; 817 818 pd_disp: power-domain@2 { 819 reg = <2>; 820 #power-domain-cells = <0>; 821 clocks = <&clks IMX6SX_CLK_PXP_AXI>, 822 <&clks IMX6SX_CLK_DISPLAY_AXI>, 823 <&clks IMX6SX_CLK_LCDIF1_PIX>, 824 <&clks IMX6SX_CLK_LCDIF_APB>, 825 <&clks IMX6SX_CLK_LCDIF2_PIX>, 826 <&clks IMX6SX_CLK_CSI>, 827 <&clks IMX6SX_CLK_VADC>; 828 }; 829 830 pd_pci: power-domain@3 { 831 reg = <3>; 832 #power-domain-cells = <0>; 833 power-supply = <®_pcie>; 834 }; 835 }; 836 }; 837 838 iomuxc: pinctrl@20e0000 { 839 compatible = "fsl,imx6sx-iomuxc"; 840 reg = <0x020e0000 0x4000>; 841 }; 842 843 gpr: syscon@20e4000 { 844 compatible = "fsl,imx6sx-iomuxc-gpr", 845 "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd"; 846 #address-cells = <1>; 847 #size-cells = <1>; 848 reg = <0x020e4000 0x4000>; 849 850 lvds_bridge: bridge@18 { 851 compatible = "fsl,imx6sx-ldb"; 852 reg = <0x18 0x4>; 853 clocks = <&clks IMX6SX_CLK_LDB_DI0>; 854 clock-names = "ldb"; 855 status = "disabled"; 856 857 ports { 858 #address-cells = <1>; 859 #size-cells = <0>; 860 861 port@0 { 862 reg = <0>; 863 864 ldb_from_lcdif1: endpoint { 865 }; 866 }; 867 868 port@1 { 869 reg = <1>; 870 871 ldb_lvds_ch0: endpoint { 872 }; 873 }; 874 }; 875 }; 876 }; 877 878 sdma: dma-controller@20ec000 { 879 compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma"; 880 reg = <0x020ec000 0x4000>; 881 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 882 clocks = <&clks IMX6SX_CLK_IPG>, 883 <&clks IMX6SX_CLK_SDMA>; 884 clock-names = "ipg", "ahb"; 885 #dma-cells = <3>; 886 /* imx6sx reuses imx6q sdma firmware */ 887 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; 888 }; 889 }; 890 891 aips2: bus@2100000 { 892 compatible = "fsl,aips-bus", "simple-bus"; 893 #address-cells = <1>; 894 #size-cells = <1>; 895 reg = <0x02100000 0x100000>; 896 ranges; 897 898 crypto: crypto@2100000 { 899 compatible = "fsl,sec-v4.0"; 900 #address-cells = <1>; 901 #size-cells = <1>; 902 reg = <0x2100000 0x10000>; 903 ranges = <0 0x2100000 0x10000>; 904 interrupt-parent = <&intc>; 905 clocks = <&clks IMX6SX_CLK_CAAM_MEM>, 906 <&clks IMX6SX_CLK_CAAM_ACLK>, 907 <&clks IMX6SX_CLK_CAAM_IPG>, 908 <&clks IMX6SX_CLK_EIM_SLOW>; 909 clock-names = "mem", "aclk", "ipg", "emi_slow"; 910 911 sec_jr0: jr@1000 { 912 compatible = "fsl,sec-v4.0-job-ring"; 913 reg = <0x1000 0x1000>; 914 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 915 }; 916 917 sec_jr1: jr@2000 { 918 compatible = "fsl,sec-v4.0-job-ring"; 919 reg = <0x2000 0x1000>; 920 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 921 }; 922 }; 923 924 usbotg1: usb@2184000 { 925 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; 926 reg = <0x02184000 0x200>; 927 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 928 clocks = <&clks IMX6SX_CLK_USBOH3>; 929 fsl,usbphy = <&usbphy1>; 930 fsl,usbmisc = <&usbmisc 0>; 931 ahb-burst-config = <0x0>; 932 tx-burst-size-dword = <0x10>; 933 rx-burst-size-dword = <0x10>; 934 status = "disabled"; 935 }; 936 937 usbotg2: usb@2184200 { 938 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; 939 reg = <0x02184200 0x200>; 940 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 941 clocks = <&clks IMX6SX_CLK_USBOH3>; 942 fsl,usbphy = <&usbphy2>; 943 fsl,usbmisc = <&usbmisc 1>; 944 ahb-burst-config = <0x0>; 945 tx-burst-size-dword = <0x10>; 946 rx-burst-size-dword = <0x10>; 947 status = "disabled"; 948 }; 949 950 usbh: usb@2184400 { 951 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; 952 reg = <0x02184400 0x200>; 953 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 954 clocks = <&clks IMX6SX_CLK_USBOH3>; 955 fsl,usbphy = <&usbphynop1>; 956 fsl,usbmisc = <&usbmisc 2>; 957 phy_type = "hsic"; 958 dr_mode = "host"; 959 ahb-burst-config = <0x0>; 960 tx-burst-size-dword = <0x10>; 961 rx-burst-size-dword = <0x10>; 962 status = "disabled"; 963 }; 964 965 usbmisc: usbmisc@2184800 { 966 #index-cells = <1>; 967 compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc"; 968 reg = <0x02184800 0x200>; 969 clocks = <&clks IMX6SX_CLK_USBOH3>; 970 }; 971 972 fec1: ethernet@2188000 { 973 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec"; 974 reg = <0x02188000 0x4000>; 975 interrupt-names = "int0", "pps"; 976 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 977 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 978 clocks = <&clks IMX6SX_CLK_ENET>, 979 <&clks IMX6SX_CLK_ENET_AHB>, 980 <&clks IMX6SX_CLK_ENET_PTP>, 981 <&clks IMX6SX_CLK_ENET_REF>, 982 <&clks IMX6SX_CLK_ENET_PTP>; 983 clock-names = "ipg", "ahb", "ptp", 984 "enet_clk_ref", "enet_out"; 985 fsl,num-tx-queues = <3>; 986 fsl,num-rx-queues = <3>; 987 fsl,stop-mode = <&gpr 0x10 3>; 988 status = "disabled"; 989 }; 990 991 mlb: mlb@218c000 { 992 reg = <0x0218c000 0x4000>; 993 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 994 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 995 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 996 clocks = <&clks IMX6SX_CLK_MLB>; 997 status = "disabled"; 998 }; 999 1000 usdhc1: mmc@2190000 { 1001 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; 1002 reg = <0x02190000 0x4000>; 1003 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1004 clocks = <&clks IMX6SX_CLK_USDHC1>, 1005 <&clks IMX6SX_CLK_USDHC1>, 1006 <&clks IMX6SX_CLK_USDHC1>; 1007 clock-names = "ipg", "ahb", "per"; 1008 bus-width = <4>; 1009 fsl,tuning-start-tap = <20>; 1010 fsl,tuning-step = <2>; 1011 status = "disabled"; 1012 }; 1013 1014 usdhc2: mmc@2194000 { 1015 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; 1016 reg = <0x02194000 0x4000>; 1017 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1018 clocks = <&clks IMX6SX_CLK_USDHC2>, 1019 <&clks IMX6SX_CLK_USDHC2>, 1020 <&clks IMX6SX_CLK_USDHC2>; 1021 clock-names = "ipg", "ahb", "per"; 1022 bus-width = <4>; 1023 fsl,tuning-start-tap = <20>; 1024 fsl,tuning-step = <2>; 1025 status = "disabled"; 1026 }; 1027 1028 usdhc3: mmc@2198000 { 1029 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; 1030 reg = <0x02198000 0x4000>; 1031 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1032 clocks = <&clks IMX6SX_CLK_USDHC3>, 1033 <&clks IMX6SX_CLK_USDHC3>, 1034 <&clks IMX6SX_CLK_USDHC3>; 1035 clock-names = "ipg", "ahb", "per"; 1036 bus-width = <4>; 1037 fsl,tuning-start-tap = <20>; 1038 fsl,tuning-step = <2>; 1039 status = "disabled"; 1040 }; 1041 1042 usdhc4: mmc@219c000 { 1043 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; 1044 reg = <0x0219c000 0x4000>; 1045 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1046 clocks = <&clks IMX6SX_CLK_USDHC4>, 1047 <&clks IMX6SX_CLK_USDHC4>, 1048 <&clks IMX6SX_CLK_USDHC4>; 1049 clock-names = "ipg", "ahb", "per"; 1050 bus-width = <4>; 1051 status = "disabled"; 1052 }; 1053 1054 i2c1: i2c@21a0000 { 1055 #address-cells = <1>; 1056 #size-cells = <0>; 1057 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; 1058 reg = <0x021a0000 0x4000>; 1059 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1060 clocks = <&clks IMX6SX_CLK_I2C1>; 1061 status = "disabled"; 1062 }; 1063 1064 i2c2: i2c@21a4000 { 1065 #address-cells = <1>; 1066 #size-cells = <0>; 1067 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; 1068 reg = <0x021a4000 0x4000>; 1069 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1070 clocks = <&clks IMX6SX_CLK_I2C2>; 1071 status = "disabled"; 1072 }; 1073 1074 i2c3: i2c@21a8000 { 1075 #address-cells = <1>; 1076 #size-cells = <0>; 1077 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; 1078 reg = <0x021a8000 0x4000>; 1079 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1080 clocks = <&clks IMX6SX_CLK_I2C3>; 1081 status = "disabled"; 1082 }; 1083 1084 memory-controller@21b0000 { 1085 compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc"; 1086 reg = <0x021b0000 0x4000>; 1087 clocks = <&clks IMX6SX_CLK_MMDC_P0_IPG>; 1088 }; 1089 1090 fec2: ethernet@21b4000 { 1091 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec"; 1092 reg = <0x021b4000 0x4000>; 1093 interrupt-names = "int0", "pps"; 1094 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1095 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1096 clocks = <&clks IMX6SX_CLK_ENET>, 1097 <&clks IMX6SX_CLK_ENET_AHB>, 1098 <&clks IMX6SX_CLK_ENET_PTP>, 1099 <&clks IMX6SX_CLK_ENET2_REF_125M>, 1100 <&clks IMX6SX_CLK_ENET_PTP>; 1101 clock-names = "ipg", "ahb", "ptp", 1102 "enet_clk_ref", "enet_out"; 1103 fsl,stop-mode = <&gpr 0x10 4>; 1104 status = "disabled"; 1105 }; 1106 1107 weim: memory-controller@21b8000 { 1108 #address-cells = <2>; 1109 #size-cells = <1>; 1110 compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim"; 1111 reg = <0x021b8000 0x4000>; 1112 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1113 clocks = <&clks IMX6SX_CLK_EIM_SLOW>; 1114 fsl,weim-cs-gpr = <&gpr>; 1115 status = "disabled"; 1116 }; 1117 1118 ocotp: efuse@21bc000 { 1119 #address-cells = <1>; 1120 #size-cells = <1>; 1121 compatible = "fsl,imx6sx-ocotp", "syscon"; 1122 reg = <0x021bc000 0x4000>; 1123 clocks = <&clks IMX6SX_CLK_OCOTP>; 1124 1125 cpu_speed_grade: speed-grade@10 { 1126 reg = <0x10 4>; 1127 }; 1128 1129 tempmon_calib: calib@38 { 1130 reg = <0x38 4>; 1131 }; 1132 1133 tempmon_temp_grade: temp-grade@20 { 1134 reg = <0x20 4>; 1135 }; 1136 }; 1137 1138 sai1: sai@21d4000 { 1139 compatible = "fsl,imx6sx-sai"; 1140 reg = <0x021d4000 0x4000>; 1141 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1142 clocks = <&clks IMX6SX_CLK_SAI1_IPG>, 1143 <&clks IMX6SX_CLK_SAI1>, 1144 <&clks 0>, <&clks 0>; 1145 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 1146 dma-names = "rx", "tx"; 1147 dmas = <&sdma 31 24 0>, <&sdma 32 24 0>; 1148 status = "disabled"; 1149 }; 1150 1151 audmux: audmux@21d8000 { 1152 compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux"; 1153 reg = <0x021d8000 0x4000>; 1154 status = "disabled"; 1155 }; 1156 1157 sai2: sai@21dc000 { 1158 compatible = "fsl,imx6sx-sai"; 1159 reg = <0x021dc000 0x4000>; 1160 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1161 clocks = <&clks IMX6SX_CLK_SAI2_IPG>, 1162 <&clks IMX6SX_CLK_SAI2>, 1163 <&clks 0>, <&clks 0>; 1164 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 1165 dma-names = "rx", "tx"; 1166 dmas = <&sdma 33 24 0>, <&sdma 34 24 0>; 1167 status = "disabled"; 1168 }; 1169 1170 qspi1: spi@21e0000 { 1171 #address-cells = <1>; 1172 #size-cells = <0>; 1173 compatible = "fsl,imx6sx-qspi"; 1174 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>; 1175 reg-names = "QuadSPI", "QuadSPI-memory"; 1176 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1177 clocks = <&clks IMX6SX_CLK_QSPI1>, 1178 <&clks IMX6SX_CLK_QSPI1>; 1179 clock-names = "qspi_en", "qspi"; 1180 status = "disabled"; 1181 }; 1182 1183 qspi2: spi@21e4000 { 1184 #address-cells = <1>; 1185 #size-cells = <0>; 1186 compatible = "fsl,imx6sx-qspi"; 1187 reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>; 1188 reg-names = "QuadSPI", "QuadSPI-memory"; 1189 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 1190 clocks = <&clks IMX6SX_CLK_QSPI2>, 1191 <&clks IMX6SX_CLK_QSPI2>; 1192 clock-names = "qspi_en", "qspi"; 1193 status = "disabled"; 1194 }; 1195 1196 uart2: serial@21e8000 { 1197 compatible = "fsl,imx6sx-uart", 1198 "fsl,imx6q-uart", "fsl,imx21-uart"; 1199 reg = <0x021e8000 0x4000>; 1200 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 1201 clocks = <&clks IMX6SX_CLK_UART_IPG>, 1202 <&clks IMX6SX_CLK_UART_SERIAL>; 1203 clock-names = "ipg", "per"; 1204 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; 1205 dma-names = "rx", "tx"; 1206 status = "disabled"; 1207 }; 1208 1209 uart3: serial@21ec000 { 1210 compatible = "fsl,imx6sx-uart", 1211 "fsl,imx6q-uart", "fsl,imx21-uart"; 1212 reg = <0x021ec000 0x4000>; 1213 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 1214 clocks = <&clks IMX6SX_CLK_UART_IPG>, 1215 <&clks IMX6SX_CLK_UART_SERIAL>; 1216 clock-names = "ipg", "per"; 1217 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; 1218 dma-names = "rx", "tx"; 1219 status = "disabled"; 1220 }; 1221 1222 uart4: serial@21f0000 { 1223 compatible = "fsl,imx6sx-uart", 1224 "fsl,imx6q-uart", "fsl,imx21-uart"; 1225 reg = <0x021f0000 0x4000>; 1226 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1227 clocks = <&clks IMX6SX_CLK_UART_IPG>, 1228 <&clks IMX6SX_CLK_UART_SERIAL>; 1229 clock-names = "ipg", "per"; 1230 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; 1231 dma-names = "rx", "tx"; 1232 status = "disabled"; 1233 }; 1234 1235 uart5: serial@21f4000 { 1236 compatible = "fsl,imx6sx-uart", 1237 "fsl,imx6q-uart", "fsl,imx21-uart"; 1238 reg = <0x021f4000 0x4000>; 1239 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1240 clocks = <&clks IMX6SX_CLK_UART_IPG>, 1241 <&clks IMX6SX_CLK_UART_SERIAL>; 1242 clock-names = "ipg", "per"; 1243 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; 1244 dma-names = "rx", "tx"; 1245 status = "disabled"; 1246 }; 1247 1248 i2c4: i2c@21f8000 { 1249 #address-cells = <1>; 1250 #size-cells = <0>; 1251 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; 1252 reg = <0x021f8000 0x4000>; 1253 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1254 clocks = <&clks IMX6SX_CLK_I2C4>; 1255 status = "disabled"; 1256 }; 1257 }; 1258 1259 aips3: bus@2200000 { 1260 compatible = "fsl,aips-bus", "simple-bus"; 1261 #address-cells = <1>; 1262 #size-cells = <1>; 1263 reg = <0x02200000 0x100000>; 1264 ranges; 1265 1266 spba-bus@2240000 { 1267 compatible = "fsl,spba-bus", "simple-bus"; 1268 #address-cells = <1>; 1269 #size-cells = <1>; 1270 reg = <0x02240000 0x40000>; 1271 ranges; 1272 1273 csi1: csi@2214000 { 1274 reg = <0x02214000 0x4000>; 1275 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1276 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>, 1277 <&clks IMX6SX_CLK_CSI>, 1278 <&clks IMX6SX_CLK_DCIC1>; 1279 clock-names = "disp-axi", "csi_mclk", "dcic"; 1280 status = "disabled"; 1281 }; 1282 1283 pxp: pxp@2218000 { 1284 compatible = "fsl,imx6sx-pxp", "fsl,imx6ull-pxp"; 1285 reg = <0x02218000 0x4000>; 1286 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1287 clocks = <&clks IMX6SX_CLK_PXP_AXI>; 1288 clock-names = "axi"; 1289 power-domains = <&pd_disp>; 1290 status = "disabled"; 1291 }; 1292 1293 csi2: csi@221c000 { 1294 reg = <0x0221c000 0x4000>; 1295 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1296 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>, 1297 <&clks IMX6SX_CLK_CSI>, 1298 <&clks IMX6SX_CLK_DCIC2>; 1299 clock-names = "disp-axi", "csi_mclk", "dcic"; 1300 status = "disabled"; 1301 }; 1302 1303 lcdif1: lcdif@2220000 { 1304 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif"; 1305 reg = <0x02220000 0x4000>; 1306 interrupts = <GIC_SPI 5 IRQ_TYPE_EDGE_RISING>; 1307 clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>, 1308 <&clks IMX6SX_CLK_LCDIF_APB>, 1309 <&clks IMX6SX_CLK_DISPLAY_AXI>; 1310 clock-names = "pix", "axi", "disp_axi"; 1311 assigned-clocks = <&clks IMX6SX_CLK_LCDIF1_PRE_SEL>, 1312 <&clks IMX6SX_CLK_LCDIF1_SEL>; 1313 assigned-clock-parents = <&clks IMX6SX_CLK_PLL5_VIDEO_DIV>, 1314 <&clks IMX6SX_CLK_LCDIF1_PODF>; 1315 power-domains = <&pd_disp>; 1316 status = "disabled"; 1317 1318 port { 1319 lcdif1_to_ldb: endpoint { 1320 }; 1321 }; 1322 }; 1323 1324 lcdif2: lcdif@2224000 { 1325 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif"; 1326 reg = <0x02224000 0x4000>; 1327 interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>; 1328 clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>, 1329 <&clks IMX6SX_CLK_LCDIF_APB>, 1330 <&clks IMX6SX_CLK_DISPLAY_AXI>; 1331 clock-names = "pix", "axi", "disp_axi"; 1332 power-domains = <&pd_disp>; 1333 status = "disabled"; 1334 }; 1335 1336 vadc: vadc@2228000 { 1337 reg = <0x02228000 0x4000>, <0x0222c000 0x4000>; 1338 reg-names = "vadc-vafe", "vadc-vdec"; 1339 clocks = <&clks IMX6SX_CLK_VADC>, 1340 <&clks IMX6SX_CLK_CSI>; 1341 clock-names = "vadc", "csi"; 1342 power-domains = <&pd_disp>; 1343 status = "disabled"; 1344 }; 1345 }; 1346 1347 adc1: adc@2280000 { 1348 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc"; 1349 reg = <0x02280000 0x4000>; 1350 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1351 clocks = <&clks IMX6SX_CLK_IPG>; 1352 clock-names = "adc"; 1353 fsl,adck-max-frequency = <30000000>, <40000000>, 1354 <20000000>; 1355 status = "disabled"; 1356 }; 1357 1358 adc2: adc@2284000 { 1359 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc"; 1360 reg = <0x02284000 0x4000>; 1361 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1362 clocks = <&clks IMX6SX_CLK_IPG>; 1363 clock-names = "adc"; 1364 fsl,adck-max-frequency = <30000000>, <40000000>, 1365 <20000000>; 1366 status = "disabled"; 1367 }; 1368 1369 wdog3: watchdog@2288000 { 1370 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; 1371 reg = <0x02288000 0x4000>; 1372 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1373 clocks = <&clks IMX6SX_CLK_IPG>; 1374 status = "disabled"; 1375 }; 1376 1377 ecspi5: spi@228c000 { 1378 #address-cells = <1>; 1379 #size-cells = <0>; 1380 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; 1381 reg = <0x0228c000 0x4000>; 1382 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 1383 clocks = <&clks IMX6SX_CLK_ECSPI5>, 1384 <&clks IMX6SX_CLK_ECSPI5>; 1385 clock-names = "ipg", "per"; 1386 status = "disabled"; 1387 }; 1388 1389 uart6: serial@22a0000 { 1390 compatible = "fsl,imx6sx-uart", 1391 "fsl,imx6q-uart", "fsl,imx21-uart"; 1392 reg = <0x022a0000 0x4000>; 1393 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1394 clocks = <&clks IMX6SX_CLK_UART_IPG>, 1395 <&clks IMX6SX_CLK_UART_SERIAL>; 1396 clock-names = "ipg", "per"; 1397 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>; 1398 dma-names = "rx", "tx"; 1399 status = "disabled"; 1400 }; 1401 1402 pwm5: pwm@22a4000 { 1403 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 1404 reg = <0x022a4000 0x4000>; 1405 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1406 clocks = <&clks IMX6SX_CLK_PWM5>, 1407 <&clks IMX6SX_CLK_PWM5>; 1408 clock-names = "ipg", "per"; 1409 #pwm-cells = <3>; 1410 }; 1411 1412 pwm6: pwm@22a8000 { 1413 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 1414 reg = <0x022a8000 0x4000>; 1415 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1416 clocks = <&clks IMX6SX_CLK_PWM6>, 1417 <&clks IMX6SX_CLK_PWM6>; 1418 clock-names = "ipg", "per"; 1419 #pwm-cells = <3>; 1420 }; 1421 1422 pwm7: pwm@22ac000 { 1423 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 1424 reg = <0x022ac000 0x4000>; 1425 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1426 clocks = <&clks IMX6SX_CLK_PWM7>, 1427 <&clks IMX6SX_CLK_PWM7>; 1428 clock-names = "ipg", "per"; 1429 #pwm-cells = <3>; 1430 }; 1431 1432 pwm8: pwm@22b0000 { 1433 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 1434 reg = <0x022b0000 0x4000>; 1435 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1436 clocks = <&clks IMX6SX_CLK_PWM8>, 1437 <&clks IMX6SX_CLK_PWM8>; 1438 clock-names = "ipg", "per"; 1439 #pwm-cells = <3>; 1440 }; 1441 }; 1442 1443 pcie: pcie@8ffc000 { 1444 compatible = "fsl,imx6sx-pcie"; 1445 reg = <0x08ffc000 0x04000>, <0x08f00000 0x80000>; 1446 reg-names = "dbi", "config"; 1447 #address-cells = <3>; 1448 #size-cells = <2>; 1449 device_type = "pci"; 1450 bus-range = <0x00 0xff>; 1451 ranges = <0x81000000 0 0 0x08f80000 0 0x00010000>, /* downstream I/O */ 1452 <0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */ 1453 num-lanes = <1>; 1454 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 1455 interrupt-names = "msi"; 1456 #interrupt-cells = <1>; 1457 interrupt-map-mask = <0 0 0 0x7>; 1458 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1459 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1460 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1461 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 1462 clocks = <&clks IMX6SX_CLK_PCIE_AXI>, 1463 <&clks IMX6SX_CLK_LVDS1_OUT>, 1464 <&clks IMX6SX_CLK_PCIE_REF_125M>, 1465 <&clks IMX6SX_CLK_DISPLAY_AXI>; 1466 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi"; 1467 power-domains = <&pd_disp>, <&pd_pci>; 1468 power-domain-names = "pcie", "pcie_phy"; 1469 status = "disabled"; 1470 }; 1471 }; 1472}; 1473