xref: /linux/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi (revision a1ff5a7d78a036d6c2178ee5acd6ba4946243800)
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
3
4#include <dt-bindings/interrupt-controller/arm-gic.h>
5#include <dt-bindings/clock/sun50i-h6-ccu.h>
6#include <dt-bindings/clock/sun50i-h6-r-ccu.h>
7#include <dt-bindings/clock/sun6i-rtc.h>
8#include <dt-bindings/clock/sun8i-de2.h>
9#include <dt-bindings/clock/sun8i-tcon-top.h>
10#include <dt-bindings/reset/sun50i-h6-ccu.h>
11#include <dt-bindings/reset/sun50i-h6-r-ccu.h>
12#include <dt-bindings/reset/sun8i-de2.h>
13#include <dt-bindings/thermal/thermal.h>
14
15/ {
16	interrupt-parent = <&gic>;
17	#address-cells = <1>;
18	#size-cells = <1>;
19
20	cpus {
21		#address-cells = <1>;
22		#size-cells = <0>;
23
24		cpu0: cpu@0 {
25			compatible = "arm,cortex-a53";
26			device_type = "cpu";
27			reg = <0>;
28			enable-method = "psci";
29			clocks = <&ccu CLK_CPUX>;
30			clock-latency-ns = <244144>; /* 8 32k periods */
31			#cooling-cells = <2>;
32			i-cache-size = <0x8000>;
33			i-cache-line-size = <64>;
34			i-cache-sets = <256>;
35			d-cache-size = <0x8000>;
36			d-cache-line-size = <64>;
37			d-cache-sets = <128>;
38			next-level-cache = <&l2_cache>;
39		};
40
41		cpu1: cpu@1 {
42			compatible = "arm,cortex-a53";
43			device_type = "cpu";
44			reg = <1>;
45			enable-method = "psci";
46			clocks = <&ccu CLK_CPUX>;
47			clock-latency-ns = <244144>; /* 8 32k periods */
48			#cooling-cells = <2>;
49			i-cache-size = <0x8000>;
50			i-cache-line-size = <64>;
51			i-cache-sets = <256>;
52			d-cache-size = <0x8000>;
53			d-cache-line-size = <64>;
54			d-cache-sets = <128>;
55			next-level-cache = <&l2_cache>;
56		};
57
58		cpu2: cpu@2 {
59			compatible = "arm,cortex-a53";
60			device_type = "cpu";
61			reg = <2>;
62			enable-method = "psci";
63			clocks = <&ccu CLK_CPUX>;
64			clock-latency-ns = <244144>; /* 8 32k periods */
65			#cooling-cells = <2>;
66			i-cache-size = <0x8000>;
67			i-cache-line-size = <64>;
68			i-cache-sets = <256>;
69			d-cache-size = <0x8000>;
70			d-cache-line-size = <64>;
71			d-cache-sets = <128>;
72			next-level-cache = <&l2_cache>;
73		};
74
75		cpu3: cpu@3 {
76			compatible = "arm,cortex-a53";
77			device_type = "cpu";
78			reg = <3>;
79			enable-method = "psci";
80			clocks = <&ccu CLK_CPUX>;
81			clock-latency-ns = <244144>; /* 8 32k periods */
82			#cooling-cells = <2>;
83			i-cache-size = <0x8000>;
84			i-cache-line-size = <64>;
85			i-cache-sets = <256>;
86			d-cache-size = <0x8000>;
87			d-cache-line-size = <64>;
88			d-cache-sets = <128>;
89			next-level-cache = <&l2_cache>;
90		};
91
92		l2_cache: l2-cache {
93			compatible = "cache";
94			cache-level = <2>;
95			cache-unified;
96			cache-size = <0x80000>;
97			cache-line-size = <64>;
98			cache-sets = <512>;
99		};
100	};
101
102	de: display-engine {
103		compatible = "allwinner,sun50i-h6-display-engine";
104		allwinner,pipelines = <&mixer0>;
105		status = "disabled";
106	};
107
108	osc24M: osc24M-clk {
109		#clock-cells = <0>;
110		compatible = "fixed-clock";
111		clock-frequency = <24000000>;
112		clock-output-names = "osc24M";
113	};
114
115	pmu {
116		compatible = "arm,cortex-a53-pmu";
117		interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
118			     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
119			     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
120			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
121		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
122	};
123
124	psci {
125		compatible = "arm,psci-0.2";
126		method = "smc";
127	};
128
129	timer {
130		compatible = "arm,armv8-timer";
131		arm,no-tick-in-suspend;
132		interrupts = <GIC_PPI 13
133			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
134			     <GIC_PPI 14
135			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
136			     <GIC_PPI 11
137			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
138			     <GIC_PPI 10
139			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
140	};
141
142	soc {
143		compatible = "simple-bus";
144		#address-cells = <1>;
145		#size-cells = <1>;
146		ranges;
147
148		bus@1000000 {
149			compatible = "allwinner,sun50i-h6-de3",
150				     "allwinner,sun50i-a64-de2";
151			reg = <0x1000000 0x400000>;
152			allwinner,sram = <&de2_sram 1>;
153			#address-cells = <1>;
154			#size-cells = <1>;
155			ranges = <0 0x1000000 0x400000>;
156
157			display_clocks: clock@0 {
158				compatible = "allwinner,sun50i-h6-de3-clk";
159				reg = <0x0 0x10000>;
160				clocks = <&ccu CLK_BUS_DE>,
161					 <&ccu CLK_DE>;
162				clock-names = "bus",
163					      "mod";
164				resets = <&ccu RST_BUS_DE>;
165				#clock-cells = <1>;
166				#reset-cells = <1>;
167			};
168
169			mixer0: mixer@100000 {
170				compatible = "allwinner,sun50i-h6-de3-mixer-0";
171				reg = <0x100000 0x100000>;
172				clocks = <&display_clocks CLK_BUS_MIXER0>,
173					 <&display_clocks CLK_MIXER0>;
174				clock-names = "bus",
175					      "mod";
176				resets = <&display_clocks RST_MIXER0>;
177				iommus = <&iommu 0>;
178
179				ports {
180					#address-cells = <1>;
181					#size-cells = <0>;
182
183					mixer0_out: port@1 {
184						reg = <1>;
185
186						mixer0_out_tcon_top_mixer0: endpoint {
187							remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
188						};
189					};
190				};
191			};
192		};
193
194		video-codec-g2@1c00000 {
195			compatible = "allwinner,sun50i-h6-vpu-g2";
196			reg = <0x01c00000 0x1000>;
197			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
198			clocks = <&ccu CLK_BUS_VP9>, <&ccu CLK_VP9>;
199			clock-names = "bus", "mod";
200			resets = <&ccu RST_BUS_VP9>;
201			iommus = <&iommu 5>;
202		};
203
204		video-codec@1c0e000 {
205			compatible = "allwinner,sun50i-h6-video-engine";
206			reg = <0x01c0e000 0x2000>;
207			clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
208				 <&ccu CLK_MBUS_VE>;
209			clock-names = "ahb", "mod", "ram";
210			resets = <&ccu RST_BUS_VE>;
211			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
212			allwinner,sram = <&ve_sram 1>;
213			iommus = <&iommu 3>;
214		};
215
216		gpu: gpu@1800000 {
217			compatible = "allwinner,sun50i-h6-mali",
218				     "arm,mali-t720";
219			reg = <0x01800000 0x4000>;
220			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
221				     <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
222				     <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
223			interrupt-names = "job", "mmu", "gpu";
224			clocks = <&ccu CLK_GPU>, <&ccu CLK_BUS_GPU>;
225			clock-names = "core", "bus";
226			resets = <&ccu RST_BUS_GPU>;
227			#cooling-cells = <2>;
228			status = "disabled";
229		};
230
231		crypto: crypto@1904000 {
232			compatible = "allwinner,sun50i-h6-crypto";
233			reg = <0x01904000 0x1000>;
234			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
235			clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>, <&ccu CLK_MBUS_CE>;
236			clock-names = "bus", "mod", "ram";
237			resets = <&ccu RST_BUS_CE>;
238		};
239
240		syscon: syscon@3000000 {
241			compatible = "allwinner,sun50i-h6-system-control",
242				     "allwinner,sun50i-a64-system-control";
243			reg = <0x03000000 0x1000>;
244			#address-cells = <1>;
245			#size-cells = <1>;
246			ranges;
247
248			sram_c: sram@28000 {
249				compatible = "mmio-sram";
250				reg = <0x00028000 0x1e000>;
251				#address-cells = <1>;
252				#size-cells = <1>;
253				ranges = <0 0x00028000 0x1e000>;
254
255				de2_sram: sram-section@0 {
256					compatible = "allwinner,sun50i-h6-sram-c",
257						     "allwinner,sun50i-a64-sram-c";
258					reg = <0x0000 0x1e000>;
259				};
260			};
261
262			sram_c1: sram@1a00000 {
263				compatible = "mmio-sram";
264				reg = <0x01a00000 0x200000>;
265				#address-cells = <1>;
266				#size-cells = <1>;
267				ranges = <0 0x01a00000 0x200000>;
268
269				ve_sram: sram-section@0 {
270					compatible = "allwinner,sun50i-h6-sram-c1",
271						     "allwinner,sun4i-a10-sram-c1";
272					reg = <0x000000 0x200000>;
273				};
274			};
275		};
276
277		ccu: clock@3001000 {
278			compatible = "allwinner,sun50i-h6-ccu";
279			reg = <0x03001000 0x1000>;
280			clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>;
281			clock-names = "hosc", "losc", "iosc";
282			#clock-cells = <1>;
283			#reset-cells = <1>;
284		};
285
286		dma: dma-controller@3002000 {
287			compatible = "allwinner,sun50i-h6-dma";
288			reg = <0x03002000 0x1000>;
289			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
290			clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
291			clock-names = "bus", "mbus";
292			dma-channels = <16>;
293			dma-requests = <46>;
294			resets = <&ccu RST_BUS_DMA>;
295			#dma-cells = <1>;
296		};
297
298		msgbox: mailbox@3003000 {
299			compatible = "allwinner,sun50i-h6-msgbox",
300				     "allwinner,sun6i-a31-msgbox";
301			reg = <0x03003000 0x1000>;
302			clocks = <&ccu CLK_BUS_MSGBOX>;
303			resets = <&ccu RST_BUS_MSGBOX>;
304			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
305			#mbox-cells = <1>;
306		};
307
308		sid: efuse@3006000 {
309			compatible = "allwinner,sun50i-h6-sid";
310			reg = <0x03006000 0x400>;
311			#address-cells = <1>;
312			#size-cells = <1>;
313
314			ths_calibration: thermal-sensor-calibration@14 {
315				reg = <0x14 0x8>;
316			};
317
318			cpu_speed_grade: cpu-speed-grade@1c {
319				reg = <0x1c 0x4>;
320			};
321		};
322
323		timer@3009000 {
324			compatible = "allwinner,sun50i-h6-timer",
325				     "allwinner,sun8i-a23-timer";
326			reg = <0x03009000 0xa0>;
327			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
328				     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
329			clocks = <&osc24M>;
330		};
331
332		watchdog: watchdog@30090a0 {
333			compatible = "allwinner,sun50i-h6-wdt",
334				     "allwinner,sun6i-a31-wdt";
335			reg = <0x030090a0 0x20>;
336			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
337			clocks = <&osc24M>;
338			/* Broken on some H6 boards */
339			status = "disabled";
340		};
341
342		pwm: pwm@300a000 {
343			compatible = "allwinner,sun50i-h6-pwm";
344			reg = <0x0300a000 0x400>;
345			clocks = <&osc24M>, <&ccu CLK_BUS_PWM>;
346			clock-names = "mod", "bus";
347			resets = <&ccu RST_BUS_PWM>;
348			#pwm-cells = <3>;
349			status = "disabled";
350		};
351
352		pio: pinctrl@300b000 {
353			compatible = "allwinner,sun50i-h6-pinctrl";
354			reg = <0x0300b000 0x400>;
355			interrupt-parent = <&r_intc>;
356			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
357				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
358				     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
359				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
360			clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc CLK_OSC32K>;
361			clock-names = "apb", "hosc", "losc";
362			gpio-controller;
363			#gpio-cells = <3>;
364			interrupt-controller;
365			#interrupt-cells = <3>;
366
367			ext_rgmii_pins: rgmii-pins {
368				pins = "PD0", "PD1", "PD2", "PD3", "PD4",
369				       "PD5", "PD7", "PD8", "PD9", "PD10",
370				       "PD11", "PD12", "PD13", "PD19", "PD20";
371				function = "emac";
372				drive-strength = <40>;
373			};
374
375			hdmi_pins: hdmi-pins {
376				pins = "PH8", "PH9", "PH10";
377				function = "hdmi";
378			};
379
380			i2c0_pins: i2c0-pins {
381				pins = "PD25", "PD26";
382				function = "i2c0";
383			};
384
385			i2c1_pins: i2c1-pins {
386				pins = "PH5", "PH6";
387				function = "i2c1";
388			};
389
390			i2c2_pins: i2c2-pins {
391				pins = "PD23", "PD24";
392				function = "i2c2";
393			};
394
395			mmc0_pins: mmc0-pins {
396				pins = "PF0", "PF1", "PF2", "PF3",
397				       "PF4", "PF5";
398				function = "mmc0";
399				drive-strength = <30>;
400				bias-pull-up;
401			};
402
403			/omit-if-no-ref/
404			mmc1_pins: mmc1-pins {
405				pins = "PG0", "PG1", "PG2", "PG3",
406				       "PG4", "PG5";
407				function = "mmc1";
408				drive-strength = <30>;
409				bias-pull-up;
410			};
411
412			mmc2_pins: mmc2-pins {
413				pins = "PC1", "PC4", "PC5", "PC6",
414				       "PC7", "PC8", "PC9", "PC10",
415				       "PC11", "PC12", "PC13", "PC14";
416				function = "mmc2";
417				drive-strength = <30>;
418				bias-pull-up;
419			};
420
421			/omit-if-no-ref/
422			spi0_pins: spi0-pins {
423				pins = "PC0", "PC2", "PC3";
424				function = "spi0";
425			};
426
427			/* pin shared with MMC2-CMD (eMMC) */
428			/omit-if-no-ref/
429			spi0_cs_pin: spi0-cs-pin {
430				pins = "PC5";
431				function = "spi0";
432			};
433
434			/omit-if-no-ref/
435			spi1_pins: spi1-pins {
436				pins = "PH4", "PH5", "PH6";
437				function = "spi1";
438			};
439
440			/omit-if-no-ref/
441			spi1_cs_pin: spi1-cs-pin {
442				pins = "PH3";
443				function = "spi1";
444			};
445
446			/omit-if-no-ref/
447			spdif_tx_pin: spdif-tx-pin {
448				pins = "PH7";
449				function = "spdif";
450			};
451
452			uart0_ph_pins: uart0-ph-pins {
453				pins = "PH0", "PH1";
454				function = "uart0";
455			};
456
457			uart1_pins: uart1-pins {
458				pins = "PG6", "PG7";
459				function = "uart1";
460			};
461
462			uart1_rts_cts_pins: uart1-rts-cts-pins {
463				pins = "PG8", "PG9";
464				function = "uart1";
465			};
466		};
467
468		gic: interrupt-controller@3021000 {
469			compatible = "arm,gic-400";
470			reg = <0x03021000 0x1000>,
471			      <0x03022000 0x2000>,
472			      <0x03024000 0x2000>,
473			      <0x03026000 0x2000>;
474			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
475			interrupt-controller;
476			#interrupt-cells = <3>;
477		};
478
479		iommu: iommu@30f0000 {
480			compatible = "allwinner,sun50i-h6-iommu";
481			reg = <0x030f0000 0x10000>;
482			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
483			clocks = <&ccu CLK_BUS_IOMMU>;
484			resets = <&ccu RST_BUS_IOMMU>;
485			#iommu-cells = <1>;
486		};
487
488		mmc0: mmc@4020000 {
489			compatible = "allwinner,sun50i-h6-mmc",
490				     "allwinner,sun50i-a64-mmc";
491			reg = <0x04020000 0x1000>;
492			clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
493			clock-names = "ahb", "mmc";
494			resets = <&ccu RST_BUS_MMC0>;
495			reset-names = "ahb";
496			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
497			pinctrl-names = "default";
498			pinctrl-0 = <&mmc0_pins>;
499			max-frequency = <150000000>;
500			status = "disabled";
501			#address-cells = <1>;
502			#size-cells = <0>;
503		};
504
505		mmc1: mmc@4021000 {
506			compatible = "allwinner,sun50i-h6-mmc",
507				     "allwinner,sun50i-a64-mmc";
508			reg = <0x04021000 0x1000>;
509			clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
510			clock-names = "ahb", "mmc";
511			resets = <&ccu RST_BUS_MMC1>;
512			reset-names = "ahb";
513			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
514			pinctrl-names = "default";
515			pinctrl-0 = <&mmc1_pins>;
516			max-frequency = <150000000>;
517			status = "disabled";
518			#address-cells = <1>;
519			#size-cells = <0>;
520		};
521
522		mmc2: mmc@4022000 {
523			compatible = "allwinner,sun50i-h6-emmc",
524				     "allwinner,sun50i-a64-emmc";
525			reg = <0x04022000 0x1000>;
526			clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
527			clock-names = "ahb", "mmc";
528			resets = <&ccu RST_BUS_MMC2>;
529			reset-names = "ahb";
530			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
531			pinctrl-names = "default";
532			pinctrl-0 = <&mmc2_pins>;
533			max-frequency = <150000000>;
534			status = "disabled";
535			#address-cells = <1>;
536			#size-cells = <0>;
537		};
538
539		uart0: serial@5000000 {
540			compatible = "snps,dw-apb-uart";
541			reg = <0x05000000 0x400>;
542			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
543			reg-shift = <2>;
544			reg-io-width = <4>;
545			clocks = <&ccu CLK_BUS_UART0>;
546			resets = <&ccu RST_BUS_UART0>;
547			status = "disabled";
548		};
549
550		uart1: serial@5000400 {
551			compatible = "snps,dw-apb-uart";
552			reg = <0x05000400 0x400>;
553			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
554			reg-shift = <2>;
555			reg-io-width = <4>;
556			clocks = <&ccu CLK_BUS_UART1>;
557			resets = <&ccu RST_BUS_UART1>;
558			status = "disabled";
559		};
560
561		uart2: serial@5000800 {
562			compatible = "snps,dw-apb-uart";
563			reg = <0x05000800 0x400>;
564			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
565			reg-shift = <2>;
566			reg-io-width = <4>;
567			clocks = <&ccu CLK_BUS_UART2>;
568			resets = <&ccu RST_BUS_UART2>;
569			status = "disabled";
570		};
571
572		uart3: serial@5000c00 {
573			compatible = "snps,dw-apb-uart";
574			reg = <0x05000c00 0x400>;
575			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
576			reg-shift = <2>;
577			reg-io-width = <4>;
578			clocks = <&ccu CLK_BUS_UART3>;
579			resets = <&ccu RST_BUS_UART3>;
580			status = "disabled";
581		};
582
583		i2c0: i2c@5002000 {
584			compatible = "allwinner,sun50i-h6-i2c",
585				     "allwinner,sun6i-a31-i2c";
586			reg = <0x05002000 0x400>;
587			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
588			clocks = <&ccu CLK_BUS_I2C0>;
589			resets = <&ccu RST_BUS_I2C0>;
590			pinctrl-names = "default";
591			pinctrl-0 = <&i2c0_pins>;
592			status = "disabled";
593			#address-cells = <1>;
594			#size-cells = <0>;
595		};
596
597		i2c1: i2c@5002400 {
598			compatible = "allwinner,sun50i-h6-i2c",
599				     "allwinner,sun6i-a31-i2c";
600			reg = <0x05002400 0x400>;
601			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
602			clocks = <&ccu CLK_BUS_I2C1>;
603			resets = <&ccu RST_BUS_I2C1>;
604			pinctrl-names = "default";
605			pinctrl-0 = <&i2c1_pins>;
606			status = "disabled";
607			#address-cells = <1>;
608			#size-cells = <0>;
609		};
610
611		i2c2: i2c@5002800 {
612			compatible = "allwinner,sun50i-h6-i2c",
613				     "allwinner,sun6i-a31-i2c";
614			reg = <0x05002800 0x400>;
615			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
616			clocks = <&ccu CLK_BUS_I2C2>;
617			resets = <&ccu RST_BUS_I2C2>;
618			pinctrl-names = "default";
619			pinctrl-0 = <&i2c2_pins>;
620			status = "disabled";
621			#address-cells = <1>;
622			#size-cells = <0>;
623		};
624
625		spi0: spi@5010000 {
626			compatible = "allwinner,sun50i-h6-spi",
627				     "allwinner,sun8i-h3-spi";
628			reg = <0x05010000 0x1000>;
629			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
630			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
631			clock-names = "ahb", "mod";
632			dmas = <&dma 22>, <&dma 22>;
633			dma-names = "rx", "tx";
634			resets = <&ccu RST_BUS_SPI0>;
635			status = "disabled";
636			#address-cells = <1>;
637			#size-cells = <0>;
638		};
639
640		spi1: spi@5011000 {
641			compatible = "allwinner,sun50i-h6-spi",
642				     "allwinner,sun8i-h3-spi";
643			reg = <0x05011000 0x1000>;
644			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
645			clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
646			clock-names = "ahb", "mod";
647			dmas = <&dma 23>, <&dma 23>;
648			dma-names = "rx", "tx";
649			resets = <&ccu RST_BUS_SPI1>;
650			status = "disabled";
651			#address-cells = <1>;
652			#size-cells = <0>;
653		};
654
655		emac: ethernet@5020000 {
656			compatible = "allwinner,sun50i-h6-emac",
657				     "allwinner,sun50i-a64-emac";
658			syscon = <&syscon>;
659			reg = <0x05020000 0x10000>;
660			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
661			interrupt-names = "macirq";
662			resets = <&ccu RST_BUS_EMAC>;
663			reset-names = "stmmaceth";
664			clocks = <&ccu CLK_BUS_EMAC>;
665			clock-names = "stmmaceth";
666			status = "disabled";
667
668			mdio: mdio {
669				compatible = "snps,dwmac-mdio";
670				#address-cells = <1>;
671				#size-cells = <0>;
672			};
673		};
674
675		i2s1: i2s@5091000 {
676			#sound-dai-cells = <0>;
677			compatible = "allwinner,sun50i-h6-i2s";
678			reg = <0x05091000 0x1000>;
679			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
680			clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
681			clock-names = "apb", "mod";
682			dmas = <&dma 4>, <&dma 4>;
683			resets = <&ccu RST_BUS_I2S1>;
684			dma-names = "rx", "tx";
685			status = "disabled";
686		};
687
688		spdif: spdif@5093000 {
689			#sound-dai-cells = <0>;
690			compatible = "allwinner,sun50i-h6-spdif";
691			reg = <0x05093000 0x400>;
692			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
693			clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
694			clock-names = "apb", "spdif";
695			resets = <&ccu RST_BUS_SPDIF>;
696			dmas = <&dma 2>, <&dma 2>;
697			dma-names = "rx", "tx";
698			status = "disabled";
699		};
700
701		usb2otg: usb@5100000 {
702			compatible = "allwinner,sun50i-h6-musb",
703				     "allwinner,sun8i-a33-musb";
704			reg = <0x05100000 0x0400>;
705			clocks = <&ccu CLK_BUS_OTG>;
706			resets = <&ccu RST_BUS_OTG>;
707			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
708			interrupt-names = "mc";
709			phys = <&usb2phy 0>;
710			phy-names = "usb";
711			extcon = <&usb2phy 0>;
712			status = "disabled";
713		};
714
715		usb2phy: phy@5100400 {
716			compatible = "allwinner,sun50i-h6-usb-phy";
717			reg = <0x05100400 0x24>,
718			      <0x05101800 0x4>,
719			      <0x05311800 0x4>;
720			reg-names = "phy_ctrl",
721				    "pmu0",
722				    "pmu3";
723			clocks = <&ccu CLK_USB_PHY0>,
724				 <&ccu CLK_USB_PHY3>;
725			clock-names = "usb0_phy",
726				      "usb3_phy";
727			resets = <&ccu RST_USB_PHY0>,
728				 <&ccu RST_USB_PHY3>;
729			reset-names = "usb0_reset",
730				      "usb3_reset";
731			status = "disabled";
732			#phy-cells = <1>;
733		};
734
735		ehci0: usb@5101000 {
736			compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
737			reg = <0x05101000 0x100>;
738			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
739			clocks = <&ccu CLK_BUS_OHCI0>,
740				 <&ccu CLK_BUS_EHCI0>,
741				 <&ccu CLK_USB_OHCI0>;
742			resets = <&ccu RST_BUS_OHCI0>,
743				 <&ccu RST_BUS_EHCI0>;
744			phys = <&usb2phy 0>;
745			phy-names = "usb";
746			status = "disabled";
747		};
748
749		ohci0: usb@5101400 {
750			compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
751			reg = <0x05101400 0x100>;
752			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
753			clocks = <&ccu CLK_BUS_OHCI0>,
754				 <&ccu CLK_USB_OHCI0>;
755			resets = <&ccu RST_BUS_OHCI0>;
756			phys = <&usb2phy 0>;
757			phy-names = "usb";
758			status = "disabled";
759		};
760
761		dwc3: usb@5200000 {
762			compatible = "snps,dwc3";
763			reg = <0x05200000 0x10000>;
764			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
765			clocks = <&ccu CLK_BUS_XHCI>,
766				 <&ccu CLK_BUS_XHCI>,
767				 <&rtc CLK_OSC32K>;
768			clock-names = "ref", "bus_early", "suspend";
769			resets = <&ccu RST_BUS_XHCI>;
770			/*
771			 * The datasheet of the chip doesn't declare the
772			 * peripheral function, and there's no boards known
773			 * to have a USB Type-B port routed to the port.
774			 * In addition, no one has tested the peripheral
775			 * function yet.
776			 * So set the dr_mode to "host" in the DTSI file.
777			 */
778			dr_mode = "host";
779			phys = <&usb3phy>;
780			phy-names = "usb3-phy";
781			status = "disabled";
782		};
783
784		usb3phy: phy@5210000 {
785			compatible = "allwinner,sun50i-h6-usb3-phy";
786			reg = <0x5210000 0x10000>;
787			clocks = <&ccu CLK_USB_PHY1>;
788			resets = <&ccu RST_USB_PHY1>;
789			#phy-cells = <0>;
790			status = "disabled";
791		};
792
793		ehci3: usb@5311000 {
794			compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
795			reg = <0x05311000 0x100>;
796			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
797			clocks = <&ccu CLK_BUS_OHCI3>,
798				 <&ccu CLK_BUS_EHCI3>,
799				 <&ccu CLK_USB_OHCI3>;
800			resets = <&ccu RST_BUS_OHCI3>,
801				 <&ccu RST_BUS_EHCI3>;
802			phys = <&usb2phy 3>;
803			phy-names = "usb";
804			status = "disabled";
805		};
806
807		ohci3: usb@5311400 {
808			compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
809			reg = <0x05311400 0x100>;
810			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
811			clocks = <&ccu CLK_BUS_OHCI3>,
812				 <&ccu CLK_USB_OHCI3>;
813			resets = <&ccu RST_BUS_OHCI3>;
814			phys = <&usb2phy 3>;
815			phy-names = "usb";
816			status = "disabled";
817		};
818
819		hdmi: hdmi@6000000 {
820			compatible = "allwinner,sun50i-h6-dw-hdmi";
821			reg = <0x06000000 0x10000>;
822			reg-io-width = <1>;
823			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
824			clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
825				 <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>,
826				 <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>;
827			clock-names = "iahb", "isfr", "tmds", "cec", "hdcp",
828				      "hdcp-bus";
829			resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>;
830			reset-names = "ctrl", "hdcp";
831			phys = <&hdmi_phy>;
832			phy-names = "phy";
833			pinctrl-names = "default";
834			pinctrl-0 = <&hdmi_pins>;
835			status = "disabled";
836
837			ports {
838				#address-cells = <1>;
839				#size-cells = <0>;
840
841				hdmi_in: port@0 {
842					reg = <0>;
843
844					hdmi_in_tcon_top: endpoint {
845						remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
846					};
847				};
848
849				hdmi_out: port@1 {
850					reg = <1>;
851				};
852			};
853		};
854
855		hdmi_phy: hdmi-phy@6010000 {
856			compatible = "allwinner,sun50i-h6-hdmi-phy";
857			reg = <0x06010000 0x10000>;
858			clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>;
859			clock-names = "bus", "mod";
860			resets = <&ccu RST_BUS_HDMI>;
861			reset-names = "phy";
862			#phy-cells = <0>;
863		};
864
865		tcon_top: tcon-top@6510000 {
866			compatible = "allwinner,sun50i-h6-tcon-top";
867			reg = <0x06510000 0x1000>;
868			clocks = <&ccu CLK_BUS_TCON_TOP>,
869				 <&ccu CLK_TCON_TV0>;
870			clock-names = "bus",
871				      "tcon-tv0";
872			clock-output-names = "tcon-top-tv0";
873			resets = <&ccu RST_BUS_TCON_TOP>;
874			#clock-cells = <1>;
875
876			ports {
877				#address-cells = <1>;
878				#size-cells = <0>;
879
880				tcon_top_mixer0_in: port@0 {
881					#address-cells = <1>;
882					#size-cells = <0>;
883					reg = <0>;
884
885					tcon_top_mixer0_in_mixer0: endpoint@0 {
886						reg = <0>;
887						remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
888					};
889				};
890
891				tcon_top_mixer0_out: port@1 {
892					#address-cells = <1>;
893					#size-cells = <0>;
894					reg = <1>;
895
896					tcon_top_mixer0_out_tcon_tv: endpoint@2 {
897						reg = <2>;
898						remote-endpoint = <&tcon_tv_in_tcon_top_mixer0>;
899					};
900				};
901
902				tcon_top_hdmi_in: port@4 {
903					#address-cells = <1>;
904					#size-cells = <0>;
905					reg = <4>;
906
907					tcon_top_hdmi_in_tcon_tv: endpoint@0 {
908						reg = <0>;
909						remote-endpoint = <&tcon_tv_out_tcon_top>;
910					};
911				};
912
913				tcon_top_hdmi_out: port@5 {
914					reg = <5>;
915
916					tcon_top_hdmi_out_hdmi: endpoint {
917						remote-endpoint = <&hdmi_in_tcon_top>;
918					};
919				};
920			};
921		};
922
923		tcon_tv: lcd-controller@6515000 {
924			compatible = "allwinner,sun50i-h6-tcon-tv",
925				     "allwinner,sun8i-r40-tcon-tv";
926			reg = <0x06515000 0x1000>;
927			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
928			clocks = <&ccu CLK_BUS_TCON_TV0>,
929				 <&tcon_top CLK_TCON_TOP_TV0>;
930			clock-names = "ahb",
931				      "tcon-ch1";
932			resets = <&ccu RST_BUS_TCON_TV0>;
933			reset-names = "lcd";
934
935			ports {
936				#address-cells = <1>;
937				#size-cells = <0>;
938
939				tcon_tv_in: port@0 {
940					reg = <0>;
941
942					tcon_tv_in_tcon_top_mixer0: endpoint {
943						remote-endpoint = <&tcon_top_mixer0_out_tcon_tv>;
944					};
945				};
946
947				tcon_tv_out: port@1 {
948					#address-cells = <1>;
949					#size-cells = <0>;
950					reg = <1>;
951
952					tcon_tv_out_tcon_top: endpoint@1 {
953						reg = <1>;
954						remote-endpoint = <&tcon_top_hdmi_in_tcon_tv>;
955					};
956				};
957			};
958		};
959
960		rtc: rtc@7000000 {
961			compatible = "allwinner,sun50i-h6-rtc";
962			reg = <0x07000000 0x400>;
963			interrupt-parent = <&r_intc>;
964			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
965				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
966			clock-output-names = "osc32k", "osc32k-out", "iosc";
967			#clock-cells = <1>;
968		};
969
970		r_ccu: clock@7010000 {
971			compatible = "allwinner,sun50i-h6-r-ccu";
972			reg = <0x07010000 0x400>;
973			clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>,
974				 <&ccu CLK_PLL_PERIPH0>;
975			clock-names = "hosc", "losc", "iosc", "pll-periph";
976			#clock-cells = <1>;
977			#reset-cells = <1>;
978		};
979
980		r_watchdog: watchdog@7020400 {
981			compatible = "allwinner,sun50i-h6-wdt",
982				     "allwinner,sun6i-a31-wdt";
983			reg = <0x07020400 0x20>;
984			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
985			clocks = <&osc24M>;
986		};
987
988		r_intc: interrupt-controller@7021000 {
989			compatible = "allwinner,sun50i-h6-r-intc";
990			interrupt-controller;
991			#interrupt-cells = <3>;
992			reg = <0x07021000 0x400>;
993			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
994		};
995
996		r_pio: pinctrl@7022000 {
997			compatible = "allwinner,sun50i-h6-r-pinctrl";
998			reg = <0x07022000 0x400>;
999			interrupt-parent = <&r_intc>;
1000			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1001				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1002			clocks = <&r_ccu CLK_R_APB1>, <&osc24M>,
1003				 <&rtc CLK_OSC32K>;
1004			clock-names = "apb", "hosc", "losc";
1005			gpio-controller;
1006			#gpio-cells = <3>;
1007			interrupt-controller;
1008			#interrupt-cells = <3>;
1009
1010			r_i2c_pins: r-i2c-pins {
1011				pins = "PL0", "PL1";
1012				function = "s_i2c";
1013			};
1014
1015			r_ir_rx_pin: r-ir-rx-pin {
1016				pins = "PL9";
1017				function = "s_cir_rx";
1018			};
1019
1020			r_rsb_pins: r-rsb-pins {
1021				pins = "PL0", "PL1";
1022				function = "s_rsb";
1023			};
1024		};
1025
1026		r_ir: ir@7040000 {
1027				compatible = "allwinner,sun50i-h6-ir",
1028					     "allwinner,sun6i-a31-ir";
1029				reg = <0x07040000 0x400>;
1030				interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
1031				clocks = <&r_ccu CLK_R_APB1_IR>,
1032					 <&r_ccu CLK_IR>;
1033				clock-names = "apb", "ir";
1034				resets = <&r_ccu RST_R_APB1_IR>;
1035				pinctrl-names = "default";
1036				pinctrl-0 = <&r_ir_rx_pin>;
1037				status = "disabled";
1038		};
1039
1040		r_i2c: i2c@7081400 {
1041			compatible = "allwinner,sun50i-h6-i2c",
1042				     "allwinner,sun6i-a31-i2c";
1043			reg = <0x07081400 0x400>;
1044			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1045			clocks = <&r_ccu CLK_R_APB2_I2C>;
1046			resets = <&r_ccu RST_R_APB2_I2C>;
1047			pinctrl-names = "default";
1048			pinctrl-0 = <&r_i2c_pins>;
1049			status = "disabled";
1050			#address-cells = <1>;
1051			#size-cells = <0>;
1052		};
1053
1054		r_rsb: rsb@7083000 {
1055			compatible = "allwinner,sun8i-a23-rsb";
1056			reg = <0x07083000 0x400>;
1057			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1058			clocks = <&r_ccu CLK_R_APB2_RSB>;
1059			clock-frequency = <3000000>;
1060			resets = <&r_ccu RST_R_APB2_RSB>;
1061			pinctrl-names = "default";
1062			pinctrl-0 = <&r_rsb_pins>;
1063			status = "disabled";
1064			#address-cells = <1>;
1065			#size-cells = <0>;
1066		};
1067
1068		ths: thermal-sensor@5070400 {
1069			compatible = "allwinner,sun50i-h6-ths";
1070			reg = <0x05070400 0x100>;
1071			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1072			clocks = <&ccu CLK_BUS_THS>;
1073			clock-names = "bus";
1074			resets = <&ccu RST_BUS_THS>;
1075			nvmem-cells = <&ths_calibration>;
1076			nvmem-cell-names = "calibration";
1077			#thermal-sensor-cells = <1>;
1078		};
1079	};
1080
1081	thermal-zones {
1082		cpu-thermal {
1083			polling-delay-passive = <0>;
1084			polling-delay = <0>;
1085			thermal-sensors = <&ths 0>;
1086
1087			trips {
1088				cpu_alert: cpu-alert {
1089					temperature = <85000>;
1090					hysteresis = <2000>;
1091					type = "passive";
1092				};
1093
1094				cpu-crit {
1095					temperature = <100000>;
1096					hysteresis = <0>;
1097					type = "critical";
1098				};
1099			};
1100
1101			cooling-maps {
1102				map0 {
1103					trip = <&cpu_alert>;
1104					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1105							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1106							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1107							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1108				};
1109			};
1110		};
1111
1112		gpu-thermal {
1113			polling-delay-passive = <1000>;
1114			polling-delay = <2000>;
1115			thermal-sensors = <&ths 1>;
1116
1117			trips {
1118				gpu_alert0: gpu-alert-0 {
1119					temperature = <95000>;
1120					hysteresis = <2000>;
1121					type = "passive";
1122				};
1123
1124				gpu_alert1: gpu-alert-1 {
1125					temperature = <100000>;
1126					hysteresis = <2000>;
1127					type = "passive";
1128				};
1129
1130				gpu_alert2: gpu-alert-2 {
1131					temperature = <105000>;
1132					hysteresis = <2000>;
1133					type = "passive";
1134				};
1135
1136				gpu-crit {
1137					temperature = <115000>;
1138					hysteresis = <0>;
1139					type = "critical";
1140				};
1141			};
1142
1143			cooling-maps {
1144				// Forbid the GPU to go over 756MHz
1145				map0 {
1146					trip = <&gpu_alert0>;
1147					cooling-device = <&gpu 1 THERMAL_NO_LIMIT>;
1148				};
1149
1150				// Forbid the GPU to go over 624MHz
1151				map1 {
1152					trip = <&gpu_alert1>;
1153					cooling-device = <&gpu 2 THERMAL_NO_LIMIT>;
1154				};
1155
1156				// Forbid the GPU to go over 576MHz
1157				map2 {
1158					trip = <&gpu_alert2>;
1159					cooling-device = <&gpu 3 THERMAL_NO_LIMIT>;
1160				};
1161			};
1162		};
1163	};
1164};
1165