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/linux/Documentation/devicetree/bindings/hwmon/
H A Dmax6697.txt4 - compatible:
16 - reg: I2C address
20 - smbus-timeout-disable
21 Set to disable SMBus timeout. If not specified, SMBus timeout will be
23 - extended-range-enable
26 - beta-compensation-enable
30 - alert-mask
34 - over-temperature-mask
35 Over-temperature bit mask. Over-temperature reporting disabled for
38 If not specified, over-temperature reporting will be enabled for all
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H A Dst,stts751.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Javier Carrasco <javier.carrasco.cruz@gmail.com>
19 smbus-timeout-disable:
21 When set, the smbus timeout function will be disabled.
25 - compatible
26 - reg
31 - |
33 #address-cells = <1>;
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H A Djedec,jc42.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Jedec JC-42.4 compatible temperature sensors
10 - Jean Delvare <jdelvare@suse.com>
11 - Guenter Roeck <linux@roeck-us.net>
16 const: jedec,jc-42.4-temp
19 - compatible
24 - const: jedec,jc-42.4-temp
25 - items:
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/linux/drivers/i2c/busses/
H A Di2c-amd8111.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * SMBus 2.0 driver for AMD-8111 IO-Hub.
21 MODULE_DESCRIPTION("AMD8111 SMBus 2.0 driver");
61 #define AMD_EC_CMD_BD 0x83 /* disable burst mode */
68 static int amd_ec_wait_write(struct amd_smbus *smbus) in amd_ec_wait_write() argument
70 int timeout = 500; in amd_ec_wait_write() local
72 while ((inb(smbus->base + AMD_EC_SC) & AMD_EC_SC_IBF) && --timeout) in amd_ec_wait_write()
75 if (!timeout) { in amd_ec_wait_write()
76 dev_warn(&smbus->dev->dev, in amd_ec_wait_write()
77 "Timeout while waiting for IBF to clear\n"); in amd_ec_wait_write()
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H A Di2c-i801.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
6 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de>
16 * region SMBus Block proc. block
18 * ---------------------------------------------------------------------------
43 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes
51 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes
54 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes
55 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes
61 * Kaby Lake PCH-H (PCH) 0xa2a3 32 hard yes yes yes
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H A Di2c-ali15x3.c1 // SPDX-License-Identifier: GPL-2.0-or-later
34 ACPI-compliant Power Management Unit (PMU).
47 /* Note: we assume there can only be one ALI15X3, with one SMBus interface */
59 /* ALI15X3 SMBus address offsets */
127 - SMB I/O address is initialized in ali15x3_setup()
128 - Device is enabled in ali15x3_setup()
129 - We can use the addresses in ali15x3_setup()
133 The data sheet says that the address registers are read-only in ali15x3_setup()
143 /* Determine the address of the SMBus area */ in ali15x3_setup()
145 ali15x3_smba &= (0xffff & ~(ALI15X3_SMB_IOSIZE - 1)); in ali15x3_setup()
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H A Di2c-ali1535.c1 // SPDX-License-Identifier: GPL-2.0-or-later
18 the sequencing of the SMBus transactions has been modified
22 by comparing this driver to the i2c-ali15x3 driver.
26 ACPI-compliant Power Management Unit (PMU).
39 /* Note: we assume there can only be one ALI1535, with one SMBus interface */
52 /* ALI1535 SMBus address offsets */
87 #define ALI1535_DEV10B_EN 0x80 /* Enable 10-bit addressing in */
89 #define ALI1535_T_OUT 0x08 /* Time-out Command (write) */
90 #define ALI1535_A_HIGH_BIT9 0x08 /* Bit 9 of 10-bit address in */
91 /* Alert-Response-Address */
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H A Di2c-viapro.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
6 Copyright (C) 2005 - 2008 Jean Delvare <jdelvare@suse.de>
30 Note: we assume there can only be one device, with one SMBus interface.
50 /* SMBus address offsets */
62 /* SMBus data in configuration space can be found in two places,
84 MODULE_PARM_DESC(force, "Forcibly enable the SMBus. DANGEROUS!");
91 "Forcibly enable the SMBus at the given address. "
118 for (; i < I2C_SMBUS_BLOCK_MAX - 1; i++) in vt596_dump_regs()
127 /* Return -1 on error, 0 on success */
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H A Di2c-sis630.c1 // SPDX-License-Identifier: GPL-2.0-or-later
16 +------------------------+--------------------+-------------------+
18 +------------------------+--------------------+-------------------+
20 | SMBus registers offset | 0x80 | 0xE0 |
25 +------------------------+--------------------+-------------------+
28 Note: we assume there can only be one device, with one SMBus interface.
43 /* SIS630/730/964 SMBus registers */
58 #define MSTO_EN 0x40 /* Host Master Timeout Enable */
100 /* SMBus base address */
126 /* Make sure the SMBus host is ready to start transmitting. */ in sis630_transaction_start()
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H A Di2c-piix4.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl> and
11 Serverworks OSB4, CSB5, CSB6, HT-1000, HT-1100
13 AMD Hudson-2, ML, CZ
18 SMBus interfaces.
32 #include <linux/i2c-smbus.h>
37 #include <linux/platform_data/x86/amd-fch.h>
39 #include "i2c-piix4.h"
62 /* Multi-port constants */
76 * Hudson-2/Bolton port is always selected by bits 2:1 of register 0x2f.
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H A Di2c-stm32f7.c1 // SPDX-License-Identifier: GPL-2.0
14 * This driver is based on i2c-stm32f4.c
21 #include <linux/i2c-smbus.h>
39 #include "i2c-stm32.h"
187 * struct stm32f7_i2c_regs - i2c f7 registers backup
203 * struct stm32f7_i2c_spec - private i2c specification timing
225 * struct stm32f7_i2c_setup - private I2C timing setup parameters
245 * struct stm32f7_i2c_timings - private I2C output parameters
263 * struct stm32f7_i2c_msg - client specific data
264 * @addr: 8-bit or 10-bit slave addr, including r/w bit
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H A Di2c-mlxbf.c1 // SPDX-License-Identifier: GPL-2.0
57 * Note that the following SMBus, CAUSE, GPIO and PLL register addresses
59 * memory-mapped region whose addresses are specified in either the DT or
64 * SMBus Master core clock frequency. Timing configurations are
65 * strongly dependent on the core clock frequency of the SMBus
69 /* Reference clock for Bluefield - 156 MHz. */
109 /* Transfer timeout occurred. */
148 * Note that Smbus GWs are on GPIOs 30:25. Two pins are used to control
151 * SMBUS GW0 -> bits[26:25]
152 * SMBUS GW1 -> bits[28:27]
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H A Di2c-bcm-iproc.c1 // SPDX-License-Identifier: GPL-2.0-only
138 #define M_RX_FIFO_MAX_THLD_VALUE (M_TX_RX_FIFO_SIZE - 1)
233 if (iproc_i2c->idm_base) { in iproc_i2c_rd_reg()
234 spin_lock_irqsave(&iproc_i2c->idm_lock, flags); in iproc_i2c_rd_reg()
235 writel(iproc_i2c->ape_addr_mask, in iproc_i2c_rd_reg()
236 iproc_i2c->idm_base + IDM_CTRL_DIRECT_OFFSET); in iproc_i2c_rd_reg()
237 val = readl(iproc_i2c->base + offset); in iproc_i2c_rd_reg()
238 spin_unlock_irqrestore(&iproc_i2c->idm_lock, flags); in iproc_i2c_rd_reg()
240 val = readl(iproc_i2c->base + offset); in iproc_i2c_rd_reg()
251 if (iproc_i2c->idm_base) { in iproc_i2c_wr_reg()
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H A Di2c-at91.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * i2c Support for Atmel's AT91 Two-Wire Interface (TWI)
18 #include <linux/dma-mapping.h>
23 #define AT91_I2C_TIMEOUT msecs_to_jiffies(100) /* transfer timeout */
33 #define AT91_TWI_MSDIS BIT(3) /* Master Transfer Disable */
35 #define AT91_TWI_SVDIS BIT(5) /* Slave Transfer Disable */
36 #define AT91_TWI_QUICK BIT(6) /* SMBus quick command */
40 #define AT91_TWI_ACMDIS BIT(17) /* Alternative Command Mode Disable */
45 #define AT91_TWI_FIFODIS BIT(29) /* FIFO Disable */
80 #define AT91_TWI_IDR 0x0028 /* Interrupt Disable Register */
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H A Di2c-nomadik.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2009 ST-Ericsson SA
11 * - The memory bus only supports 32-bit accesses.
12 * - (only EyeQ5) A register must be configured for the I2C speed mode;
35 #define DRIVER_NAME "nmk-i2c"
74 #define I2C_MCR_A7 GENMASK(7, 1) /* 7-bit address */
75 #define I2C_MCR_EA10 GENMASK(10, 8) /* 10-bit Extended address */
88 /* Baud-rate counter register (BRCR) */
89 #define I2C_BRCR_BRCNT1 GENMASK(31, 16) /* Baud-rate counter 1 */
90 #define I2C_BRCR_BRCNT2 GENMASK(15, 0) /* Baud-rate counter 2 */
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H A Di2c-axxia.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * (-EINVAL) is returned.
69 #define MST_STATUS_TSS (1 << 7) /* Timeout */
84 #define SLV_ADDR_DEC_SA1M BIT(3) /* 10-bit addressing for addr_1 enabled */
86 #define SLV_ADDR_DEC_SA2M BIT(5) /* 10-bit addressing for addr_2 enabled */
98 #define SLV_FIFO_TNAK BIT(3) /* Timeout NACK */
121 * struct axxia_i2c_dev - I2C device context
158 int_en = readl(idev->base + MST_INT_ENABLE); in i2c_int_disable()
159 writel(int_en & ~mask, idev->base + MST_INT_ENABLE); in i2c_int_disable()
166 int_en = readl(idev->base + MST_INT_ENABLE); in i2c_int_enable()
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H A Di2c-designware-master.c1 // SPDX-License-Identifier: GPL-2.0-or-later
28 #include "i2c-designware-core.h"
37 regmap_write(dev->map, DW_IC_TX_TL, dev->tx_fifo_depth / 2); in i2c_dw_configure_fifo_master()
38 regmap_write(dev->map, DW_IC_RX_TL, 0); in i2c_dw_configure_fifo_master()
41 regmap_write(dev->map, DW_IC_CON, dev->master_cfg); in i2c_dw_configure_fifo_master()
48 struct i2c_timings *t = &dev->timings; in i2c_dw_set_timings_master()
57 ret = regmap_read(dev->map, DW_IC_COMP_PARAM_1, &comp_param1); in i2c_dw_set_timings_master()
63 sda_falling_time = t->sda_fall_ns ?: 300; /* ns */ in i2c_dw_set_timings_master()
64 scl_falling_time = t->scl_fall_ns ?: 300; /* ns */ in i2c_dw_set_timings_master()
67 if (!dev->ss_hcnt || !dev->ss_lcnt) { in i2c_dw_set_timings_master()
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/linux/drivers/net/ethernet/intel/e1000e/
H A Dich8lan.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
5 * 82562G-2 10/100 Network Connection
7 * 82562GT-2 10/100 Network Connection
9 * 82562V-2 10/100 Network Connection
10 * 82566DC-2 Gigabit Network Connection
12 * 82566DM-2 Gigabit Network Connection
19 * 82567LM-
1875 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT; e1000_acquire_swflag_ich8lan() local
3629 e1000_flash_cycle_ich8lan(struct e1000_hw * hw,u32 timeout) e1000_flash_cycle_ich8lan() argument
4645 u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT; e1000_erase_flash_bank_ich8lan() local
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H A Dich8lan.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
36 #define E1000_ICH_FWSM_PCIM2PCI 0x01000000 /* ME PCIm-to-PCI active */
93 /* bit24: RXDCTL thresholds granularity: 0 - cache lines, 1 - descriptors */
106 #define E1000_PCH2_RAR_ENTRIES 5 /* RAR[0], SHRA[0-3] */
107 #define E1000_PCH_LPT_RAR_ENTRIES 12 /* RAR[0], SHRA[0-10] */
144 /* Half-duplex collision counts */
165 /* SMBus Control Phy Register */
176 #define I218_ULP_CONFIG1_RESET_TO_SMBUS 0x0100 /* Reset to SMBus mode */
179 /* disable clear of sticky ULP on PERST */
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/linux/drivers/usb/host/
H A Dpci-quirks.c1 // SPDX-License-Identifier: GPL-2.0
4 * Some of it includes work-arounds for PCI hardware and BIOS quirks.
5 * It may need to run early during booting -- before USB would normally
6 * initialize -- to ensure that Linux doesn't use any legacy modes.
22 #include "pci-quirks.h"
23 #include "xhci-ext-caps.h"
146 * amd_chipset_sb_type_init - initialize amd chipset southbridge type
148 * AMD FCH/SB generation and revision is identified by SMBus controller
156 pinfo->sb_type.gen = AMD_CHIPSET_UNKNOWN; in amd_chipset_sb_type_init()
158 pinfo->smbus_dev = pci_get_device(PCI_VENDOR_ID_ATI, in amd_chipset_sb_type_init()
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/linux/drivers/hwmon/
H A Djc42.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * jc42.c - driver for Jedec JC42.4 compliant temperature sensors
68 /* SMBUS register */
69 #define SMBUS_STMOUT BIT(7) /* SMBus time-out, active low */
188 #define JC42_TEMP_MIN_EXTENDED (-4000
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H A Dstts751.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2016-2017 Istituto Italiano di Tecnologia - RBCS - EDL
17 #include <linux/hwmon-sysfs.h>
32 0x48, 0x49, 0x38, 0x39, /* STTS751-0 */
33 0x4A, 0x4B, 0x3A, 0x3B, /* STTS751-1 */
104 * vice-vers. They are (mostly) taken from lm90 driver. Unit is in mC.
120 switch (priv->interval) { in stts751_adjust_resolution()
135 if (priv->res == res) in stts751_adjust_resolution()
138 priv->config &= ~STTS751_CONF_RES_MASK; in stts751_adjust_resolution()
139 priv->config |= res << STTS751_CONF_RES_SHIFT; in stts751_adjust_resolution()
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/linux/drivers/misc/eeprom/
H A Didt_89hpesx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2016 T-Platforms. All Rights Reserved.
5 * IDT PCIe-switch NTB Linux driver
8 * Serge Semin <fancer.lancer@gmail.com>, <Sergey.Semin@t-platforms.ru>
11 * NOTE of the IDT 89HPESx SMBus-slave interface driver
13 * IDT PCIe-switches. IDT provides a simple SMBus interface to perform IO-
15 * SMBus of switches. Using that interface this the driver creates a simple
16 * binary sysfs-file in the device directory:
17 * /sys/bus/i2c/devices/<bus>-<devaddr>/eeprom
18 * In case if read-only flag is specified in the dts-node of device desription,
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/linux/drivers/pci/
H A Dquirks.c1 // SPDX-License-Identifier: GPL-2.0
3 * This file contains work-arounds for many known PCI hardware bugs.
5 * should be handled in arch-specific code.
22 #include <linux/isa-dma.h> /* isa_dma_bridge_buggy */
41 if (test_bit(PCI_LINK_LBMS_SEEN, &dev->priv_flags)) in pcie_lbms_seen()
102 int ret = -ENOTTY; in pcie_failed_link_retrain()
105 !pcie_cap_has_lnkctl2(dev) || !dev->link_active_reporting) in pcie_failed_link_retrain()
112 pci_info(dev, "broken device, retraining non-functional downstream link at 2.5GT/s\n"); in pcie_failed_link_retrain()
173 if ((f->class == (u32) (dev->class >> f->class_shift) || in pci_do_fixups()
174 f->class == (u32) PCI_ANY_ID) && in pci_do_fixups()
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/linux/drivers/rtc/
H A Drtc-ds1374.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * RTC client/driver for the Maxim/Dallas DS1374 Real-Time Clock over I2C
9 * Copyright (C) 2006-2007 Freescale Semiconductor
14 * recommended in .../Documentation/i2c/writing-clients.rst section
15 * "Sending and receiving", using SMBus level communication is preferred.
93 return -EINVAL; in ds1374_read_rtc()
100 return -EIO; in ds1374_read_rtc()
102 for (i = nbytes - 1, *time = 0; i >= 0; i--) in ds1374_read_rtc()
116 return -EINVAL; in ds1374_write_rtc()
137 dev_warn(&client->dev, in ds1374_check_rtc_status()
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