Lines Matching +full:smbus +full:- +full:timeout +full:- +full:disable
1 // SPDX-License-Identifier: GPL-2.0-only
138 #define M_RX_FIFO_MAX_THLD_VALUE (M_TX_RX_FIFO_SIZE - 1)
233 if (iproc_i2c->idm_base) {
234 spin_lock_irqsave(&iproc_i2c->idm_lock, flags);
235 writel(iproc_i2c->ape_addr_mask,
236 iproc_i2c->idm_base + IDM_CTRL_DIRECT_OFFSET);
237 val = readl(iproc_i2c->base + offset);
238 spin_unlock_irqrestore(&iproc_i2c->idm_lock, flags);
240 val = readl(iproc_i2c->base + offset);
251 if (iproc_i2c->idm_base) {
252 spin_lock_irqsave(&iproc_i2c->idm_lock, flags);
253 writel(iproc_i2c->ape_addr_mask,
254 iproc_i2c->idm_base + IDM_CTRL_DIRECT_OFFSET);
255 writel(val, iproc_i2c->base + offset);
256 spin_unlock_irqrestore(&iproc_i2c->idm_lock, flags);
258 writel(val, iproc_i2c->base + offset);
267 iproc_i2c->tx_underrun = 0;
296 val |= (iproc_i2c->slave->addr << S_CFG_NIC_SMB_ADDR3_SHIFT);
310 iproc_i2c->slave_int_mask = val;
334 if (!iproc_i2c->slave_rx_only) {
341 dev_warn(iproc_i2c->device,
343 "slave random stretch time timeout\n" :
353 dev_warn(iproc_i2c->device, "Slave aborted read transaction\n");
358 /* re-initialize i2c for recovery */
379 /* Start of SMBUS Master write */
380 i2c_slave_event(iproc_i2c->slave,
382 iproc_i2c->rx_start_rcvd = true;
383 iproc_i2c->slave_read_complete = false;
385 iproc_i2c->rx_start_rcvd) {
386 /* Middle of SMBUS Master write */
387 i2c_slave_event(iproc_i2c->slave,
390 iproc_i2c->rx_start_rcvd) {
391 /* End of SMBUS Master write */
392 if (iproc_i2c->slave_rx_only)
393 i2c_slave_event(iproc_i2c->slave,
397 i2c_slave_event(iproc_i2c->slave, I2C_SLAVE_STOP,
400 iproc_i2c->rx_start_rcvd = false;
401 iproc_i2c->slave_read_complete = true;
419 if (!iproc_i2c->slave_rx_only && iproc_i2c->slave_read_complete) {
421 * In case of single byte master-read request,
430 iproc_i2c->tx_underrun = 0;
431 iproc_i2c->slave_int_mask |= BIT(IE_S_TX_UNDERRUN_SHIFT);
440 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, iproc_i2c->slave_int_mask);
450 iproc_i2c->tx_underrun++;
451 if (iproc_i2c->tx_underrun == 1)
452 /* Start of SMBUS for Master Read */
453 i2c_slave_event(iproc_i2c->slave,
458 i2c_slave_event(iproc_i2c->slave,
475 * Disable interrupt for TX FIFO becomes empty and
476 * less than PKT_LENGTH bytes were output on the SMBUS
478 iproc_i2c->slave_int_mask &= ~BIT(IE_S_TX_UNDERRUN_SHIFT);
483 /* End of SMBUS for Master Read */
495 i2c_slave_event(iproc_i2c->slave, I2C_SLAVE_STOP, &value);
507 * Slave events in case of master-write, master-write-read and,
508 * master-read
510 * Master-write : only IS_S_RX_EVENT_SHIFT event
511 * Master-write-read: both IS_S_RX_EVENT_SHIFT and IS_S_RD_EVENT_SHIFT
513 * Master-read : both IS_S_RX_EVENT_SHIFT and IS_S_RD_EVENT_SHIFT
524 /* disable slave interrupts */
526 val &= ~iproc_i2c->slave_int_mask;
530 /* Master-write-read request */
531 iproc_i2c->slave_rx_only = false;
533 /* Master-write request only */
534 iproc_i2c->slave_rx_only = true;
537 tasklet_schedule(&iproc_i2c->slave_rx_tasklet);
551 struct i2c_msg *msg = iproc_i2c->msg;
555 while (iproc_i2c->rx_bytes < msg->len) {
562 msg->buf[iproc_i2c->rx_bytes] =
564 iproc_i2c->rx_bytes++;
570 struct i2c_msg *msg = iproc_i2c->msg;
571 unsigned int tx_bytes = msg->len - iproc_i2c->tx_bytes;
579 unsigned int idx = iproc_i2c->tx_bytes + i;
581 val = msg->buf[idx];
584 if (idx == msg->len - 1) {
587 if (iproc_i2c->irq) {
592 * disable TX FIFO underrun interrupt
606 iproc_i2c->tx_bytes += tx_bytes;
611 struct i2c_msg *msg = iproc_i2c->msg;
615 bytes_left = msg->len - iproc_i2c->rx_bytes;
617 if (iproc_i2c->irq) {
618 /* finished reading all data, disable rx thld event */
623 } else if (bytes_left < iproc_i2c->thld_bytes) {
629 iproc_i2c->thld_bytes = bytes_left;
632 * bytes_left >= iproc_i2c->thld_bytes,
634 * It will remain as iproc_i2c->thld_bytes itself
651 iproc_i2c->xfer_is_done = 1;
652 if (iproc_i2c->irq)
653 complete(&iproc_i2c->done);
708 /* disable all interrupts */
731 dev_err(iproc_i2c->device, "lost bus arbitration\n");
732 return -EAGAIN;
735 dev_err(iproc_i2c->device, "NAK addr:0x%02x\n", msg->addr);
736 return -ENXIO;
739 dev_err(iproc_i2c->device, "NAK data\n");
740 return -ENXIO;
743 dev_err(iproc_i2c->device, "bus timeout\n");
744 return -ETIMEDOUT;
747 dev_err(iproc_i2c->device, "FIFO under-run\n");
748 return -ENXIO;
751 dev_err(iproc_i2c->device, "RX FIFO full\n");
752 return -ETIMEDOUT;
755 dev_err(iproc_i2c->device, "unknown error code=%d\n", val);
757 /* re-initialize i2c for recovery */
762 return -EIO;
776 if (iproc_i2c->irq) {
777 time_left = wait_for_completion_timeout(&iproc_i2c->done,
779 /* disable all interrupts */
784 synchronize_irq(iproc_i2c->irq);
787 unsigned long timeout = jiffies + time_left;
795 if (time_after(jiffies, timeout)) {
802 } while (!iproc_i2c->xfer_is_done);
805 if (!time_left && !iproc_i2c->xfer_is_done) {
809 return -ETIMEDOUT;
824 * If 'process_call' is true, then this is a multi-msg transfer that requires
841 dev_warn(iproc_i2c->device, "bus is busy\n");
842 return -EBUSY;
845 iproc_i2c->msg = msg;
853 * loading up to TX FIFO size - 1 bytes of data since the first byte
856 tx_bytes = min_t(unsigned int, msg->len, M_TX_RX_FIFO_SIZE - 1);
857 if (!(msg->flags & I2C_M_RD)) {
859 val = msg->buf[i];
862 if (!process_call && (i == msg->len - 1))
867 iproc_i2c->tx_bytes = tx_bytes;
873 iproc_i2c->msg = msg; /* point to second msg */
886 if (iproc_i2c->irq)
887 reinit_completion(&iproc_i2c->done);
889 iproc_i2c->xfer_is_done = 0;
903 if (!process_call && !(msg->flags & I2C_M_RD) &&
904 msg->len > iproc_i2c->tx_bytes)
913 if (msg->len == 0) {
914 /* SMBUS QUICK Command (Read/Write) */
916 } else if (msg->flags & I2C_M_RD) {
919 iproc_i2c->rx_bytes = 0;
920 if (msg->len > M_RX_FIFO_MAX_THLD_VALUE)
921 iproc_i2c->thld_bytes = M_RX_FIFO_THLD_VALUE;
923 iproc_i2c->thld_bytes = msg->len;
928 tmp |= iproc_i2c->thld_bytes << M_FIFO_RX_THLD_SHIFT;
938 (msg->len << M_CMD_RD_CNT_SHIFT);
943 if (iproc_i2c->irq)
960 dev_err(iproc_i2c->device, "Invalid repeated start\n");
961 return -EOPNOTSUPP;
967 dev_err(iproc_i2c->device, "xfer failed\n");
980 if (adap->algo->reg_slave)
988 struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(slave->adapter);
990 if (iproc_i2c->slave)
991 return -EBUSY;
993 if (slave->flags & I2C_CLIENT_TEN)
994 return -EAFNOSUPPORT;
996 iproc_i2c->slave = slave;
998 tasklet_init(&iproc_i2c->slave_rx_tasklet, slave_rx_tasklet_fn,
1008 struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(slave->adapter);
1011 if (!iproc_i2c->slave)
1012 return -EINVAL;
1014 disable_irq(iproc_i2c->irq);
1016 tasklet_kill(&iproc_i2c->slave_rx_tasklet);
1018 /* disable all slave interrupts */
1036 iproc_i2c->slave = NULL;
1038 enable_irq(iproc_i2c->irq);
1060 int ret = of_property_read_u32(iproc_i2c->device->of_node,
1061 "clock-frequency", &bus_speed);
1063 dev_info(iproc_i2c->device,
1064 "unable to interpret clock-frequency DT property\n");
1069 return dev_err_probe(iproc_i2c->device, -EINVAL,
1070 "%d Hz not supported (out of 100-400 kHz range)\n",
1077 iproc_i2c->bus_speed = bus_speed;
1083 dev_info(iproc_i2c->device, "bus set to %u Hz\n", bus_speed);
1094 iproc_i2c = devm_kzalloc(&pdev->dev, sizeof(*iproc_i2c),
1097 return -ENOMEM;
1100 iproc_i2c->device = &pdev->dev;
1101 iproc_i2c->type = (kernel_ulong_t)of_device_get_match_data(&pdev->dev);
1102 init_completion(&iproc_i2c->done);
1104 iproc_i2c->base = devm_platform_ioremap_resource(pdev, 0);
1105 if (IS_ERR(iproc_i2c->base))
1106 return PTR_ERR(iproc_i2c->base);
1108 if (iproc_i2c->type == IPROC_I2C_NIC) {
1109 iproc_i2c->idm_base = devm_platform_ioremap_resource(pdev, 1);
1110 if (IS_ERR(iproc_i2c->idm_base))
1111 return PTR_ERR(iproc_i2c->idm_base);
1113 ret = of_property_read_u32(iproc_i2c->device->of_node,
1114 "brcm,ape-hsls-addr-mask",
1115 &iproc_i2c->ape_addr_mask);
1117 return dev_err_probe(iproc_i2c->device, ret,
1118 "'brcm,ape-hsls-addr-mask' missing\n");
1120 spin_lock_init(&iproc_i2c->idm_lock);
1135 ret = devm_request_irq(iproc_i2c->device, irq,
1136 bcm_iproc_i2c_isr, 0, pdev->name,
1139 return dev_err_probe(iproc_i2c->device, ret,
1142 iproc_i2c->irq = irq;
1144 dev_warn(iproc_i2c->device,
1150 adap = &iproc_i2c->adapter;
1152 snprintf(adap->name, sizeof(adap->name), "Broadcom iProc (%s)",
1153 of_node_full_name(iproc_i2c->device->of_node));
1154 adap->algo = &bcm_iproc_algo;
1155 adap->quirks = &bcm_iproc_i2c_quirks;
1156 adap->dev.parent = &pdev->dev;
1157 adap->dev.of_node = pdev->dev.of_node;
1166 if (iproc_i2c->irq) {
1173 synchronize_irq(iproc_i2c->irq);
1176 i2c_del_adapter(&iproc_i2c->adapter);
1184 if (iproc_i2c->irq) {
1191 synchronize_irq(iproc_i2c->irq);
1194 /* now disable the controller */
1207 * sleep, so re-initialize the block here
1214 val |= (iproc_i2c->bus_speed == I2C_MAX_FAST_MODE_FREQ) << TIM_CFG_MODE_400_SHIFT;
1229 .compatible = "brcm,iproc-i2c",
1232 .compatible = "brcm,iproc-nic-i2c",
1241 .name = "bcm-iproc-i2c",